1 /* $OpenBSD: cpuconf.h,v 1.4 2008/09/11 02:38:14 kevlo Exp $ */ 2 /* $NetBSD: cpuconf.h,v 1.7 2003/05/23 00:57:24 ichiro Exp $ */ 3 4 /* 5 * Copyright (c) 2002 Wasabi Systems, Inc. 6 * All rights reserved. 7 * 8 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed for the NetBSD Project by 21 * Wasabi Systems, Inc. 22 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 23 * or promote products derived from this software without specific prior 24 * written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #ifndef _ARM_CPUCONF_H_ 40 #define _ARM_CPUCONF_H_ 41 42 /* 43 * IF YOU CHANGE THIS FILE, MAKE SURE TO UPDATE THE DEFINITION OF 44 * "PMAP_NEEDS_PTE_SYNC" IN <arm/arm/pmap.h> FOR THE CPU TYPE 45 * YOU ARE ADDING SUPPORT FOR. 46 */ 47 48 /* 49 * Determine which ARM architecture versions are configured. 50 */ 51 #if (defined(CPU_ARM2) || defined(CPU_ARM250) || defined(CPU_ARM3)) 52 #define ARM_ARCH_2 1 53 #else 54 #define ARM_ARCH_2 0 55 #endif 56 57 #if (defined(CPU_ARM6) || defined(CPU_ARM7)) 58 #define ARM_ARCH_3 1 59 #else 60 #define ARM_ARCH_3 0 61 #endif 62 63 #if (defined(CPU_ARM7TDMI) || defined(CPU_ARM8) || defined(CPU_ARM9) || \ 64 defined(CPU_SA110) || defined(CPU_SA1100) || defined(CPU_SA1110) || \ 65 defined(CPU_IXP12X0) || defined(CPU_XSCALE_IXP425)) 66 #define ARM_ARCH_4 1 67 #else 68 #define ARM_ARCH_4 0 69 #endif 70 71 #if (defined(CPU_ARM9E) || defined(CPU_ARM10) || \ 72 defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \ 73 defined(CPU_XSCALE_PXA2X0)) 74 #define ARM_ARCH_5 1 75 #else 76 #define ARM_ARCH_5 0 77 #endif 78 79 /* 80 * Define which MMU classes are configured: 81 * 82 * ARM_MMU_MEMC Prehistoric, external memory controller 83 * and MMU for ARMv2 CPUs. 84 * 85 * ARM_MMU_GENERIC Generic ARM MMU, compatible with ARM6. 86 * 87 * ARM_MMU_SA1 StrongARM SA-1 MMU. Compatible with generic 88 * ARM MMU, but has no write-through cache mode. 89 * 90 * ARM_MMU_XSCALE XScale MMU. Compatible with generic ARM 91 * MMU, but also has several extensions which 92 * require different PTE layout to use. 93 */ 94 #if (defined(CPU_ARM2) || defined(CPU_ARM250) || defined(CPU_ARM3)) 95 #define ARM_MMU_MEMC 1 96 #else 97 #define ARM_MMU_MEMC 0 98 #endif 99 100 #if (defined(CPU_ARM6) || defined(CPU_ARM7) || defined(CPU_ARM7TDMI) || \ 101 defined(CPU_ARM8) || defined(CPU_ARM9) || defined(CPU_ARM9E) || \ 102 defined(CPU_ARM10)) 103 #define ARM_MMU_GENERIC 1 104 #else 105 #define ARM_MMU_GENERIC 0 106 #endif 107 108 #if (defined(CPU_SA110) || defined(CPU_SA1100) || defined(CPU_SA1110) ||\ 109 defined(CPU_IXP12X0)) 110 #define ARM_MMU_SA1 1 111 #else 112 #define ARM_MMU_SA1 0 113 #endif 114 115 #if (defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \ 116 defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425)) 117 #define ARM_MMU_XSCALE 1 118 #else 119 #define ARM_MMU_XSCALE 0 120 #endif 121 122 #define ARM_NMMUS (ARM_MMU_MEMC + ARM_MMU_GENERIC + \ 123 ARM_MMU_SA1 + ARM_MMU_XSCALE) 124 125 /* 126 * Define features that may be present on a subset of CPUs 127 * 128 * ARM_XSCALE_PMU Performance Monitoring Unit on 80200 and 80321 129 */ 130 131 #if (defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321)) 132 #define ARM_XSCALE_PMU 1 133 #else 134 #define ARM_XSCALE_PMU 0 135 #endif 136 137 #endif /* _ARM_CPUCONF_H_ */ 138