1 /* $OpenBSD: pci_machdep.c,v 1.67 2017/10/14 04:44:43 jsg Exp $ */ 2 /* $NetBSD: pci_machdep.c,v 1.3 2003/05/07 21:33:58 fvdl Exp $ */ 3 4 /*- 5 * Copyright (c) 1997, 1998 The NetBSD Foundation, Inc. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to The NetBSD Foundation 9 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 10 * NASA Ames Research Center. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * Copyright (c) 1996 Christopher G. Demetriou. All rights reserved. 36 * Copyright (c) 1994 Charles M. Hannum. All rights reserved. 37 * 38 * Redistribution and use in source and binary forms, with or without 39 * modification, are permitted provided that the following conditions 40 * are met: 41 * 1. Redistributions of source code must retain the above copyright 42 * notice, this list of conditions and the following disclaimer. 43 * 2. Redistributions in binary form must reproduce the above copyright 44 * notice, this list of conditions and the following disclaimer in the 45 * documentation and/or other materials provided with the distribution. 46 * 3. All advertising materials mentioning features or use of this software 47 * must display the following acknowledgement: 48 * This product includes software developed by Charles M. Hannum. 49 * 4. The name of the author may not be used to endorse or promote products 50 * derived from this software without specific prior written permission. 51 * 52 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 53 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 54 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 55 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 56 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 57 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 58 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 59 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 60 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 61 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 62 */ 63 64 /* 65 * Machine-specific functions for PCI autoconfiguration. 66 */ 67 68 #include <sys/param.h> 69 #include <sys/systm.h> 70 #include <sys/extent.h> 71 #include <sys/malloc.h> 72 73 #include <machine/bus.h> 74 75 #include <machine/pio.h> 76 #include <machine/intr.h> 77 #include <machine/biosvar.h> 78 79 #include <dev/isa/isareg.h> 80 #include <dev/pci/pcivar.h> 81 #include <dev/pci/pcireg.h> 82 #include <dev/pci/pcidevs.h> 83 #include <dev/pci/ppbreg.h> 84 85 #include "ioapic.h" 86 87 #if NIOAPIC > 0 88 #include <machine/i82093var.h> 89 #include <machine/mpbiosvar.h> 90 #endif 91 92 /* 93 * Memory Mapped Configuration space access. 94 * 95 * Since mapping the whole configuration space will cost us up to 96 * 256MB of kernel virtual memory, we use seperate mappings per bus. 97 * The mappings are created on-demand, such that we only use kernel 98 * virtual memory for busses that are actually present. 99 */ 100 bus_addr_t pci_mcfg_addr; 101 int pci_mcfg_min_bus, pci_mcfg_max_bus; 102 bus_space_tag_t pci_mcfgt = X86_BUS_SPACE_MEM; 103 bus_space_handle_t pci_mcfgh[256]; 104 void pci_mcfg_map_bus(int); 105 106 struct mutex pci_conf_lock = MUTEX_INITIALIZER(IPL_HIGH); 107 108 #define PCI_CONF_LOCK() \ 109 do { \ 110 mtx_enter(&pci_conf_lock); \ 111 } while (0) 112 113 #define PCI_CONF_UNLOCK() \ 114 do { \ 115 mtx_leave(&pci_conf_lock); \ 116 } while (0) 117 118 #define PCI_MODE1_ENABLE 0x80000000UL 119 #define PCI_MODE1_ADDRESS_REG 0x0cf8 120 #define PCI_MODE1_DATA_REG 0x0cfc 121 122 /* 123 * PCI doesn't have any special needs; just use the generic versions 124 * of these functions. 125 */ 126 struct bus_dma_tag pci_bus_dma_tag = { 127 NULL, /* _may_bounce */ 128 _bus_dmamap_create, 129 _bus_dmamap_destroy, 130 _bus_dmamap_load, 131 _bus_dmamap_load_mbuf, 132 _bus_dmamap_load_uio, 133 _bus_dmamap_load_raw, 134 _bus_dmamap_unload, 135 _bus_dmamap_sync, 136 _bus_dmamem_alloc, 137 _bus_dmamem_alloc_range, 138 _bus_dmamem_free, 139 _bus_dmamem_map, 140 _bus_dmamem_unmap, 141 _bus_dmamem_mmap, 142 }; 143 144 void 145 pci_attach_hook(struct device *parent, struct device *self, 146 struct pcibus_attach_args *pba) 147 { 148 pci_chipset_tag_t pc = pba->pba_pc; 149 pcitag_t tag; 150 pcireg_t id, class; 151 152 if (pba->pba_bus != 0) 153 return; 154 155 /* 156 * In order to decide whether the system supports MSI we look 157 * at the host bridge, which should be device 0 function 0 on 158 * bus 0. It is better to not enable MSI on systems that 159 * support it than the other way around, so be conservative 160 * here. So we don't enable MSI if we don't find a host 161 * bridge there. We also deliberately don't enable MSI on 162 * chipsets from low-end manifacturers like VIA and SiS. 163 */ 164 tag = pci_make_tag(pc, 0, 0, 0); 165 id = pci_conf_read(pc, tag, PCI_ID_REG); 166 class = pci_conf_read(pc, tag, PCI_CLASS_REG); 167 168 if (PCI_CLASS(class) != PCI_CLASS_BRIDGE || 169 PCI_SUBCLASS(class) != PCI_SUBCLASS_BRIDGE_HOST) 170 return; 171 172 switch (PCI_VENDOR(id)) { 173 case PCI_VENDOR_INTEL: 174 /* 175 * In the wonderful world of virtualization you can 176 * have the latest 64-bit AMD multicore CPU behind a 177 * prehistoric Intel host bridge. Give them what they 178 * deserve. 179 */ 180 switch (PCI_PRODUCT(id)) { 181 case PCI_PRODUCT_INTEL_82441FX: /* QEMU */ 182 case PCI_PRODUCT_INTEL_82443BX: /* VMWare */ 183 break; 184 default: 185 pba->pba_flags |= PCI_FLAGS_MSI_ENABLED; 186 break; 187 } 188 break; 189 case PCI_VENDOR_NVIDIA: 190 case PCI_VENDOR_AMD: 191 pba->pba_flags |= PCI_FLAGS_MSI_ENABLED; 192 break; 193 } 194 195 /* 196 * Don't enable MSI on a HyperTransport bus. In order to 197 * determine that bus 0 is a HyperTransport bus, we look at 198 * device 24 function 0, which is the HyperTransport 199 * host/primary interface integrated on most 64-bit AMD CPUs. 200 * If that device has a HyperTransport capability, bus 0 must 201 * be a HyperTransport bus and we disable MSI. 202 */ 203 tag = pci_make_tag(pc, 0, 24, 0); 204 if (pci_get_capability(pc, tag, PCI_CAP_HT, NULL, NULL)) 205 pba->pba_flags &= ~PCI_FLAGS_MSI_ENABLED; 206 } 207 208 int 209 pci_bus_maxdevs(pci_chipset_tag_t pc, int busno) 210 { 211 return (32); 212 } 213 214 pcitag_t 215 pci_make_tag(pci_chipset_tag_t pc, int bus, int device, int function) 216 { 217 if (bus >= 256 || device >= 32 || function >= 8) 218 panic("pci_make_tag: bad request"); 219 220 return (PCI_MODE1_ENABLE | 221 (bus << 16) | (device << 11) | (function << 8)); 222 } 223 224 void 225 pci_decompose_tag(pci_chipset_tag_t pc, pcitag_t tag, int *bp, int *dp, int *fp) 226 { 227 if (bp != NULL) 228 *bp = (tag >> 16) & 0xff; 229 if (dp != NULL) 230 *dp = (tag >> 11) & 0x1f; 231 if (fp != NULL) 232 *fp = (tag >> 8) & 0x7; 233 } 234 235 int 236 pci_conf_size(pci_chipset_tag_t pc, pcitag_t tag) 237 { 238 int bus; 239 240 if (pci_mcfg_addr) { 241 pci_decompose_tag(pc, tag, &bus, NULL, NULL); 242 if (bus >= pci_mcfg_min_bus && bus <= pci_mcfg_max_bus) 243 return PCIE_CONFIG_SPACE_SIZE; 244 } 245 246 return PCI_CONFIG_SPACE_SIZE; 247 } 248 249 void 250 pci_mcfg_map_bus(int bus) 251 { 252 if (pci_mcfgh[bus]) 253 return; 254 255 if (bus_space_map(pci_mcfgt, pci_mcfg_addr + (bus << 20), 1 << 20, 256 0, &pci_mcfgh[bus])) 257 panic("pci_conf_read: cannot map mcfg space"); 258 } 259 260 pcireg_t 261 pci_conf_read(pci_chipset_tag_t pc, pcitag_t tag, int reg) 262 { 263 pcireg_t data; 264 int bus; 265 266 KASSERT((reg & 0x3) == 0); 267 268 if (pci_mcfg_addr && reg >= PCI_CONFIG_SPACE_SIZE) { 269 pci_decompose_tag(pc, tag, &bus, NULL, NULL); 270 if (bus >= pci_mcfg_min_bus && bus <= pci_mcfg_max_bus) { 271 pci_mcfg_map_bus(bus); 272 data = bus_space_read_4(pci_mcfgt, pci_mcfgh[bus], 273 (tag & 0x000ff00) << 4 | reg); 274 return data; 275 } 276 } 277 278 PCI_CONF_LOCK(); 279 outl(PCI_MODE1_ADDRESS_REG, tag | reg); 280 data = inl(PCI_MODE1_DATA_REG); 281 outl(PCI_MODE1_ADDRESS_REG, 0); 282 PCI_CONF_UNLOCK(); 283 284 return data; 285 } 286 287 void 288 pci_conf_write(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t data) 289 { 290 int bus; 291 292 KASSERT((reg & 0x3) == 0); 293 294 if (pci_mcfg_addr && reg >= PCI_CONFIG_SPACE_SIZE) { 295 pci_decompose_tag(pc, tag, &bus, NULL, NULL); 296 if (bus >= pci_mcfg_min_bus && bus <= pci_mcfg_max_bus) { 297 pci_mcfg_map_bus(bus); 298 bus_space_write_4(pci_mcfgt, pci_mcfgh[bus], 299 (tag & 0x000ff00) << 4 | reg, data); 300 return; 301 } 302 } 303 304 PCI_CONF_LOCK(); 305 outl(PCI_MODE1_ADDRESS_REG, tag | reg); 306 outl(PCI_MODE1_DATA_REG, data); 307 outl(PCI_MODE1_ADDRESS_REG, 0); 308 PCI_CONF_UNLOCK(); 309 } 310 311 void msi_hwmask(struct pic *, int); 312 void msi_hwunmask(struct pic *, int); 313 void msi_addroute(struct pic *, struct cpu_info *, int, int, int); 314 void msi_delroute(struct pic *, struct cpu_info *, int, int, int); 315 316 struct pic msi_pic = { 317 {0, {NULL}, NULL, 0, "msi", NULL, 0, 0}, 318 PIC_MSI, 319 #ifdef MULTIPROCESSOR 320 {}, 321 #endif 322 msi_hwmask, 323 msi_hwunmask, 324 msi_addroute, 325 msi_delroute, 326 NULL, 327 ioapic_edge_stubs 328 }; 329 330 void 331 msi_hwmask(struct pic *pic, int pin) 332 { 333 } 334 335 void 336 msi_hwunmask(struct pic *pic, int pin) 337 { 338 } 339 340 void 341 msi_addroute(struct pic *pic, struct cpu_info *ci, int pin, int vec, int type) 342 { 343 pci_chipset_tag_t pc = NULL; /* XXX */ 344 pcitag_t tag = pin; 345 pcireg_t reg, addr; 346 int off; 347 348 if (pci_get_capability(pc, tag, PCI_CAP_MSI, &off, ®) == 0) 349 panic("%s: no msi capability", __func__); 350 351 addr = 0xfee00000UL | (ci->ci_apicid << 12); 352 353 if (reg & PCI_MSI_MC_C64) { 354 pci_conf_write(pc, tag, off + PCI_MSI_MA, addr); 355 pci_conf_write(pc, tag, off + PCI_MSI_MAU32, 0); 356 pci_conf_write(pc, tag, off + PCI_MSI_MD64, vec); 357 } else { 358 pci_conf_write(pc, tag, off + PCI_MSI_MA, addr); 359 pci_conf_write(pc, tag, off + PCI_MSI_MD32, vec); 360 } 361 pci_conf_write(pc, tag, off, reg | PCI_MSI_MC_MSIE); 362 } 363 364 void 365 msi_delroute(struct pic *pic, struct cpu_info *ci, int pin, int vec, int type) 366 { 367 pci_chipset_tag_t pc = NULL; /* XXX */ 368 pcitag_t tag = pin; 369 pcireg_t reg; 370 int off; 371 372 if (pci_get_capability(pc, tag, PCI_CAP_MSI, &off, ®)) 373 pci_conf_write(pc, tag, off, reg & ~PCI_MSI_MC_MSIE); 374 } 375 376 int 377 pci_intr_map_msi(struct pci_attach_args *pa, pci_intr_handle_t *ihp) 378 { 379 pci_chipset_tag_t pc = pa->pa_pc; 380 pcitag_t tag = pa->pa_tag; 381 382 if ((pa->pa_flags & PCI_FLAGS_MSI_ENABLED) == 0 || mp_busses == NULL || 383 pci_get_capability(pc, tag, PCI_CAP_MSI, NULL, NULL) == 0) 384 return 1; 385 386 ihp->tag = tag; 387 ihp->line = APIC_INT_VIA_MSG; 388 ihp->pin = 0; 389 return 0; 390 } 391 392 void msix_hwmask(struct pic *, int); 393 void msix_hwunmask(struct pic *, int); 394 void msix_addroute(struct pic *, struct cpu_info *, int, int, int); 395 void msix_delroute(struct pic *, struct cpu_info *, int, int, int); 396 397 struct pic msix_pic = { 398 {0, {NULL}, NULL, 0, "msix", NULL, 0, 0}, 399 PIC_MSI, 400 #ifdef MULTIPROCESSOR 401 {}, 402 #endif 403 msix_hwmask, 404 msix_hwunmask, 405 msix_addroute, 406 msix_delroute, 407 NULL, 408 ioapic_edge_stubs 409 }; 410 411 /* 412 * We pack the MSI-X vector number into the lower 8 bits of the PCI 413 * tag and use that as the MSI-X "PIC" pin number. This allows us to 414 * address 256 MSI-X vectors which ought to be enough for anybody. 415 */ 416 #define PCI_MSIX_VEC_MASK 0xff 417 #define PCI_MSIX_VEC(pin) ((pin) & PCI_MSIX_VEC_MASK) 418 #define PCI_MSIX_TAG(pin) ((pin) & ~PCI_MSIX_VEC_MASK) 419 #define PCI_MSIX_PIN(tag, vec) ((tag) | (vec)) 420 421 void 422 msix_hwmask(struct pic *pic, int pin) 423 { 424 } 425 426 void 427 msix_hwunmask(struct pic *pic, int pin) 428 { 429 } 430 431 void 432 msix_addroute(struct pic *pic, struct cpu_info *ci, int pin, int vec, int type) 433 { 434 pci_chipset_tag_t pc = NULL; /* XXX */ 435 bus_space_tag_t memt = X86_BUS_SPACE_MEM; /* XXX */ 436 bus_space_handle_t memh; 437 bus_addr_t base; 438 pcitag_t tag = PCI_MSIX_TAG(pin); 439 int entry = PCI_MSIX_VEC(pin); 440 pcireg_t reg, addr, table; 441 uint32_t ctrl; 442 int bir, offset; 443 int off, tblsz; 444 445 if (pci_get_capability(pc, tag, PCI_CAP_MSIX, &off, ®) == 0) 446 panic("%s: no msix capability", __func__); 447 448 addr = 0xfee00000UL | (ci->ci_apicid << 12); 449 450 table = pci_conf_read(pc, tag, off + PCI_MSIX_TABLE); 451 bir = (table & PCI_MSIX_TABLE_BIR); 452 offset = (table & PCI_MSIX_TABLE_OFF); 453 tblsz = PCI_MSIX_MC_TBLSZ(reg) + 1; 454 455 bir = PCI_MAPREG_START + bir * 4; 456 if (pci_mem_find(pc, tag, bir, &base, NULL, NULL) || 457 _bus_space_map(memt, base + offset, tblsz * 16, 0, &memh)) 458 panic("%s: cannot map registers", __func__); 459 460 bus_space_write_8(memt, memh, PCI_MSIX_MA(entry), addr); 461 bus_space_write_4(memt, memh, PCI_MSIX_MD(entry), vec); 462 bus_space_barrier(memt, memh, PCI_MSIX_MA(entry), 16, 463 BUS_SPACE_BARRIER_WRITE); 464 ctrl = bus_space_read_4(memt, memh, PCI_MSIX_VC(entry)); 465 bus_space_write_4(memt, memh, PCI_MSIX_VC(entry), 466 ctrl & ~PCI_MSIX_VC_MASK); 467 468 _bus_space_unmap(memt, memh, tblsz * 16, NULL); 469 470 pci_conf_write(pc, tag, off, reg | PCI_MSIX_MC_MSIXE); 471 } 472 473 void 474 msix_delroute(struct pic *pic, struct cpu_info *ci, int pin, int vec, int type) 475 { 476 pci_chipset_tag_t pc = NULL; /* XXX */ 477 bus_space_tag_t memt = X86_BUS_SPACE_MEM; /* XXX */ 478 bus_space_handle_t memh; 479 bus_addr_t base; 480 pcitag_t tag = PCI_MSIX_TAG(pin); 481 int entry = PCI_MSIX_VEC(pin); 482 pcireg_t reg, table; 483 uint32_t ctrl; 484 int bir, offset; 485 int off, tblsz; 486 487 if (pci_get_capability(pc, tag, PCI_CAP_MSIX, &off, ®) == 0) 488 return; 489 490 table = pci_conf_read(pc, tag, off + PCI_MSIX_TABLE); 491 bir = (table & PCI_MSIX_TABLE_BIR); 492 offset = (table & PCI_MSIX_TABLE_OFF); 493 tblsz = PCI_MSIX_MC_TBLSZ(reg) + 1; 494 495 bir = PCI_MAPREG_START + bir * 4; 496 if (pci_mem_find(pc, tag, bir, &base, NULL, NULL) || 497 _bus_space_map(memt, base + offset, tblsz * 16, 0, &memh)) 498 panic("%s: cannot map registers", __func__); 499 500 ctrl = bus_space_read_4(memt, memh, PCI_MSIX_VC(entry)); 501 bus_space_write_4(memt, memh, PCI_MSIX_VC(entry), 502 ctrl | PCI_MSIX_VC_MASK); 503 504 _bus_space_unmap(memt, memh, tblsz * 16, NULL); 505 } 506 507 int 508 pci_intr_map_msix(struct pci_attach_args *pa, int vec, pci_intr_handle_t *ihp) 509 { 510 pci_chipset_tag_t pc = pa->pa_pc; 511 pcitag_t tag = pa->pa_tag; 512 pcireg_t reg; 513 514 KASSERT(PCI_MSIX_VEC(vec) == vec); 515 516 if ((pa->pa_flags & PCI_FLAGS_MSI_ENABLED) == 0 || mp_busses == NULL || 517 pci_get_capability(pc, tag, PCI_CAP_MSIX, NULL, ®) == 0) 518 return 1; 519 520 if (vec > PCI_MSIX_MC_TBLSZ(reg)) 521 return 1; 522 523 ihp->tag = PCI_MSIX_PIN(tag, vec); 524 ihp->line = APIC_INT_VIA_MSGX; 525 ihp->pin = 0; 526 return 0; 527 } 528 529 int 530 pci_intr_map(struct pci_attach_args *pa, pci_intr_handle_t *ihp) 531 { 532 int pin = pa->pa_rawintrpin; 533 int line = pa->pa_intrline; 534 #if NIOAPIC > 0 535 struct mp_intr_map *mip; 536 int bus, dev, func; 537 #endif 538 539 if (pin == 0) { 540 /* No IRQ used. */ 541 goto bad; 542 } 543 544 if (pin > PCI_INTERRUPT_PIN_MAX) { 545 printf("pci_intr_map: bad interrupt pin %d\n", pin); 546 goto bad; 547 } 548 549 ihp->tag = pa->pa_tag; 550 ihp->line = line; 551 ihp->pin = pin; 552 553 #if NIOAPIC > 0 554 pci_decompose_tag(pa->pa_pc, pa->pa_tag, &bus, &dev, &func); 555 556 if (mp_busses != NULL) { 557 int mpspec_pin = (dev << 2) | (pin - 1); 558 559 if (bus < mp_nbusses) { 560 for (mip = mp_busses[bus].mb_intrs; 561 mip != NULL; mip = mip->next) { 562 if (&mp_busses[bus] == mp_isa_bus || 563 &mp_busses[bus] == mp_eisa_bus) 564 continue; 565 if (mip->bus_pin == mpspec_pin) { 566 ihp->line = mip->ioapic_ih | line; 567 return 0; 568 } 569 } 570 } 571 572 if (pa->pa_bridgetag) { 573 int swizpin = PPB_INTERRUPT_SWIZZLE(pin, dev); 574 if (pa->pa_bridgeih[swizpin - 1].line != -1) { 575 ihp->line = pa->pa_bridgeih[swizpin - 1].line; 576 ihp->line |= line; 577 return 0; 578 } 579 } 580 /* 581 * No explicit PCI mapping found. This is not fatal, 582 * we'll try the ISA (or possibly EISA) mappings next. 583 */ 584 } 585 #endif 586 587 /* 588 * Section 6.2.4, `Miscellaneous Functions', says that 255 means 589 * `unknown' or `no connection' on a PC. We assume that a device with 590 * `no connection' either doesn't have an interrupt (in which case the 591 * pin number should be 0, and would have been noticed above), or 592 * wasn't configured by the BIOS (in which case we punt, since there's 593 * no real way we can know how the interrupt lines are mapped in the 594 * hardware). 595 * 596 * XXX 597 * Since IRQ 0 is only used by the clock, and we can't actually be sure 598 * that the BIOS did its job, we also recognize that as meaning that 599 * the BIOS has not configured the device. 600 */ 601 if (line == 0 || line == X86_PCI_INTERRUPT_LINE_NO_CONNECTION) 602 goto bad; 603 604 if (line >= NUM_LEGACY_IRQS) { 605 printf("pci_intr_map: bad interrupt line %d\n", line); 606 goto bad; 607 } 608 if (line == 2) { 609 printf("pci_intr_map: changed line 2 to line 9\n"); 610 line = 9; 611 } 612 613 #if NIOAPIC > 0 614 if (mp_busses != NULL) { 615 if (mip == NULL && mp_isa_bus) { 616 for (mip = mp_isa_bus->mb_intrs; mip != NULL; 617 mip = mip->next) { 618 if (mip->bus_pin == line) { 619 ihp->line = mip->ioapic_ih | line; 620 return 0; 621 } 622 } 623 } 624 #if NEISA > 0 625 if (mip == NULL && mp_eisa_bus) { 626 for (mip = mp_eisa_bus->mb_intrs; mip != NULL; 627 mip = mip->next) { 628 if (mip->bus_pin == line) { 629 ihp->line = mip->ioapic_ih | line; 630 return 0; 631 } 632 } 633 } 634 #endif 635 if (mip == NULL) { 636 printf("pci_intr_map: " 637 "bus %d dev %d func %d pin %d; line %d\n", 638 bus, dev, func, pin, line); 639 printf("pci_intr_map: no MP mapping found\n"); 640 } 641 } 642 #endif 643 644 return 0; 645 646 bad: 647 ihp->line = -1; 648 return 1; 649 } 650 651 const char * 652 pci_intr_string(pci_chipset_tag_t pc, pci_intr_handle_t ih) 653 { 654 static char irqstr[64]; 655 656 if (ih.line == 0) 657 panic("pci_intr_string: bogus handle 0x%x", ih.line); 658 659 if (ih.line & APIC_INT_VIA_MSG) 660 return ("msi"); 661 if (ih.line & APIC_INT_VIA_MSGX) 662 return ("msix"); 663 664 #if NIOAPIC > 0 665 if (ih.line & APIC_INT_VIA_APIC) 666 snprintf(irqstr, sizeof(irqstr), "apic %d int %d", 667 APIC_IRQ_APIC(ih.line), APIC_IRQ_PIN(ih.line)); 668 else 669 snprintf(irqstr, sizeof(irqstr), "irq %d", 670 pci_intr_line(pc, ih)); 671 #else 672 snprintf(irqstr, sizeof(irqstr), "irq %d", pci_intr_line(pc, ih)); 673 #endif 674 return (irqstr); 675 } 676 677 #include "acpiprt.h" 678 #if NACPIPRT > 0 679 void acpiprt_route_interrupt(int bus, int dev, int pin); 680 #endif 681 682 void * 683 pci_intr_establish(pci_chipset_tag_t pc, pci_intr_handle_t ih, int level, 684 int (*func)(void *), void *arg, const char *what) 685 { 686 int pin, irq; 687 int bus, dev; 688 pcitag_t tag = ih.tag; 689 struct pic *pic; 690 691 if (ih.line & APIC_INT_VIA_MSG) { 692 return intr_establish(-1, &msi_pic, tag, IST_PULSE, level, 693 func, arg, what); 694 } 695 if (ih.line & APIC_INT_VIA_MSGX) { 696 return intr_establish(-1, &msix_pic, tag, IST_PULSE, level, 697 func, arg, what); 698 } 699 700 pci_decompose_tag(pc, ih.tag, &bus, &dev, NULL); 701 #if NACPIPRT > 0 702 acpiprt_route_interrupt(bus, dev, ih.pin); 703 #endif 704 705 pic = &i8259_pic; 706 pin = irq = ih.line; 707 708 #if NIOAPIC > 0 709 if (ih.line & APIC_INT_VIA_APIC) { 710 pic = (struct pic *)ioapic_find(APIC_IRQ_APIC(ih.line)); 711 if (pic == NULL) { 712 printf("pci_intr_establish: bad ioapic %d\n", 713 APIC_IRQ_APIC(ih.line)); 714 return NULL; 715 } 716 pin = APIC_IRQ_PIN(ih.line); 717 irq = APIC_IRQ_LEGACY_IRQ(ih.line); 718 if (irq < 0 || irq >= NUM_LEGACY_IRQS) 719 irq = -1; 720 } 721 #endif 722 723 return intr_establish(irq, pic, pin, IST_LEVEL, level, func, arg, what); 724 } 725 726 void 727 pci_intr_disestablish(pci_chipset_tag_t pc, void *cookie) 728 { 729 intr_disestablish(cookie); 730 } 731 732 struct extent *pciio_ex; 733 struct extent *pcimem_ex; 734 struct extent *pcibus_ex; 735 736 void 737 pci_init_extents(void) 738 { 739 bios_memmap_t *bmp; 740 u_int64_t size; 741 742 if (pciio_ex == NULL) { 743 /* 744 * We only have 64K of addressable I/O space. 745 * However, since BARs may contain garbage, we cover 746 * the full 32-bit address space defined by PCI of 747 * which we only make the first 64K available. 748 */ 749 pciio_ex = extent_create("pciio", 0, 0xffffffff, M_DEVBUF, 750 NULL, 0, EX_NOWAIT | EX_FILLED); 751 if (pciio_ex == NULL) 752 return; 753 extent_free(pciio_ex, 0, 0x10000, EX_NOWAIT); 754 } 755 756 if (pcimem_ex == NULL) { 757 /* 758 * Cover the 36-bit address space addressable by PAE 759 * here. As long as vendors continue to support 760 * 32-bit operating systems, we should never see BARs 761 * outside that region. 762 * 763 * Dell 13G servers have important devices outside the 764 * 36-bit address space. Until we can extract the address 765 * ranges from ACPI, expand the allowed range to suit. 766 */ 767 pcimem_ex = extent_create("pcimem", 0, 0xffffffffffffffffUL, 768 M_DEVBUF, NULL, 0, EX_NOWAIT); 769 if (pcimem_ex == NULL) 770 return; 771 extent_alloc_region(pcimem_ex, 0x40000000000UL, 772 0xfffffc0000000000UL, EX_NOWAIT); 773 774 for (bmp = bios_memmap; bmp->type != BIOS_MAP_END; bmp++) { 775 /* 776 * Ignore address space beyond 4G. 777 */ 778 if (bmp->addr >= 0x100000000ULL) 779 continue; 780 size = bmp->size; 781 if (bmp->addr + size >= 0x100000000ULL) 782 size = 0x100000000ULL - bmp->addr; 783 784 /* Ignore zero-sized regions. */ 785 if (size == 0) 786 continue; 787 788 if (extent_alloc_region(pcimem_ex, bmp->addr, size, 789 EX_NOWAIT)) 790 printf("memory map conflict 0x%llx/0x%llx\n", 791 bmp->addr, bmp->size); 792 } 793 794 /* Take out the video buffer area and BIOS areas. */ 795 extent_alloc_region(pcimem_ex, IOM_BEGIN, IOM_SIZE, 796 EX_CONFLICTOK | EX_NOWAIT); 797 } 798 799 if (pcibus_ex == NULL) { 800 pcibus_ex = extent_create("pcibus", 0, 0xff, M_DEVBUF, 801 NULL, 0, EX_NOWAIT); 802 } 803 } 804 805 #include "acpi.h" 806 #if NACPI > 0 807 void acpi_pci_match(struct device *, struct pci_attach_args *); 808 pcireg_t acpi_pci_min_powerstate(pci_chipset_tag_t, pcitag_t); 809 void acpi_pci_set_powerstate(pci_chipset_tag_t, pcitag_t, int, int); 810 #endif 811 812 void 813 pci_dev_postattach(struct device *dev, struct pci_attach_args *pa) 814 { 815 #if NACPI > 0 816 acpi_pci_match(dev, pa); 817 #endif 818 } 819 820 pcireg_t 821 pci_min_powerstate(pci_chipset_tag_t pc, pcitag_t tag) 822 { 823 #if NACPI > 0 824 return acpi_pci_min_powerstate(pc, tag); 825 #else 826 return pci_get_powerstate(pc, tag); 827 #endif 828 } 829 830 void 831 pci_set_powerstate_md(pci_chipset_tag_t pc, pcitag_t tag, int state, int pre) 832 { 833 #if NACPI > 0 834 acpi_pci_set_powerstate(pc, tag, state, pre); 835 #endif 836 } 837