1 /* $OpenBSD: specialreg.h,v 1.48 2016/09/10 17:15:44 mlarkin Exp $ */ 2 /* $NetBSD: specialreg.h,v 1.1 2003/04/26 18:39:48 fvdl Exp $ */ 3 /* $NetBSD: x86/specialreg.h,v 1.2 2003/04/25 21:54:30 fvdl Exp $ */ 4 5 /*- 6 * Copyright (c) 1991 The Regents of the University of California. 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. Neither the name of the University nor the names of its contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 25 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 27 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 31 * SUCH DAMAGE. 32 * 33 * @(#)specialreg.h 7.1 (Berkeley) 5/9/91 34 */ 35 36 /* 37 * Bits in 386 special registers: 38 */ 39 #define CR0_PE 0x00000001 /* Protected mode Enable */ 40 #define CR0_MP 0x00000002 /* "Math" Present (NPX or NPX emulator) */ 41 #define CR0_EM 0x00000004 /* EMulate non-NPX coproc. (trap ESC only) */ 42 #define CR0_TS 0x00000008 /* Task Switched (if MP, trap ESC and WAIT) */ 43 #define CR0_ET 0x00000010 /* Extension Type (387 (if set) vs 287) */ 44 #define CR0_PG 0x80000000 /* PaGing enable */ 45 46 /* 47 * Bits in 486 special registers: 48 */ 49 #define CR0_NE 0x00000020 /* Numeric Error enable (EX16 vs IRQ13) */ 50 #define CR0_WP 0x00010000 /* Write Protect (honor PG_RW in all modes) */ 51 #define CR0_AM 0x00040000 /* Alignment Mask (set to enable AC flag) */ 52 #define CR0_NW 0x20000000 /* Not Write-through */ 53 #define CR0_CD 0x40000000 /* Cache Disable */ 54 55 /* 56 * Cyrix 486 DLC special registers, accessible as IO ports. 57 */ 58 #define CCR0 0xc0 /* configuration control register 0 */ 59 #define CCR0_NC0 0x01 /* first 64K of each 1M memory region is non-cacheable */ 60 #define CCR0_NC1 0x02 /* 640K-1M region is non-cacheable */ 61 #define CCR0_A20M 0x04 /* enables A20M# input pin */ 62 #define CCR0_KEN 0x08 /* enables KEN# input pin */ 63 #define CCR0_FLUSH 0x10 /* enables FLUSH# input pin */ 64 #define CCR0_BARB 0x20 /* flushes internal cache when entering hold state */ 65 #define CCR0_CO 0x40 /* cache org: 1=direct mapped, 0=2x set assoc */ 66 #define CCR0_SUSPEND 0x80 /* enables SUSP# and SUSPA# pins */ 67 68 #define CCR1 0xc1 /* configuration control register 1 */ 69 #define CCR1_RPL 0x01 /* enables RPLSET and RPLVAL# pins */ 70 /* the remaining 7 bits of this register are reserved */ 71 72 /* 73 * bits in CR3 74 */ 75 #define CR3_PWT (1ULL << 3) 76 #define CR3_PCD (1ULL << 4) 77 78 /* 79 * bits in the pentiums %cr4 register: 80 */ 81 82 #define CR4_VME 0x00000001 /* virtual 8086 mode extension enable */ 83 #define CR4_PVI 0x00000002 /* protected mode virtual interrupt enable */ 84 #define CR4_TSD 0x00000004 /* restrict RDTSC instruction to cpl 0 only */ 85 #define CR4_DE 0x00000008 /* debugging extension */ 86 #define CR4_PSE 0x00000010 /* large (4MB) page size enable */ 87 #define CR4_PAE 0x00000020 /* physical address extension enable */ 88 #define CR4_MCE 0x00000040 /* machine check enable */ 89 #define CR4_PGE 0x00000080 /* page global enable */ 90 #define CR4_PCE 0x00000100 /* enable RDPMC instruction for all cpls */ 91 #define CR4_OSFXSR 0x00000200 /* enable fxsave/fxrestor and SSE */ 92 #define CR4_OSXMMEXCPT 0x00000400 /* enable unmasked SSE exceptions */ 93 #define CR4_UMIP 0x00000800 /* user mode instruction prevention */ 94 #define CR4_VMXE 0x00002000 /* enable virtual machine operation */ 95 #define CR4_SMXE 0x00004000 /* enable safe mode operation */ 96 #define CR4_FSGSBASE 0x00010000 /* enable {RD,WR}{FS,GS}BASE ops */ 97 #define CR4_PCIDE 0x00020000 /* enable process-context IDs */ 98 #define CR4_OSXSAVE 0x00040000 /* enable XSAVE and extended states */ 99 #define CR4_SMEP 0x00100000 /* supervisor mode exec protection */ 100 #define CR4_SMAP 0x00200000 /* supervisor mode access prevention */ 101 #define CR4_PKE 0x00400000 /* protection key enable */ 102 103 /* 104 * Extended Control Register XCR0 105 */ 106 #define XCR0_X87 0x00000001 /* x87 FPU/MMX state */ 107 #define XCR0_SSE 0x00000002 /* SSE state */ 108 #define XCR0_AVX 0x00000004 /* AVX state */ 109 110 /* 111 * CPUID "features" bits (CPUID function 0x1): 112 * EDX bits, then ECX bits 113 */ 114 115 #define CPUID_FPU 0x00000001 /* processor has an FPU? */ 116 #define CPUID_VME 0x00000002 /* has virtual mode (%cr4's VME/PVI) */ 117 #define CPUID_DE 0x00000004 /* has debugging extension */ 118 #define CPUID_PSE 0x00000008 /* has 4MB page size extension */ 119 #define CPUID_TSC 0x00000010 /* has time stamp counter */ 120 #define CPUID_MSR 0x00000020 /* has model specific registers */ 121 #define CPUID_PAE 0x00000040 /* has phys address extension */ 122 #define CPUID_MCE 0x00000080 /* has machine check exception */ 123 #define CPUID_CX8 0x00000100 /* has CMPXCHG8B instruction */ 124 #define CPUID_APIC 0x00000200 /* has enabled APIC */ 125 #define CPUID_SYS1 0x00000400 /* has SYSCALL/SYSRET inst. (Cyrix) */ 126 #define CPUID_SEP 0x00000800 /* has SYSCALL/SYSRET inst. (AMD/Intel) */ 127 #define CPUID_MTRR 0x00001000 /* has memory type range register */ 128 #define CPUID_PGE 0x00002000 /* has page global extension */ 129 #define CPUID_MCA 0x00004000 /* has machine check architecture */ 130 #define CPUID_CMOV 0x00008000 /* has CMOVcc instruction */ 131 #define CPUID_PAT 0x00010000 /* has page attribute table */ 132 #define CPUID_PSE36 0x00020000 /* has 36bit page size extension */ 133 #define CPUID_PSN 0x00040000 /* has processor serial number */ 134 #define CPUID_CFLUSH 0x00080000 /* CFLUSH insn supported */ 135 #define CPUID_B20 0x00100000 /* reserved */ 136 #define CPUID_DS 0x00200000 /* Debug Store */ 137 #define CPUID_ACPI 0x00400000 /* ACPI performance modulation regs */ 138 #define CPUID_MMX 0x00800000 /* has MMX instructions */ 139 #define CPUID_FXSR 0x01000000 /* has FXRSTOR instruction */ 140 #define CPUID_SSE 0x02000000 /* has streaming SIMD extensions */ 141 #define CPUID_SSE2 0x04000000 /* has streaming SIMD extensions #2 */ 142 #define CPUID_SS 0x08000000 /* self-snoop */ 143 #define CPUID_HTT 0x10000000 /* Hyper-Threading Technology */ 144 #define CPUID_TM 0x20000000 /* thermal monitor (TCC) */ 145 #define CPUID_B30 0x40000000 /* reserved */ 146 #define CPUID_PBE 0x80000000 /* Pending Break Enabled restarts clock */ 147 148 #define CPUIDECX_SSE3 0x00000001 /* streaming SIMD extensions #3 */ 149 #define CPUIDECX_PCLMUL 0x00000002 /* Carryless Multiplication */ 150 #define CPUIDECX_DTES64 0x00000004 /* 64bit debug store */ 151 #define CPUIDECX_MWAIT 0x00000008 /* Monitor/Mwait */ 152 #define CPUIDECX_DSCPL 0x00000010 /* CPL Qualified Debug Store */ 153 #define CPUIDECX_VMX 0x00000020 /* Virtual Machine Extensions */ 154 #define CPUIDECX_SMX 0x00000040 /* Safer Mode Extensions */ 155 #define CPUIDECX_EST 0x00000080 /* enhanced SpeedStep */ 156 #define CPUIDECX_TM2 0x00000100 /* thermal monitor 2 */ 157 #define CPUIDECX_SSSE3 0x00000200 /* Supplemental Streaming SIMD Ext. 3 */ 158 #define CPUIDECX_CNXTID 0x00000400 /* Context ID */ 159 #define CPUIDECX_SDBG 0x00000800 /* Silicon debug capability */ 160 #define CPUIDECX_FMA3 0x00001000 /* Fused Multiply Add */ 161 #define CPUIDECX_CX16 0x00002000 /* has CMPXCHG16B instruction */ 162 #define CPUIDECX_XTPR 0x00004000 /* xTPR Update Control */ 163 #define CPUIDECX_PDCM 0x00008000 /* Perfmon and Debug Capability */ 164 #define CPUIDECX_PCID 0x00020000 /* Process-context ID Capability */ 165 #define CPUIDECX_DCA 0x00040000 /* Direct Cache Access */ 166 #define CPUIDECX_SSE41 0x00080000 /* Streaming SIMD Extensions 4.1 */ 167 #define CPUIDECX_SSE42 0x00100000 /* Streaming SIMD Extensions 4.2 */ 168 #define CPUIDECX_X2APIC 0x00200000 /* Extended xAPIC Support */ 169 #define CPUIDECX_MOVBE 0x00400000 /* MOVBE Instruction */ 170 #define CPUIDECX_POPCNT 0x00800000 /* POPCNT Instruction */ 171 #define CPUIDECX_DEADLINE 0x01000000 /* APIC one-shot via deadline */ 172 #define CPUIDECX_AES 0x02000000 /* AES Instruction */ 173 #define CPUIDECX_XSAVE 0x04000000 /* XSAVE/XSTOR States */ 174 #define CPUIDECX_OSXSAVE 0x08000000 /* OSXSAVE */ 175 #define CPUIDECX_AVX 0x10000000 /* Advanced Vector Extensions */ 176 #define CPUIDECX_F16C 0x20000000 /* 16bit fp conversion */ 177 #define CPUIDECX_RDRAND 0x40000000 /* RDRAND instruction */ 178 #define CPUIDECX_HV 0x80000000 /* Running on hypervisor */ 179 180 /* 181 * "Structured Extended Feature Flags Parameters" (CPUID function 0x7, leaf 0) 182 * EBX bits 183 */ 184 #define SEFF0EBX_FSGSBASE 0x00000001 /* {RD,WR}[FG]SBASE instructions */ 185 #define SEFF0EBX_SGX 0x00000004 /* Software Guard Extensions */ 186 #define SEFF0EBX_BMI1 0x00000008 /* advanced bit manipulation */ 187 #define SEFF0EBX_HLE 0x00000010 /* Hardware Lock Elision */ 188 #define SEFF0EBX_AVX2 0x00000020 /* Advanced Vector Extensions 2 */ 189 #define SEFF0EBX_SMEP 0x00000080 /* Supervisor mode exec protection */ 190 #define SEFF0EBX_BMI2 0x00000100 /* advanced bit manipulation */ 191 #define SEFF0EBX_ERMS 0x00000200 /* Enhanced REP MOVSB/STOSB */ 192 #define SEFF0EBX_INVPCID 0x00000400 /* INVPCID instruction */ 193 #define SEFF0EBX_RTM 0x00000800 /* Restricted Transactional Memory */ 194 #define SEFF0EBX_PQM 0x00001000 /* Quality of Service Monitoring */ 195 #define SEFF0EBX_MPX 0x00004000 /* Memory Protection Extensions */ 196 #define SEFF0EBX_AVX512F 0x00010000 /* AVX-512 foundation inst */ 197 #define SEFF0EBX_AVX512DQ 0x00020000 /* AVX-512 double/quadword */ 198 #define SEFF0EBX_RDSEED 0x00040000 /* RDSEED instruction */ 199 #define SEFF0EBX_ADX 0x00080000 /* ADCX/ADOX instructions */ 200 #define SEFF0EBX_SMAP 0x00100000 /* Supervisor mode access prevent */ 201 #define SEFF0EBX_AVX512IFMA 0x00200000 /* AVX-512 integer mult-add */ 202 #define SEFF0EBX_PCOMMIT 0x00400000 /* Persistent commit inst */ 203 #define SEFF0EBX_CLFLUSHOPT 0x00800000 /* cache line flush */ 204 #define SEFF0EBX_CLWB 0x01000000 /* cache line write back */ 205 #define SEFF0EBX_PT 0x02000000 /* Processor Trace */ 206 #define SEFF0EBX_AVX512PF 0x04000000 /* AVX-512 prefetch */ 207 #define SEFF0EBX_AVX512ER 0x08000000 /* AVX-512 exp/reciprocal */ 208 #define SEFF0EBX_AVX512CD 0x10000000 /* AVX-512 conflict detection */ 209 #define SEFF0EBX_SHA 0x20000000 /* SHA Extensions */ 210 #define SEFF0EBX_AVX512BW 0x40000000 /* AVX-512 byte/word inst */ 211 #define SEFF0EBX_AVX512VL 0x80000000 /* AVX-512 vector len inst */ 212 /* SEFF ECX bits */ 213 #define SEFF0ECX_PREFETCHWT1 0x00000001 /* PREFETCHWT1 instruction */ 214 #define SEFF0ECX_AVX512VBMI 0x00000002 /* AVX-512 vector bit inst */ 215 #define SEFF0ECX_UMIP 0x00000004 /* UMIP support */ 216 #define SEFF0ECX_PKU 0x00000008 /* Page prot keys for user mode */ 217 218 /* 219 * Thermal and Power Management (CPUID function 0x6) EAX bits 220 */ 221 #define TPM_SENSOR 0x00000001 /* Digital temp sensor */ 222 #define TPM_ARAT 0x00000004 /* APIC Timer Always Running */ 223 224 /* 225 * "Architectural Performance Monitoring" bits (CPUID function 0x0a): 226 * EAX bits, EBX bits, EDX bits. 227 */ 228 229 #define CPUIDEAX_VERID 0x000000ff /* Version ID */ 230 #define CPUIDEAX_NUM_GC(cpuid) (((cpuid) >> 8) & 0x000000ff) 231 #define CPUIDEAX_BIT_GC(cpuid) (((cpuid) >> 16) & 0x000000ff) 232 #define CPUIDEAX_LEN_EBX(cpuid) (((cpuid) >> 24) & 0x000000ff) 233 234 #define CPUIDEBX_EVT_CORE (1 << 0) /* Core cycle */ 235 #define CPUIDEBX_EVT_INST (1 << 1) /* Instruction retired */ 236 #define CPUIDEBX_EVT_REFR (1 << 2) /* Reference cycles */ 237 #define CPUIDEBX_EVT_CACHE_REF (1 << 3) /* Last-level cache ref. */ 238 #define CPUIDEBX_EVT_CACHE_MIS (1 << 4) /* Last-level cache miss. */ 239 #define CPUIDEBX_EVT_BRANCH_INST (1 << 5) /* Branch instruction ret. */ 240 #define CPUIDEBX_EVT_BRANCH_MISP (1 << 6) /* Branch mispredict ret. */ 241 242 #define CPUIDEDX_NUM_FC(cpuid) (((cpuid) >> 0) & 0x0000001f) 243 #define CPUIDEDX_BIT_FC(cpuid) (((cpuid) >> 5) & 0x000000ff) 244 245 /* 246 * CPUID "extended features" bits (CPUID function 0x80000001): 247 * EDX bits, then ECX bits 248 */ 249 250 #define CPUID_MPC 0x00080000 /* Multiprocessing Capable */ 251 #define CPUID_NXE 0x00100000 /* No-Execute Extension */ 252 #define CPUID_MMXX 0x00400000 /* AMD MMX Extensions */ 253 #define CPUID_FFXSR 0x02000000 /* fast FP/MMX save/restore */ 254 #define CPUID_PAGE1GB 0x04000000 /* 1-GByte pages */ 255 #define CPUID_LONG 0x20000000 /* long mode */ 256 #define CPUID_3DNOW2 0x40000000 /* 3DNow! Instruction Extension */ 257 #define CPUID_3DNOW 0x80000000 /* 3DNow! Instructions */ 258 259 #define CPUIDECX_LAHF 0x00000001 /* LAHF and SAHF instructions */ 260 #define CPUIDECX_CMPLEG 0x00000002 /* Core MP legacy mode */ 261 #define CPUIDECX_SVM 0x00000004 /* Secure Virtual Machine */ 262 #define CPUIDECX_EAPICSP 0x00000008 /* Extended APIC space */ 263 #define CPUIDECX_AMCR8 0x00000010 /* LOCK MOV CR0 means MOV CR8 */ 264 #define CPUIDECX_ABM 0x00000020 /* LZCNT instruction */ 265 #define CPUIDECX_SSE4A 0x00000040 /* SSE4-A instruction set */ 266 #define CPUIDECX_MASSE 0x00000080 /* Misaligned SSE mode */ 267 #define CPUIDECX_3DNOWP 0x00000100 /* 3DNowPrefetch */ 268 #define CPUIDECX_OSVW 0x00000200 /* OS visible workaround */ 269 #define CPUIDECX_IBS 0x00000400 /* Instruction based sampling */ 270 #define CPUIDECX_XOP 0x00000800 /* Extended operating support */ 271 #define CPUIDECX_SKINIT 0x00001000 /* SKINIT and STGI are supported */ 272 #define CPUIDECX_WDT 0x00002000 /* Watchdog timer */ 273 /* Reserved 0x00004000 */ 274 #define CPUIDECX_LWP 0x00008000 /* Lightweight profiling support */ 275 #define CPUIDECX_FMA4 0x00010000 /* 4-operand FMA instructions */ 276 /* Reserved 0x00020000 */ 277 /* Reserved 0x00040000 */ 278 #define CPUIDECX_NODEID 0x00080000 /* Support for MSRC001C */ 279 /* Reserved 0x00100000 */ 280 #define CPUIDECX_TBM 0x00200000 /* Trailing bit manipulation instruction */ 281 #define CPUIDECX_TOPEXT 0x00400000 /* Topology extensions support */ 282 283 /* 284 * "Advanced Power Management Information" bits (CPUID function 0x80000007): 285 * EDX bits. 286 */ 287 288 #define CPUIDEDX_ITSC (1 << 8) /* Invariant TSC */ 289 290 #define CPUID2FAMILY(cpuid) (((cpuid) >> 8) & 15) 291 #define CPUID2MODEL(cpuid) (((cpuid) >> 4) & 15) 292 #define CPUID2STEPPING(cpuid) ((cpuid) & 15) 293 294 #define CPUID(code, eax, ebx, ecx, edx) \ 295 __asm volatile("cpuid" \ 296 : "=a" (eax), "=b" (ebx), "=c" (ecx), "=d" (edx) \ 297 : "a" (code)); 298 #define CPUID_LEAF(code, leaf, eax, ebx, ecx, edx) \ 299 __asm volatile("cpuid" \ 300 : "=a" (eax), "=b" (ebx), "=c" (ecx), "=d" (edx) \ 301 : "a" (code), "c" (leaf)); 302 303 304 /* 305 * Model-specific registers for the i386 family 306 */ 307 #define MSR_P5_MC_ADDR 0x000 /* P5 only */ 308 #define MSR_P5_MC_TYPE 0x001 /* P5 only */ 309 #define MSR_TSC 0x010 310 #define MSR_CESR 0x011 /* P5 only (trap on P6) */ 311 #define MSR_CTR0 0x012 /* P5 only (trap on P6) */ 312 #define MSR_CTR1 0x013 /* P5 only (trap on P6) */ 313 #define MSR_APICBASE 0x01b 314 #define APICBASE_BSP 0x100 315 #define APICBASE_ENABLE_X2APIC 0x400 316 #define APICBASE_GLOBAL_ENABLE 0x800 317 #define MSR_EBL_CR_POWERON 0x02a 318 #define MSR_EBC_FREQUENCY_ID 0x02c /* Pentium 4 only */ 319 #define MSR_TEST_CTL 0x033 320 #define MSR_IA32_FEATURE_CONTROL 0x03a 321 #define MSR_BIOS_UPDT_TRIG 0x079 322 #define MSR_BBL_CR_D0 0x088 /* PII+ only */ 323 #define MSR_BBL_CR_D1 0x089 /* PII+ only */ 324 #define MSR_BBL_CR_D2 0x08a /* PII+ only */ 325 #define MSR_BIOS_SIGN 0x08b 326 #define MSR_PERFCTR0 0x0c1 327 #define MSR_PERFCTR1 0x0c2 328 #define MSR_FSB_FREQ 0x0cd /* Core Duo/Solo only */ 329 /* 330 * for Core i Series and newer Xeons, see 331 * http://www.intel.com/content/dam/www/public/us/en/ 332 * documents/white-papers/cpu-monitoring-dts-peci-paper.pdf 333 */ 334 #define MSR_TEMPERATURE_TARGET 0x1a2 /* Core i Series, Newer Xeons */ 335 #define MSR_TEMPERATURE_TARGET_TJMAX(msr) (((msr) >> 16) & 0xff) 336 /* 337 * not documented anywhere, see intelcore_update_sensor() 338 * only available Core Duo and Core Solo Processors 339 */ 340 #define MSR_TEMPERATURE_TARGET_UNDOCUMENTED 0x0ee 341 #define MSR_TEMPERATURE_TARGET_LOW_BIT_UNDOCUMENTED 0x40000000 342 #define MSR_MTRRcap 0x0fe 343 #define MTRRcap_FIXED 0x100 /* bit 8 - fixed MTRRs supported */ 344 #define MTRRcap_WC 0x400 /* bit 10 - WC type supported */ 345 #define MTRRcap_SMRR 0x800 /* bit 11 - SMM range reg supported */ 346 #define MSR_BBL_CR_ADDR 0x116 /* PII+ only */ 347 #define MSR_BBL_CR_DECC 0x118 /* PII+ only */ 348 #define MSR_BBL_CR_CTL 0x119 /* PII+ only */ 349 #define MSR_BBL_CR_TRIG 0x11a /* PII+ only */ 350 #define MSR_BBL_CR_BUSY 0x11b /* PII+ only */ 351 #define MSR_BBL_CR_CTR3 0x11e /* PII+ only */ 352 #define MSR_SYSENTER_CS 0x174 /* PII+ only */ 353 #define MSR_SYSENTER_ESP 0x175 /* PII+ only */ 354 #define MSR_SYSENTER_EIP 0x176 /* PII+ only */ 355 #define MSR_MCG_CAP 0x179 356 #define MSR_MCG_STATUS 0x17a 357 #define MSR_MCG_CTL 0x17b 358 #define MSR_EVNTSEL0 0x186 359 #define MSR_EVNTSEL1 0x187 360 #define MSR_PERF_STATUS 0x198 /* Pentium M */ 361 #define MSR_PERF_CTL 0x199 /* Pentium M */ 362 #define PERF_CTL_TURBO 0x100000000ULL /* bit 32 - turbo mode */ 363 #define MSR_THERM_CONTROL 0x19a 364 #define MSR_THERM_INTERRUPT 0x19b 365 #define MSR_THERM_STATUS 0x19c 366 #define MSR_THERM_STATUS_VALID_BIT 0x80000000 367 #define MSR_THERM_STATUS_TEMP(msr) ((msr >> 16) & 0x7f) 368 #define MSR_THERM2_CTL 0x19d /* Pentium M */ 369 #define MSR_DEBUGCTLMSR 0x1d9 370 #define MSR_LASTBRANCHFROMIP 0x1db 371 #define MSR_LASTBRANCHTOIP 0x1dc 372 #define MSR_LASTINTFROMIP 0x1dd 373 #define MSR_LASTINTTOIP 0x1de 374 #define MSR_ROB_CR_BKUPTMPDR6 0x1e0 375 #define MSR_MTRRvarBase 0x200 376 #define MSR_MTRRfix64K_00000 0x250 377 #define MSR_MTRRfix16K_80000 0x258 378 #define MSR_MTRRfix4K_C0000 0x268 379 #define MSR_CR_PAT 0x277 380 #define MSR_MTRRdefType 0x2ff 381 #define MTRRdefType_FIXED_ENABLE 0x400 /* bit 10 - fixed MTRR enabled */ 382 #define MTRRdefType_ENABLE 0x800 /* bit 11 - MTRRs enabled */ 383 #define MSR_PERF_FIXED_CTR1 0x30a /* CPU_CLK_Unhalted.Core */ 384 #define MSR_PERF_FIXED_CTR2 0x30b /* CPU_CLK.Unhalted.Ref */ 385 #define MSR_PERF_FIXED_CTR_CTRL 0x38d 386 #define MSR_PERF_FIXED_CTR_FC_DIS 0x0 /* disable counter */ 387 #define MSR_PERF_FIXED_CTR_FC_1 0x1 /* count ring 1 */ 388 #define MSR_PERF_FIXED_CTR_FC_123 0x2 /* count rings 1,2,3 */ 389 #define MSR_PERF_FIXED_CTR_FC_ANY 0x3 /* count everything */ 390 #define MSR_PERF_FIXED_CTR_FC_MASK 0x3 391 #define MSR_PERF_FIXED_CTR_FC(_i, _v) ((_v) << (4 * (_i))) 392 #define MSR_PERF_FIXED_CTR_ANYTHR(_i) (0x4 << (4 * (_i))) 393 #define MSR_PERF_FIXED_CTR_INT(_i) (0x8 << (4 * (_i))) 394 #define MSR_PERF_GLOBAL_CTRL 0x38f 395 #define MSR_PERF_GLOBAL_CTR1_EN (1ULL << 33) 396 #define MSR_PERF_GLOBAL_CTR2_EN (1ULL << 34) 397 #define MSR_MC0_CTL 0x400 398 #define MSR_MC0_STATUS 0x401 399 #define MSR_MC0_ADDR 0x402 400 #define MSR_MC0_MISC 0x403 401 #define MSR_MC1_CTL 0x404 402 #define MSR_MC1_STATUS 0x405 403 #define MSR_MC1_ADDR 0x406 404 #define MSR_MC1_MISC 0x407 405 #define MSR_MC2_CTL 0x408 406 #define MSR_MC2_STATUS 0x409 407 #define MSR_MC2_ADDR 0x40a 408 #define MSR_MC2_MISC 0x40b 409 #define MSR_MC4_CTL 0x40c 410 #define MSR_MC4_STATUS 0x40d 411 #define MSR_MC4_ADDR 0x40e 412 #define MSR_MC4_MISC 0x40f 413 #define MSR_MC3_CTL 0x410 414 #define MSR_MC3_STATUS 0x411 415 #define MSR_MC3_ADDR 0x412 416 #define MSR_MC3_MISC 0x413 417 418 /* VIA MSR */ 419 #define MSR_CENT_TMTEMPERATURE 0x1423 /* Thermal monitor temperature */ 420 421 /* 422 * AMD K6/K7 MSRs. 423 */ 424 #define MSR_K6_UWCCR 0xc0000085 425 #define MSR_K7_EVNTSEL0 0xc0010000 426 #define MSR_K7_EVNTSEL1 0xc0010001 427 #define MSR_K7_EVNTSEL2 0xc0010002 428 #define MSR_K7_EVNTSEL3 0xc0010003 429 #define MSR_K7_PERFCTR0 0xc0010004 430 #define MSR_K7_PERFCTR1 0xc0010005 431 #define MSR_K7_PERFCTR2 0xc0010006 432 #define MSR_K7_PERFCTR3 0xc0010007 433 434 /* 435 * AMD K8 (Opteron) MSRs. 436 */ 437 #define MSR_SYSCFG 0xc0000010 438 439 #define MSR_EFER 0xc0000080 /* Extended feature enable */ 440 #define EFER_SCE 0x00000001 /* SYSCALL extension */ 441 #define EFER_LME 0x00000100 /* Long Mode Enabled */ 442 #define EFER_LMA 0x00000400 /* Long Mode Active */ 443 #define EFER_NXE 0x00000800 /* No-Execute Enabled */ 444 #define EFER_SVME 0x00001000 /* SVM Enabled */ 445 446 #define MSR_STAR 0xc0000081 /* 32 bit syscall gate addr */ 447 #define MSR_LSTAR 0xc0000082 /* 64 bit syscall gate addr */ 448 #define MSR_CSTAR 0xc0000083 /* compat syscall gate addr */ 449 #define MSR_SFMASK 0xc0000084 /* flags to clear on syscall */ 450 451 #define MSR_FSBASE 0xc0000100 /* 64bit offset for fs: */ 452 #define MSR_GSBASE 0xc0000101 /* 64bit offset for gs: */ 453 #define MSR_KERNELGSBASE 0xc0000102 /* storage for swapgs ins */ 454 #define MSR_INT_PEN_MSG 0xc0010055 /* Interrupt pending message */ 455 456 #define MSR_DE_CFG 0xc0011029 /* Decode Configuration */ 457 #define DE_CFG_721 0x00000001 /* errata 721 */ 458 459 #define IPM_C1E_CMP_HLT 0x10000000 460 #define IPM_SMI_CMP_HLT 0x08000000 461 462 /* 463 * These require a 'passcode' for access. See cpufunc.h. 464 */ 465 #define MSR_HWCR 0xc0010015 466 #define HWCR_FFDIS 0x00000040 467 468 #define MSR_NB_CFG 0xc001001f 469 #define NB_CFG_DISIOREQLOCK 0x0000000000000004ULL 470 #define NB_CFG_DISDATMSK 0x0000001000000000ULL 471 472 #define MSR_LS_CFG 0xc0011020 473 #define LS_CFG_DIS_LS2_SQUISH 0x02000000 474 475 #define MSR_IC_CFG 0xc0011021 476 #define IC_CFG_DIS_SEQ_PREFETCH 0x00000800 477 478 #define MSR_DC_CFG 0xc0011022 479 #define DC_CFG_DIS_CNV_WC_SSO 0x00000004 480 #define DC_CFG_DIS_SMC_CHK_BUF 0x00000400 481 482 #define MSR_BU_CFG 0xc0011023 483 #define BU_CFG_THRL2IDXCMPDIS 0x0000080000000000ULL 484 #define BU_CFG_WBPFSMCCHKDIS 0x0000200000000000ULL 485 #define BU_CFG_WBENHWSBDIS 0x0001000000000000ULL 486 487 /* 488 * Constants related to MTRRs 489 */ 490 #define MTRR_N64K 8 /* numbers of fixed-size entries */ 491 #define MTRR_N16K 16 492 #define MTRR_N4K 64 493 494 /* 495 * the following four 3-byte registers control the non-cacheable regions. 496 * These registers must be written as three separate bytes. 497 * 498 * NCRx+0: A31-A24 of starting address 499 * NCRx+1: A23-A16 of starting address 500 * NCRx+2: A15-A12 of starting address | NCR_SIZE_xx. 501 * 502 * The non-cacheable region's starting address must be aligned to the 503 * size indicated by the NCR_SIZE_xx field. 504 */ 505 #define NCR1 0xc4 506 #define NCR2 0xc7 507 #define NCR3 0xca 508 #define NCR4 0xcd 509 510 #define NCR_SIZE_0K 0 511 #define NCR_SIZE_4K 1 512 #define NCR_SIZE_8K 2 513 #define NCR_SIZE_16K 3 514 #define NCR_SIZE_32K 4 515 #define NCR_SIZE_64K 5 516 #define NCR_SIZE_128K 6 517 #define NCR_SIZE_256K 7 518 #define NCR_SIZE_512K 8 519 #define NCR_SIZE_1M 9 520 #define NCR_SIZE_2M 10 521 #define NCR_SIZE_4M 11 522 #define NCR_SIZE_8M 12 523 #define NCR_SIZE_16M 13 524 #define NCR_SIZE_32M 14 525 #define NCR_SIZE_4G 15 526 527 /* 528 * Performance monitor events. 529 * 530 * Note that 586-class and 686-class CPUs have different performance 531 * monitors available, and they are accessed differently: 532 * 533 * 686-class: `rdpmc' instruction 534 * 586-class: `rdmsr' instruction, CESR MSR 535 * 536 * The descriptions of these events are too lengthy to include here. 537 * See Appendix A of "Intel Architecture Software Developer's 538 * Manual, Volume 3: System Programming" for more information. 539 */ 540 541 /* 542 * 586-class CESR MSR format. Lower 16 bits is CTR0, upper 16 bits 543 * is CTR1. 544 */ 545 546 #define PMC5_CESR_EVENT 0x003f 547 #define PMC5_CESR_OS 0x0040 548 #define PMC5_CESR_USR 0x0080 549 #define PMC5_CESR_E 0x0100 550 #define PMC5_CESR_P 0x0200 551 552 #define PMC5_DATA_READ 0x00 553 #define PMC5_DATA_WRITE 0x01 554 #define PMC5_DATA_TLB_MISS 0x02 555 #define PMC5_DATA_READ_MISS 0x03 556 #define PMC5_DATA_WRITE_MISS 0x04 557 #define PMC5_WRITE_M_E 0x05 558 #define PMC5_DATA_LINES_WBACK 0x06 559 #define PMC5_DATA_CACHE_SNOOP 0x07 560 #define PMC5_DATA_CACHE_SNOOP_HIT 0x08 561 #define PMC5_MEM_ACCESS_BOTH_PIPES 0x09 562 #define PMC5_BANK_CONFLICTS 0x0a 563 #define PMC5_MISALIGNED_DATA 0x0b 564 #define PMC5_INST_READ 0x0c 565 #define PMC5_INST_TLB_MISS 0x0d 566 #define PMC5_INST_CACHE_MISS 0x0e 567 #define PMC5_SEGMENT_REG_LOAD 0x0f 568 #define PMC5_BRANCHES 0x12 569 #define PMC5_BTB_HITS 0x13 570 #define PMC5_BRANCH_TAKEN 0x14 571 #define PMC5_PIPELINE_FLUSH 0x15 572 #define PMC5_INST_EXECUTED 0x16 573 #define PMC5_INST_EXECUTED_V_PIPE 0x17 574 #define PMC5_BUS_UTILIZATION 0x18 575 #define PMC5_WRITE_BACKUP_STALL 0x19 576 #define PMC5_DATA_READ_STALL 0x1a 577 #define PMC5_WRITE_E_M_STALL 0x1b 578 #define PMC5_LOCKED_BUS 0x1c 579 #define PMC5_IO_CYCLE 0x1d 580 #define PMC5_NONCACHE_MEM_READ 0x1e 581 #define PMC5_AGI_STALL 0x1f 582 #define PMC5_FLOPS 0x22 583 #define PMC5_BP0_MATCH 0x23 584 #define PMC5_BP1_MATCH 0x24 585 #define PMC5_BP2_MATCH 0x25 586 #define PMC5_BP3_MATCH 0x26 587 #define PMC5_HARDWARE_INTR 0x27 588 #define PMC5_DATA_RW 0x28 589 #define PMC5_DATA_RW_MISS 0x29 590 591 /* 592 * 686-class Event Selector MSR format. 593 */ 594 595 #define PMC6_EVTSEL_EVENT 0x000000ff 596 #define PMC6_EVTSEL_UNIT 0x0000ff00 597 #define PMC6_EVTSEL_UNIT_SHIFT 8 598 #define PMC6_EVTSEL_USR (1 << 16) 599 #define PMC6_EVTSEL_OS (1 << 17) 600 #define PMC6_EVTSEL_E (1 << 18) 601 #define PMC6_EVTSEL_PC (1 << 19) 602 #define PMC6_EVTSEL_INT (1 << 20) 603 #define PMC6_EVTSEL_EN (1 << 22) /* PerfEvtSel0 only */ 604 #define PMC6_EVTSEL_INV (1 << 23) 605 #define PMC6_EVTSEL_COUNTER_MASK 0xff000000 606 #define PMC6_EVTSEL_COUNTER_MASK_SHIFT 24 607 608 /* Data Cache Unit */ 609 #define PMC6_DATA_MEM_REFS 0x43 610 #define PMC6_DCU_LINES_IN 0x45 611 #define PMC6_DCU_M_LINES_IN 0x46 612 #define PMC6_DCU_M_LINES_OUT 0x47 613 #define PMC6_DCU_MISS_OUTSTANDING 0x48 614 615 /* Instruction Fetch Unit */ 616 #define PMC6_IFU_IFETCH 0x80 617 #define PMC6_IFU_IFETCH_MISS 0x81 618 #define PMC6_ITLB_MISS 0x85 619 #define PMC6_IFU_MEM_STALL 0x86 620 #define PMC6_ILD_STALL 0x87 621 622 /* L2 Cache */ 623 #define PMC6_L2_IFETCH 0x28 624 #define PMC6_L2_LD 0x29 625 #define PMC6_L2_ST 0x2a 626 #define PMC6_L2_LINES_IN 0x24 627 #define PMC6_L2_LINES_OUT 0x26 628 #define PMC6_L2_M_LINES_INM 0x25 629 #define PMC6_L2_M_LINES_OUTM 0x27 630 #define PMC6_L2_RQSTS 0x2e 631 #define PMC6_L2_ADS 0x21 632 #define PMC6_L2_DBUS_BUSY 0x22 633 #define PMC6_L2_DBUS_BUSY_RD 0x23 634 635 /* External Bus Logic */ 636 #define PMC6_BUS_DRDY_CLOCKS 0x62 637 #define PMC6_BUS_LOCK_CLOCKS 0x63 638 #define PMC6_BUS_REQ_OUTSTANDING 0x60 639 #define PMC6_BUS_TRAN_BRD 0x65 640 #define PMC6_BUS_TRAN_RFO 0x66 641 #define PMC6_BUS_TRANS_WB 0x67 642 #define PMC6_BUS_TRAN_IFETCH 0x68 643 #define PMC6_BUS_TRAN_INVAL 0x69 644 #define PMC6_BUS_TRAN_PWR 0x6a 645 #define PMC6_BUS_TRANS_P 0x6b 646 #define PMC6_BUS_TRANS_IO 0x6c 647 #define PMC6_BUS_TRAN_DEF 0x6d 648 #define PMC6_BUS_TRAN_BURST 0x6e 649 #define PMC6_BUS_TRAN_ANY 0x70 650 #define PMC6_BUS_TRAN_MEM 0x6f 651 #define PMC6_BUS_DATA_RCV 0x64 652 #define PMC6_BUS_BNR_DRV 0x61 653 #define PMC6_BUS_HIT_DRV 0x7a 654 #define PMC6_BUS_HITM_DRDV 0x7b 655 #define PMC6_BUS_SNOOP_STALL 0x7e 656 657 /* Floating Point Unit */ 658 #define PMC6_FLOPS 0xc1 659 #define PMC6_FP_COMP_OPS_EXE 0x10 660 #define PMC6_FP_ASSIST 0x11 661 #define PMC6_MUL 0x12 662 #define PMC6_DIV 0x12 663 #define PMC6_CYCLES_DIV_BUSY 0x14 664 665 /* Memory Ordering */ 666 #define PMC6_LD_BLOCKS 0x03 667 #define PMC6_SB_DRAINS 0x04 668 #define PMC6_MISALIGN_MEM_REF 0x05 669 #define PMC6_EMON_KNI_PREF_DISPATCHED 0x07 /* P-III only */ 670 #define PMC6_EMON_KNI_PREF_MISS 0x4b /* P-III only */ 671 672 /* Instruction Decoding and Retirement */ 673 #define PMC6_INST_RETIRED 0xc0 674 #define PMC6_UOPS_RETIRED 0xc2 675 #define PMC6_INST_DECODED 0xd0 676 #define PMC6_EMON_KNI_INST_RETIRED 0xd8 677 #define PMC6_EMON_KNI_COMP_INST_RET 0xd9 678 679 /* Interrupts */ 680 #define PMC6_HW_INT_RX 0xc8 681 #define PMC6_CYCLES_INT_MASKED 0xc6 682 #define PMC6_CYCLES_INT_PENDING_AND_MASKED 0xc7 683 684 /* Branches */ 685 #define PMC6_BR_INST_RETIRED 0xc4 686 #define PMC6_BR_MISS_PRED_RETIRED 0xc5 687 #define PMC6_BR_TAKEN_RETIRED 0xc9 688 #define PMC6_BR_MISS_PRED_TAKEN_RET 0xca 689 #define PMC6_BR_INST_DECODED 0xe0 690 #define PMC6_BTB_MISSES 0xe2 691 #define PMC6_BR_BOGUS 0xe4 692 #define PMC6_BACLEARS 0xe6 693 694 /* Stalls */ 695 #define PMC6_RESOURCE_STALLS 0xa2 696 #define PMC6_PARTIAL_RAT_STALLS 0xd2 697 698 /* Segment Register Loads */ 699 #define PMC6_SEGMENT_REG_LOADS 0x06 700 701 /* Clocks */ 702 #define PMC6_CPU_CLK_UNHALTED 0x79 703 704 /* MMX Unit */ 705 #define PMC6_MMX_INSTR_EXEC 0xb0 /* Celeron, P-II, P-IIX only */ 706 #define PMC6_MMX_SAT_INSTR_EXEC 0xb1 /* P-II and P-III only */ 707 #define PMC6_MMX_UOPS_EXEC 0xb2 /* P-II and P-III only */ 708 #define PMC6_MMX_INSTR_TYPE_EXEC 0xb3 /* P-II and P-III only */ 709 #define PMC6_FP_MMX_TRANS 0xcc /* P-II and P-III only */ 710 #define PMC6_MMX_ASSIST 0xcd /* P-II and P-III only */ 711 #define PMC6_MMX_INSTR_RET 0xc3 /* P-II only */ 712 713 /* Segment Register Renaming */ 714 #define PMC6_SEG_RENAME_STALLS 0xd4 /* P-II and P-III only */ 715 #define PMC6_SEG_REG_RENAMES 0xd5 /* P-II and P-III only */ 716 #define PMC6_RET_SEG_RENAMES 0xd6 /* P-II and P-III only */ 717 718 /* 719 * AMD K7 Event Selector MSR format. 720 */ 721 722 #define K7_EVTSEL_EVENT 0x000000ff 723 #define K7_EVTSEL_UNIT 0x0000ff00 724 #define K7_EVTSEL_UNIT_SHIFT 8 725 #define K7_EVTSEL_USR (1 << 16) 726 #define K7_EVTSEL_OS (1 << 17) 727 #define K7_EVTSEL_E (1 << 18) 728 #define K7_EVTSEL_PC (1 << 19) 729 #define K7_EVTSEL_INT (1 << 20) 730 #define K7_EVTSEL_EN (1 << 22) 731 #define K7_EVTSEL_INV (1 << 23) 732 #define K7_EVTSEL_COUNTER_MASK 0xff000000 733 #define K7_EVTSEL_COUNTER_MASK_SHIFT 24 734 735 /* Segment Register Loads */ 736 #define K7_SEGMENT_REG_LOADS 0x20 737 738 #define K7_STORES_TO_ACTIVE_INST_STREAM 0x21 739 740 /* Data Cache Unit */ 741 #define K7_DATA_CACHE_ACCESS 0x40 742 #define K7_DATA_CACHE_MISS 0x41 743 #define K7_DATA_CACHE_REFILL 0x42 744 #define K7_DATA_CACHE_REFILL_SYSTEM 0x43 745 #define K7_DATA_CACHE_WBACK 0x44 746 #define K7_L2_DTLB_HIT 0x45 747 #define K7_L2_DTLB_MISS 0x46 748 #define K7_MISALIGNED_DATA_REF 0x47 749 #define K7_SYSTEM_REQUEST 0x64 750 #define K7_SYSTEM_REQUEST_TYPE 0x65 751 752 #define K7_SNOOP_HIT 0x73 753 #define K7_SINGLE_BIT_ECC_ERROR 0x74 754 #define K7_CACHE_LINE_INVAL 0x75 755 #define K7_CYCLES_PROCESSOR_IS_RUNNING 0x76 756 #define K7_L2_REQUEST 0x79 757 #define K7_L2_REQUEST_BUSY 0x7a 758 759 /* Instruction Fetch Unit */ 760 #define K7_IFU_IFETCH 0x80 761 #define K7_IFU_IFETCH_MISS 0x81 762 #define K7_IFU_REFILL_FROM_L2 0x82 763 #define K7_IFU_REFILL_FROM_SYSTEM 0x83 764 #define K7_ITLB_L1_MISS 0x84 765 #define K7_ITLB_L2_MISS 0x85 766 #define K7_SNOOP_RESYNC 0x86 767 #define K7_IFU_STALL 0x87 768 769 #define K7_RETURN_STACK_HITS 0x88 770 #define K7_RETURN_STACK_OVERFLOW 0x89 771 772 /* Retired */ 773 #define K7_RETIRED_INST 0xc0 774 #define K7_RETIRED_OPS 0xc1 775 #define K7_RETIRED_BRANCHES 0xc2 776 #define K7_RETIRED_BRANCH_MISPREDICTED 0xc3 777 #define K7_RETIRED_TAKEN_BRANCH 0xc4 778 #define K7_RETIRED_TAKEN_BRANCH_MISPREDICTED 0xc5 779 #define K7_RETIRED_FAR_CONTROL_TRANSFER 0xc6 780 #define K7_RETIRED_RESYNC_BRANCH 0xc7 781 #define K7_RETIRED_NEAR_RETURNS 0xc8 782 #define K7_RETIRED_NEAR_RETURNS_MISPREDICTED 0xc9 783 #define K7_RETIRED_INDIRECT_MISPREDICTED 0xca 784 785 /* Interrupts */ 786 #define K7_CYCLES_INT_MASKED 0xcd 787 #define K7_CYCLES_INT_PENDING_AND_MASKED 0xce 788 #define K7_HW_INTR_RECV 0xcf 789 790 #define K7_INSTRUCTION_DECODER_EMPTY 0xd0 791 #define K7_DISPATCH_STALLS 0xd1 792 #define K7_BRANCH_ABORTS_TO_RETIRE 0xd2 793 #define K7_SERIALIZE 0xd3 794 #define K7_SEGMENT_LOAD_STALL 0xd4 795 #define K7_ICU_FULL 0xd5 796 #define K7_RESERVATION_STATIONS_FULL 0xd6 797 #define K7_FPU_FULL 0xd7 798 #define K7_LS_FULL 0xd8 799 #define K7_ALL_QUIET_STALL 0xd9 800 #define K7_FAR_TRANSFER_OR_RESYNC_BRANCH_PENDING 0xda 801 802 #define K7_BP0_MATCH 0xdc 803 #define K7_BP1_MATCH 0xdd 804 #define K7_BP2_MATCH 0xde 805 #define K7_BP3_MATCH 0xdf 806 807 /* VIA C3 crypto featureset: for i386_has_xcrypt */ 808 #define C3_HAS_AES 1 /* cpu has AES */ 809 #define C3_HAS_SHA 2 /* cpu has SHA1 & SHA256 */ 810 #define C3_HAS_MM 4 /* cpu has RSA instructions */ 811 #define C3_HAS_AESCTR 8 /* cpu has AES-CTR instructions */ 812 813 /* Centaur Extended Feature flags */ 814 #define C3_CPUID_HAS_RNG 0x000004 815 #define C3_CPUID_DO_RNG 0x000008 816 #define C3_CPUID_HAS_ACE 0x000040 817 #define C3_CPUID_DO_ACE 0x000080 818 #define C3_CPUID_HAS_ACE2 0x000100 819 #define C3_CPUID_DO_ACE2 0x000200 820 #define C3_CPUID_HAS_PHE 0x000400 821 #define C3_CPUID_DO_PHE 0x000800 822 #define C3_CPUID_HAS_PMM 0x001000 823 #define C3_CPUID_DO_PMM 0x002000 824 825 /* VIA C3 xcrypt-* instruction context control options */ 826 #define C3_CRYPT_CWLO_ROUND_M 0x0000000f 827 #define C3_CRYPT_CWLO_ALG_M 0x00000070 828 #define C3_CRYPT_CWLO_ALG_AES 0x00000000 829 #define C3_CRYPT_CWLO_KEYGEN_M 0x00000080 830 #define C3_CRYPT_CWLO_KEYGEN_HW 0x00000000 831 #define C3_CRYPT_CWLO_KEYGEN_SW 0x00000080 832 #define C3_CRYPT_CWLO_NORMAL 0x00000000 833 #define C3_CRYPT_CWLO_INTERMEDIATE 0x00000100 834 #define C3_CRYPT_CWLO_ENCRYPT 0x00000000 835 #define C3_CRYPT_CWLO_DECRYPT 0x00000200 836 #define C3_CRYPT_CWLO_KEY128 0x0000000a /* 128bit, 10 rds */ 837 #define C3_CRYPT_CWLO_KEY192 0x0000040c /* 192bit, 12 rds */ 838 #define C3_CRYPT_CWLO_KEY256 0x0000080e /* 256bit, 15 rds */ 839 840 /* 841 * VMX 842 */ 843 #define IA32_FEATURE_CONTROL_LOCK 0x01 844 #define IA32_FEATURE_CONTROL_SMX_EN 0x02 845 #define IA32_FEATURE_CONTROL_VMX_EN 0x04 846 #define IA32_FEATURE_CONTROL_SENTER_EN (1ULL << 15) 847 #define IA32_FEATURE_CONTROL_SENTER_PARAM_MASK 0x7f00 848 #define IA32_VMX_BASIC 0x480 849 #define IA32_VMX_PINBASED_CTLS 0x481 850 #define IA32_VMX_PROCBASED_CTLS 0x482 851 #define IA32_VMX_EXIT_CTLS 0x483 852 #define IA32_VMX_ENTRY_CTLS 0x484 853 #define IA32_VMX_MISC 0x485 854 #define IA32_VMX_CR0_FIXED0 0x486 855 #define IA32_VMX_CR0_FIXED1 0x487 856 #define IA32_VMX_CR4_FIXED0 0x488 857 #define IA32_VMX_CR4_FIXED1 0x489 858 #define IA32_VMX_PROCBASED2_CTLS 0x48B 859 #define IA32_VMX_EPT_VPID_CAP 0x48C 860 #define IA32_VMX_TRUE_PINBASED_CTLS 0x48D 861 #define IA32_VMX_TRUE_PROCBASED_CTLS 0x48E 862 #define IA32_VMX_TRUE_EXIT_CTLS 0x48F 863 #define IA32_VMX_TRUE_ENTRY_CTLS 0x490 864 865 #define IA32_EPT_VPID_CAP_PAGE_WALK_4 (1ULL << 6) 866 #define IA32_EPT_VPID_CAP_WB (1ULL << 14) 867 #define IA32_EPT_VPID_CAP_AD_BITS (1ULL << 21) 868 869 #define IA32_EPT_PAGING_CACHE_TYPE_UC 0x0 870 #define IA32_EPT_PAGING_CACHE_TYPE_WB 0x6 871 #define IA32_EPT_AD_BITS_ENABLE (1ULL << 6) 872 #define IA32_EPT_PAGE_WALK_LENGTH 0x4 873 874 /* VMX : IA32_VMX_BASIC bits */ 875 #define IA32_VMX_TRUE_CTLS_AVAIL (1ULL << 55) 876 877 /* VMX : IA32_VMX_PINBASED_CTLS bits */ 878 #define IA32_VMX_EXTERNAL_INT_EXITING (1ULL << 0) 879 #define IA32_VMX_NMI_EXITING (1ULL << 3) 880 #define IA32_VMX_VIRTUAL_NMIS (1ULL << 5) 881 #define IA32_VMX_ACTIVATE_VMX_PREEMPTION_TIMER (1ULL << 6) 882 #define IA32_VMX_PROCESS_POSTED_INTERRUPTS (1ULL << 7) 883 884 /* VMX : IA32_VMX_PROCBASED_CTLS bits */ 885 #define IA32_VMX_INTERRUPT_WINDOW_EXITING (1ULL << 2) 886 #define IA32_VMX_USE_TSC_OFFSETTING (1ULL << 3) 887 #define IA32_VMX_HLT_EXITING (1ULL << 7) 888 #define IA32_VMX_INVLPG_EXITING (1ULL << 9) 889 #define IA32_VMX_MWAIT_EXITING (1ULL << 10) 890 #define IA32_VMX_RDPMC_EXITING (1ULL << 11) 891 #define IA32_VMX_RDTSC_EXITING (1ULL << 12) 892 #define IA32_VMX_CR3_LOAD_EXITING (1ULL << 15) 893 #define IA32_VMX_CR3_STORE_EXITING (1ULL << 16) 894 #define IA32_VMX_CR8_LOAD_EXITING (1ULL << 19) 895 #define IA32_VMX_CR8_STORE_EXITING (1ULL << 20) 896 #define IA32_VMX_USE_TPR_SHADOW (1ULL << 21) 897 #define IA32_VMX_NMI_WINDOW_EXITING (1ULL << 22) 898 #define IA32_VMX_MOV_DR_EXITING (1ULL << 23) 899 #define IA32_VMX_UNCONDITIONAL_IO_EXITING (1ULL << 24) 900 #define IA32_VMX_USE_IO_BITMAPS (1ULL << 25) 901 #define IA32_VMX_MONITOR_TRAP_FLAG (1ULL << 27) 902 #define IA32_VMX_USE_MSR_BITMAPS (1ULL << 28) 903 #define IA32_VMX_MONITOR_EXITING (1ULL << 29) 904 #define IA32_VMX_PAUSE_EXITING (1ULL << 30) 905 #define IA32_VMX_ACTIVATE_SECONDARY_CONTROLS (1ULL << 31) 906 907 /* VMX : IA32_VMX_PROCBASED2_CTLS bits */ 908 #define IA32_VMX_VIRTUALIZE_APIC (1ULL << 0) 909 #define IA32_VMX_ENABLE_EPT (1ULL << 1) 910 #define IA32_VMX_DESCRIPTOR_TABLE_EXITING (1ULL << 2) 911 #define IA32_VMX_ENABLE_RDTSCP (1ULL << 3) 912 #define IA32_VMX_VIRTUALIZE_X2APIC_MODE (1ULL << 4) 913 #define IA32_VMX_ENABLE_VPID (1ULL << 5) 914 #define IA32_VMX_WBINVD_EXITING (1ULL << 6) 915 #define IA32_VMX_UNRESTRICTED_GUEST (1ULL << 7) 916 #define IA32_VMX_APIC_REGISTER_VIRTUALIZATION (1ULL << 8) 917 #define IA32_VMX_VIRTUAL_INTERRUPT_DELIVERY (1ULL << 9) 918 #define IA32_VMX_PAUSE_LOOP_EXITING (1ULL << 10) 919 #define IA32_VMX_RDRAND_EXITING (1ULL << 11) 920 #define IA32_VMX_ENABLE_INVPCID (1ULL << 12) 921 #define IA32_VMX_ENABLE_VM_FUNCTIONS (1ULL << 13) 922 #define IA32_VMX_VMCS_SHADOWING (1ULL << 14) 923 #define IA32_VMX_ENABLE_ENCLS_EXITING (1ULL << 15) 924 #define IA32_VMX_RDSEED_EXITING (1ULL << 16) 925 #define IA32_VMX_ENABLE_PML (1ULL << 17) 926 #define IA32_VMX_EPT_VIOLATION_VE (1ULL << 18) 927 #define IA32_VMX_CONCEAL_VMX_FROM_PT (1ULL << 19) 928 #define IA32_VMX_ENABLE_XSAVES_XRSTORS (1ULL << 20) 929 #define IA32_VMX_ENABLE_TSC_SCALING (1ULL << 25) 930 931 /* VMX : IA32_VMX_EXIT_CTLS bits */ 932 #define IA32_VMX_SAVE_DEBUG_CONTROLS (1ULL << 2) 933 #define IA32_VMX_HOST_SPACE_ADDRESS_SIZE (1ULL << 9) 934 #define IA32_VMX_LOAD_IA32_PERF_GLOBAL_CTRL_ON_EXIT (1ULL << 12) 935 #define IA32_VMX_ACKNOWLEDGE_INTERRUPT_ON_EXIT (1ULL << 15) 936 #define IA32_VMX_SAVE_IA32_PAT_ON_EXIT (1ULL << 18) 937 #define IA32_VMX_LOAD_IA32_PAT_ON_EXIT (1ULL << 19) 938 #define IA32_VMX_SAVE_IA32_EFER_ON_EXIT (1ULL << 20) 939 #define IA32_VMX_LOAD_IA32_EFER_ON_EXIT (1ULL << 21) 940 #define IA32_VMX_SAVE_VMX_PREEMPTION_TIMER (1ULL << 22) 941 #define IA32_VMX_CLEAR_IA32_BNDCFGS_ON_EXIT (1ULL << 23) 942 #define IA32_VMX_CONCEAL_VM_EXITS_FROM_PT (1ULL << 24) 943 944 /* VMX: IA32_VMX_ENTRY_CTLS bits */ 945 #define IA32_VMX_LOAD_DEBUG_CONTROLS (1ULL << 2) 946 #define IA32_VMX_IA32E_MODE_GUEST (1ULL << 9) 947 #define IA32_VMX_ENTRY_TO_SMM (1ULL << 10) 948 #define IA32_VMX_DEACTIVATE_DUAL_MONITOR_TREATMENT (1ULL << 11) 949 #define IA32_VMX_LOAD_IA32_PERF_GLOBAL_CTRL_ON_ENTRY (1ULL << 13) 950 #define IA32_VMX_LOAD_IA32_PAT_ON_ENTRY (1ULL << 14) 951 #define IA32_VMX_LOAD_IA32_EFER_ON_ENTRY (1ULL << 15) 952 #define IA32_VMX_LOAD_IA32_BNDCFGS_ON_ENTRY (1ULL << 16) 953 #define IA32_VMX_CONCEAL_VM_ENTRIES_FROM_PT (1ULL << 17) 954 955 /* VMX : VMCS Fields */ 956 #define VMCS_GUEST_VPID 0x0000 957 #define VMCS_GUEST_IA32_ES_SEL 0x0800 958 #define VMCS_GUEST_IA32_CS_SEL 0x0802 959 #define VMCS_GUEST_IA32_SS_SEL 0x0804 960 #define VMCS_GUEST_IA32_DS_SEL 0x0806 961 #define VMCS_GUEST_IA32_FS_SEL 0x0808 962 #define VMCS_GUEST_IA32_GS_SEL 0x080A 963 #define VMCS_GUEST_IA32_LDTR_SEL 0x080C 964 #define VMCS_GUEST_IA32_TR_SEL 0x080E 965 #define VMCS_HOST_IA32_ES_SEL 0x0C00 966 #define VMCS_HOST_IA32_CS_SEL 0x0C02 967 #define VMCS_HOST_IA32_SS_SEL 0x0C04 968 #define VMCS_HOST_IA32_DS_SEL 0x0C06 969 #define VMCS_HOST_IA32_FS_SEL 0x0C08 970 #define VMCS_HOST_IA32_GS_SEL 0x0C0A 971 #define VMCS_HOST_IA32_TR_SEL 0x0C0C 972 #define VMCS_MSR_BITMAP_ADDRESS 0x2004 973 #define VMCS_EXIT_STORE_MSR_ADDRESS 0x2006 974 #define VMCS_EXIT_LOAD_MSR_ADDRESS 0x2008 975 #define VMCS_ENTRY_LOAD_MSR_ADDRESS 0x200A 976 #define VMCS_APIC_ACCESS_ADDRESS 0x2014 977 #define VMCS_GUEST_IA32_EPTP 0x201A 978 #define VMCS_GUEST_PHYSICAL_ADDRESS 0x2400 979 #define VMCS_LINK_POINTER 0x2800 980 #define VMCS_GUEST_IA32_PAT 0x2804 981 #define VMCS_HOST_IA32_PAT 0x2C00 982 #define VMCS_HOST_IA32_EFER 0x2C02 983 #define VMCS_PINBASED_CTLS 0x4000 984 #define VMCS_PROCBASED_CTLS 0x4002 985 #define VMCS_EXIT_CTLS 0x400C 986 #define VMCS_EXIT_MSR_STORE_COUNT 0x400E 987 #define VMCS_EXIT_MSR_LOAD_COUNT 0x4010 988 #define VMCS_ENTRY_CTLS 0x4012 989 #define VMCS_ENTRY_MSR_LOAD_COUNT 0x4014 990 #define VMCS_ENTRY_INTERRUPTION_INFO 0x4016 991 #define VMCS_PROCBASED2_CTLS 0x401E 992 #define VMCS_INSTRUCTION_ERROR 0x4400 993 #define VMCS_EXIT_REASON 0x4402 994 #define VMCS_EXIT_INTERRUPTION_INFO 0x4404 995 #define VMCS_INSTRUCTION_LENGTH 0x440C 996 #define VMCS_GUEST_IA32_ES_LIMIT 0x4800 997 #define VMCS_GUEST_IA32_CS_LIMIT 0x4802 998 #define VMCS_GUEST_IA32_SS_LIMIT 0x4804 999 #define VMCS_GUEST_IA32_DS_LIMIT 0x4806 1000 #define VMCS_GUEST_IA32_FS_LIMIT 0x4808 1001 #define VMCS_GUEST_IA32_GS_LIMIT 0x480A 1002 #define VMCS_GUEST_IA32_LDTR_LIMIT 0x480C 1003 #define VMCS_GUEST_IA32_TR_LIMIT 0x480E 1004 #define VMCS_GUEST_IA32_GDTR_LIMIT 0x4810 1005 #define VMCS_GUEST_IA32_IDTR_LIMIT 0x4812 1006 #define VMCS_GUEST_IA32_ES_AR 0x4814 1007 #define VMCS_GUEST_IA32_CS_AR 0x4816 1008 #define VMCS_GUEST_IA32_SS_AR 0x4818 1009 #define VMCS_GUEST_IA32_DS_AR 0x481A 1010 #define VMCS_GUEST_IA32_FS_AR 0x481C 1011 #define VMCS_GUEST_IA32_GS_AR 0x481E 1012 #define VMCS_GUEST_IA32_LDTR_AR 0x4820 1013 #define VMCS_GUEST_IA32_TR_AR 0x4822 1014 #define VMCS_GUEST_EXIT_QUALIFICATION 0x6400 1015 #define VMCS_GUEST_IA32_CR0 0x6800 1016 #define VMCS_GUEST_IA32_CR3 0x6802 1017 #define VMCS_GUEST_IA32_CR4 0x6804 1018 #define VMCS_GUEST_IA32_ES_BASE 0x6806 1019 #define VMCS_GUEST_IA32_CS_BASE 0x6808 1020 #define VMCS_GUEST_IA32_SS_BASE 0x680A 1021 #define VMCS_GUEST_IA32_DS_BASE 0x680C 1022 #define VMCS_GUEST_IA32_FS_BASE 0x680E 1023 #define VMCS_GUEST_IA32_GS_BASE 0x6810 1024 #define VMCS_GUEST_IA32_LDTR_BASE 0x6812 1025 #define VMCS_GUEST_IA32_TR_BASE 0x6814 1026 #define VMCS_GUEST_IA32_GDTR_BASE 0x6816 1027 #define VMCS_GUEST_IA32_IDTR_BASE 0x6818 1028 #define VMCS_GUEST_IA32_RSP 0x681C 1029 #define VMCS_GUEST_IA32_RIP 0x681E 1030 #define VMCS_GUEST_IA32_RFLAGS 0x6820 1031 #define VMCS_HOST_IA32_CR0 0x6C00 1032 #define VMCS_HOST_IA32_CR3 0x6C02 1033 #define VMCS_HOST_IA32_CR4 0x6C04 1034 #define VMCS_HOST_IA32_FS_BASE 0x6C06 1035 #define VMCS_HOST_IA32_TR_BASE 0x6C0A 1036 #define VMCS_HOST_IA32_GDTR_BASE 0x6C0C 1037 #define VMCS_HOST_IA32_IDTR_BASE 0x6C0E 1038 #define VMCS_HOST_IA32_RSP 0x6C14 1039 #define VMCS_HOST_IA32_RIP 0x6C16 1040 1041 #define IA32_VMX_INVVPID_INDIV_ADDR_CTX 0x0 1042 #define IA32_VMX_INVVPID_SINGLE_CTX 0x1 1043 #define IA32_VMX_INVVPID_ALL_CTX 0x2 1044 #define IA32_VMX_INVVPID_SINGLE_CTX_GLB 0x3 1045 1046 #define IA32_VMX_INVEPT_SINGLE_CTX 0x1 1047 #define IA32_VMX_INVEPT_GLOBAL_CTX 0x2 1048 1049 #define IA32_VMX_EPT_FAULT_READ (1ULL << 0) 1050 #define IA32_VMX_EPT_FAULT_WRITE (1ULL << 1) 1051 #define IA32_VMX_EPT_FAULT_EXEC (1ULL << 2) 1052 1053 #define IA32_VMX_EPT_FAULT_WAS_READABLE (1ULL << 3) 1054 #define IA32_VMX_EPT_FAULT_WAS_WRITABLE (1ULL << 4) 1055 #define IA32_VMX_EPT_FAULT_WAS_EXECABLE (1ULL << 5) 1056 1057 #define IA32_VMX_MSR_LIST_SIZE_MASK (7ULL << 25) 1058 1059 /* 1060 * SVM 1061 */ 1062 #define MSR_AMD_VM_CR 0xc0010114 1063 #define CPUID_AMD_SVM_CAP 0x8000000A 1064 #define AMD_SVMDIS 0x10 1065 #define AMD_SVM_NESTED_PAGING_CAP (1 << 0) 1066 1067 /* 1068 * PAT 1069 */ 1070 #define PATENTRY(n, type) (type << ((n) * 8)) 1071 #define PAT_UC 0x0UL 1072 #define PAT_WC 0x1UL 1073 #define PAT_WT 0x4UL 1074 #define PAT_WP 0x5UL 1075 #define PAT_WB 0x6UL 1076 #define PAT_UCMINUS 0x7UL 1077 1078