1 /* $OpenBSD: pmap.h,v 1.78 2021/06/18 06:17:28 guenther Exp $ */ 2 /* $NetBSD: pmap.h,v 1.1 2003/04/26 18:39:46 fvdl Exp $ */ 3 4 /* 5 * Copyright (c) 1997 Charles D. Cranor and Washington University. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 /* 30 * Copyright (c) 2001 Wasabi Systems, Inc. 31 * All rights reserved. 32 * 33 * Written by Frank van der Linden for Wasabi Systems, Inc. 34 * 35 * Redistribution and use in source and binary forms, with or without 36 * modification, are permitted provided that the following conditions 37 * are met: 38 * 1. Redistributions of source code must retain the above copyright 39 * notice, this list of conditions and the following disclaimer. 40 * 2. Redistributions in binary form must reproduce the above copyright 41 * notice, this list of conditions and the following disclaimer in the 42 * documentation and/or other materials provided with the distribution. 43 * 3. All advertising materials mentioning features or use of this software 44 * must display the following acknowledgement: 45 * This product includes software developed for the NetBSD Project by 46 * Wasabi Systems, Inc. 47 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 48 * or promote products derived from this software without specific prior 49 * written permission. 50 * 51 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 52 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 53 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 54 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 55 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 56 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 57 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 58 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 59 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 60 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 61 * POSSIBILITY OF SUCH DAMAGE. 62 */ 63 64 /* 65 * pmap.h: see pmap.c for the history of this pmap module. 66 */ 67 68 #ifndef _MACHINE_PMAP_H_ 69 #define _MACHINE_PMAP_H_ 70 71 #ifndef _LOCORE 72 #ifdef _KERNEL 73 #include <machine/cpufunc.h> 74 #endif /* _KERNEL */ 75 #include <sys/mutex.h> 76 #include <uvm/uvm_object.h> 77 #include <machine/pte.h> 78 #endif 79 80 /* 81 * The x86_64 pmap module closely resembles the i386 one. It uses 82 * the same recursive entry scheme. See the i386 pmap.h for a 83 * description. The alternate area trick for accessing non-current 84 * pmaps has been removed, though, because it performs badly on SMP 85 * systems. 86 * The most obvious difference to i386 is that 2 extra levels of page 87 * table need to be dealt with. The level 1 page table pages are at: 88 * 89 * l1: 0x00007f8000000000 - 0x00007fffffffffff (39 bits, needs PML4 entry) 90 * 91 * The other levels are kept as physical pages in 3 UVM objects and are 92 * temporarily mapped for virtual access when needed. 93 * 94 * The other obvious difference from i386 is that it has a direct map of all 95 * physical memory in the VA range: 96 * 97 * 0xfffffd8000000000 - 0xffffff7fffffffff 98 * 99 * The direct map is used in some cases to access PTEs of non-current pmaps. 100 * 101 * Note that address space is signed, so the layout for 48 bits is: 102 * 103 * +---------------------------------+ 0xffffffffffffffff 104 * | Kernel Image | 105 * +---------------------------------+ 0xffffff8000000000 106 * | Direct Map | 107 * +---------------------------------+ 0xfffffd8000000000 108 * ~ ~ 109 * | | 110 * | Kernel Space | 111 * | | 112 * | | 113 * +---------------------------------+ 0xffff800000000000 = 0x0000800000000000 114 * | L1 table (PTE pages) | 115 * +---------------------------------+ 0x00007f8000000000 116 * ~ ~ 117 * | | 118 * | User Space | 119 * | | 120 * | | 121 * +---------------------------------+ 0x0000000000000000 122 * 123 * In other words, there is a 'VA hole' at 0x0000800000000000 - 124 * 0xffff800000000000 which will trap, just as on, for example, 125 * sparcv9. 126 * 127 * The unused space can be used if needed, but it adds a little more 128 * complexity to the calculations. 129 */ 130 131 /* 132 * Mask to get rid of the sign-extended part of addresses. 133 */ 134 #define VA_SIGN_MASK 0xffff000000000000 135 #define VA_SIGN_NEG(va) ((va) | VA_SIGN_MASK) 136 /* 137 * XXXfvdl this one's not right. 138 */ 139 #define VA_SIGN_POS(va) ((va) & ~VA_SIGN_MASK) 140 141 #define L4_SLOT_PTE 255 142 #define L4_SLOT_KERN 256 143 #define L4_SLOT_KERNBASE 511 144 #define NUM_L4_SLOT_DIRECT 4 145 #define L4_SLOT_DIRECT (L4_SLOT_KERNBASE - NUM_L4_SLOT_DIRECT) 146 #define L4_SLOT_EARLY (L4_SLOT_DIRECT - 1) 147 148 #define PDIR_SLOT_KERN L4_SLOT_KERN 149 #define PDIR_SLOT_PTE L4_SLOT_PTE 150 #define PDIR_SLOT_DIRECT L4_SLOT_DIRECT 151 #define PDIR_SLOT_EARLY L4_SLOT_EARLY 152 153 /* 154 * the following defines give the virtual addresses of various MMU 155 * data structures: 156 * PTE_BASE: the base VA of the linear PTE mappings 157 * PDP_PDE: the VA of the PDE that points back to the PDP 158 * 159 */ 160 161 #define PTE_BASE ((pt_entry_t *) (L4_SLOT_PTE * NBPD_L4)) 162 #define PMAP_DIRECT_BASE (VA_SIGN_NEG((L4_SLOT_DIRECT * NBPD_L4))) 163 #define PMAP_DIRECT_END (VA_SIGN_NEG(((L4_SLOT_DIRECT + \ 164 NUM_L4_SLOT_DIRECT) * NBPD_L4))) 165 166 #define L1_BASE PTE_BASE 167 168 #define L2_BASE ((pd_entry_t *)((char *)L1_BASE + L4_SLOT_PTE * NBPD_L3)) 169 #define L3_BASE ((pd_entry_t *)((char *)L2_BASE + L4_SLOT_PTE * NBPD_L2)) 170 #define L4_BASE ((pd_entry_t *)((char *)L3_BASE + L4_SLOT_PTE * NBPD_L1)) 171 172 #define PDP_PDE (L4_BASE + PDIR_SLOT_PTE) 173 174 #define PDP_BASE L4_BASE 175 176 #define NKL4_MAX_ENTRIES (unsigned long)1 177 #define NKL3_MAX_ENTRIES (unsigned long)(NKL4_MAX_ENTRIES * 512) 178 #define NKL2_MAX_ENTRIES (unsigned long)(NKL3_MAX_ENTRIES * 512) 179 #define NKL1_MAX_ENTRIES (unsigned long)(NKL2_MAX_ENTRIES * 512) 180 181 #define NKL4_KIMG_ENTRIES 1 182 #define NKL3_KIMG_ENTRIES 1 183 #define NKL2_KIMG_ENTRIES 64 184 185 /* number of pages of direct map entries set up by locore0.S */ 186 #define NDML4_ENTRIES 1 187 #define NDML3_ENTRIES 1 188 #define NDML2_ENTRIES 4 /* 4GB */ 189 190 /* 191 * Since kva space is below the kernel in its entirety, we start off 192 * with zero entries on each level. 193 */ 194 #define NKL4_START_ENTRIES 0 195 #define NKL3_START_ENTRIES 0 196 #define NKL2_START_ENTRIES 0 197 #define NKL1_START_ENTRIES 0 /* XXX */ 198 199 #define NTOPLEVEL_PDES (PAGE_SIZE / (sizeof (pd_entry_t))) 200 201 #define NPDPG (PAGE_SIZE / sizeof (pd_entry_t)) 202 203 /* 204 * pl*_pi: index in the ptp page for a pde mapping a VA. 205 * (pl*_i below is the index in the virtual array of all pdes per level) 206 */ 207 #define pl1_pi(VA) (((VA_SIGN_POS(VA)) & L1_MASK) >> L1_SHIFT) 208 #define pl2_pi(VA) (((VA_SIGN_POS(VA)) & L2_MASK) >> L2_SHIFT) 209 #define pl3_pi(VA) (((VA_SIGN_POS(VA)) & L3_MASK) >> L3_SHIFT) 210 #define pl4_pi(VA) (((VA_SIGN_POS(VA)) & L4_MASK) >> L4_SHIFT) 211 212 /* 213 * pl*_i: generate index into pde/pte arrays in virtual space 214 */ 215 #define pl1_i(VA) (((VA_SIGN_POS(VA)) & L1_FRAME) >> L1_SHIFT) 216 #define pl2_i(VA) (((VA_SIGN_POS(VA)) & L2_FRAME) >> L2_SHIFT) 217 #define pl3_i(VA) (((VA_SIGN_POS(VA)) & L3_FRAME) >> L3_SHIFT) 218 #define pl4_i(VA) (((VA_SIGN_POS(VA)) & L4_FRAME) >> L4_SHIFT) 219 #define pl_i(va, lvl) \ 220 (((VA_SIGN_POS(va)) & ptp_masks[(lvl)-1]) >> ptp_shifts[(lvl)-1]) 221 222 #define PTP_MASK_INITIALIZER { L1_FRAME, L2_FRAME, L3_FRAME, L4_FRAME } 223 #define PTP_SHIFT_INITIALIZER { L1_SHIFT, L2_SHIFT, L3_SHIFT, L4_SHIFT } 224 #define NKPTP_INITIALIZER { NKL1_START_ENTRIES, NKL2_START_ENTRIES, \ 225 NKL3_START_ENTRIES, NKL4_START_ENTRIES } 226 #define NKPTPMAX_INITIALIZER { NKL1_MAX_ENTRIES, NKL2_MAX_ENTRIES, \ 227 NKL3_MAX_ENTRIES, NKL4_MAX_ENTRIES } 228 #define NBPD_INITIALIZER { NBPD_L1, NBPD_L2, NBPD_L3, NBPD_L4 } 229 #define PDES_INITIALIZER { L2_BASE, L3_BASE, L4_BASE } 230 231 /* 232 * PTP macros: 233 * a PTP's index is the PD index of the PDE that points to it 234 * a PTP's offset is the byte-offset in the PTE space that this PTP is at 235 * a PTP's VA is the first VA mapped by that PTP 236 */ 237 238 #define ptp_va2o(va, lvl) (pl_i(va, (lvl)+1) * PAGE_SIZE) 239 240 #define PTP_LEVELS 4 241 242 /* 243 * PG_AVAIL usage: we make use of the ignored bits of the PTE 244 */ 245 246 #define PG_W PG_AVAIL1 /* "wired" mapping */ 247 #define PG_PVLIST PG_AVAIL2 /* mapping has entry on pvlist */ 248 /* PG_AVAIL3 not used */ 249 250 /* 251 * PCID assignments. 252 * The shootdown code assumes KERN, PROC, and PROC_INTEL are both 253 * consecutive and in that order. 254 */ 255 #define PCID_KERN 0 /* for pmap_kernel() */ 256 #define PCID_PROC 1 /* non-pmap_kernel(), U+K */ 257 #define PCID_PROC_INTEL 2 /* non-pmap_kernel(), U-K (meltdown) */ 258 #define PCID_TEMP 3 /* temp mapping of another non-pmap_kernel() */ 259 260 extern int pmap_use_pcid; /* non-zero if PCID support is enabled */ 261 262 /* 263 * Number of PTEs per cache line. 8 byte pte, 64-byte cache line 264 * Used to avoid false sharing of cache lines. 265 */ 266 #define NPTECL 8 267 268 269 #if defined(_KERNEL) && !defined(_LOCORE) 270 /* 271 * pmap data structures: see pmap.c for details of locking. 272 */ 273 274 struct pmap; 275 typedef struct pmap *pmap_t; 276 277 /* 278 * we maintain a list of all non-kernel pmaps 279 */ 280 281 LIST_HEAD(pmap_head, pmap); /* struct pmap_head: head of a pmap list */ 282 283 /* 284 * the pmap structure 285 * 286 * note that the pm_obj contains the reference count, 287 * page list, and number of PTPs within the pmap. 288 */ 289 290 #define PMAP_TYPE_NORMAL 1 291 #define PMAP_TYPE_EPT 2 292 #define PMAP_TYPE_RVI 3 293 #define pmap_nested(pm) ((pm)->pm_type != PMAP_TYPE_NORMAL) 294 295 struct pmap { 296 struct mutex pm_mtx; 297 struct uvm_object pm_obj[PTP_LEVELS-1]; /* objects for lvl >= 1) */ 298 LIST_ENTRY(pmap) pm_list; /* list (lck by pm_list lock) */ 299 /* 300 * pm_pdir : VA of page table to be used when executing in 301 * privileged mode 302 * pm_pdirpa : PA of page table to be used when executing in 303 * privileged mode 304 * pm_pdir_intel : VA of special page table to be used when executing 305 * on an Intel CPU in usermode (no kernel mappings) 306 * pm_pdirpa_intel : PA of special page table to be used when executing 307 * on an Intel CPU in usermode (no kernel mappings) 308 */ 309 pd_entry_t *pm_pdir, *pm_pdir_intel; 310 paddr_t pm_pdirpa, pm_pdirpa_intel; 311 312 struct vm_page *pm_ptphint[PTP_LEVELS-1]; 313 /* pointer to a PTP in our pmap */ 314 struct pmap_statistics pm_stats; /* pmap stats (lck by object lock) */ 315 316 int pm_type; /* Type of pmap this is (PMAP_TYPE_x) */ 317 uint64_t eptp; /* cached EPTP (used by vmm) */ 318 }; 319 320 /* 321 * MD flags that we use for pmap_enter (in the pa): 322 */ 323 #define PMAP_PA_MASK ~((paddr_t)PAGE_MASK) /* to remove the flags */ 324 #define PMAP_NOCACHE 0x1 /* set the non-cacheable bit. */ 325 #define PMAP_WC 0x2 /* set page write combining. */ 326 327 /* 328 * We keep mod/ref flags in struct vm_page->pg_flags. 329 */ 330 #define PG_PMAP_MOD PG_PMAP0 331 #define PG_PMAP_REF PG_PMAP1 332 #define PG_PMAP_WC PG_PMAP2 333 334 /* 335 * for each managed physical page we maintain a list of <PMAP,VA>'s 336 * which it is mapped at. 337 */ 338 struct pv_entry { /* locked by its list's pvh_lock */ 339 struct pv_entry *pv_next; /* next entry */ 340 struct pmap *pv_pmap; /* the pmap */ 341 vaddr_t pv_va; /* the virtual address */ 342 struct vm_page *pv_ptp; /* the vm_page of the PTP */ 343 }; 344 345 /* 346 * global kernel variables 347 */ 348 349 extern struct pmap kernel_pmap_store; /* kernel pmap */ 350 351 extern long nkptp[]; 352 353 extern const paddr_t ptp_masks[]; 354 extern const int ptp_shifts[]; 355 extern const long nbpd[], nkptpmax[]; 356 357 /* 358 * macros 359 */ 360 361 #define pmap_kernel() (&kernel_pmap_store) 362 #define pmap_resident_count(pmap) ((pmap)->pm_stats.resident_count) 363 #define pmap_wired_count(pmap) ((pmap)->pm_stats.wired_count) 364 #define pmap_update(pmap) /* nothing (yet) */ 365 366 #define pmap_clear_modify(pg) pmap_clear_attrs(pg, PG_M) 367 #define pmap_clear_reference(pg) pmap_clear_attrs(pg, PG_U) 368 #define pmap_copy(DP,SP,D,L,S) 369 #define pmap_is_modified(pg) pmap_test_attrs(pg, PG_M) 370 #define pmap_is_referenced(pg) pmap_test_attrs(pg, PG_U) 371 #define pmap_move(DP,SP,D,L,S) 372 #define pmap_valid_entry(E) ((E) & PG_V) /* is PDE or PTE valid? */ 373 374 #define pmap_proc_iflush(p,va,len) /* nothing */ 375 #define pmap_unuse_final(p) /* nothing */ 376 #define pmap_remove_holes(vm) do { /* nothing */ } while (0) 377 378 379 /* 380 * prototypes 381 */ 382 383 void map_tramps(void); /* machdep.c */ 384 paddr_t pmap_bootstrap(paddr_t, paddr_t); 385 void pmap_randomize(void); 386 void pmap_randomize_level(pd_entry_t *, int); 387 int pmap_clear_attrs(struct vm_page *, unsigned long); 388 static void pmap_page_protect(struct vm_page *, vm_prot_t); 389 void pmap_page_remove (struct vm_page *); 390 static void pmap_protect(struct pmap *, vaddr_t, 391 vaddr_t, vm_prot_t); 392 void pmap_remove(struct pmap *, vaddr_t, vaddr_t); 393 int pmap_test_attrs(struct vm_page *, unsigned); 394 static void pmap_update_pg(vaddr_t); 395 void pmap_write_protect(struct pmap *, vaddr_t, 396 vaddr_t, vm_prot_t); 397 void pmap_fix_ept(struct pmap *, vaddr_t); 398 399 paddr_t pmap_prealloc_lowmem_ptps(paddr_t); 400 401 void pagezero(vaddr_t); 402 403 int pmap_convert(struct pmap *, int); 404 void pmap_enter_special(vaddr_t, paddr_t, vm_prot_t); 405 vaddr_t pmap_set_pml4_early(paddr_t pa); 406 void pmap_clear_pml4_early(void); 407 408 /* 409 * functions for flushing the cache for vaddrs and pages. 410 * these functions are not part of the MI pmap interface and thus 411 * should not be used as such. 412 */ 413 void pmap_flush_cache(vaddr_t, vsize_t); 414 #define pmap_flush_page(paddr) do { \ 415 KDASSERT(PHYS_TO_VM_PAGE(paddr) != NULL); \ 416 pmap_flush_cache(PMAP_DIRECT_MAP(paddr), PAGE_SIZE); \ 417 } while (/* CONSTCOND */ 0) 418 419 #define PMAP_STEAL_MEMORY /* enable pmap_steal_memory() */ 420 #define PMAP_GROWKERNEL /* turn on pmap_growkernel interface */ 421 422 /* 423 * inline functions 424 */ 425 426 static inline void 427 pmap_remove_all(struct pmap *pmap) 428 { 429 /* Nothing. */ 430 } 431 432 /* 433 * pmap_update_pg: flush one page from the TLB (or flush the whole thing 434 * if hardware doesn't support one-page flushing) 435 */ 436 437 inline static void 438 pmap_update_pg(vaddr_t va) 439 { 440 invlpg(va); 441 } 442 443 /* 444 * pmap_page_protect: change the protection of all recorded mappings 445 * of a managed page 446 * 447 * => this function is a frontend for pmap_page_remove/pmap_clear_attrs 448 * => we only have to worry about making the page more protected. 449 * unprotecting a page is done on-demand at fault time. 450 */ 451 452 inline static void 453 pmap_page_protect(struct vm_page *pg, vm_prot_t prot) 454 { 455 if ((prot & PROT_WRITE) == 0) { 456 if (prot & (PROT_READ | PROT_EXEC)) { 457 (void) pmap_clear_attrs(pg, PG_RW); 458 } else { 459 pmap_page_remove(pg); 460 } 461 } 462 } 463 464 /* 465 * pmap_protect: change the protection of pages in a pmap 466 * 467 * => this function is a frontend for pmap_remove/pmap_write_protect 468 * => we only have to worry about making the page more protected. 469 * unprotecting a page is done on-demand at fault time. 470 */ 471 472 inline static void 473 pmap_protect(struct pmap *pmap, vaddr_t sva, vaddr_t eva, vm_prot_t prot) 474 { 475 if ((prot & PROT_WRITE) == 0) { 476 if (prot & (PROT_READ| PROT_EXEC)) { 477 pmap_write_protect(pmap, sva, eva, prot); 478 } else { 479 pmap_remove(pmap, sva, eva); 480 } 481 } 482 } 483 484 /* 485 * various address inlines 486 * 487 * vtopte: return a pointer to the PTE mapping a VA, works only for 488 * user and PT addresses 489 * 490 * kvtopte: return a pointer to the PTE mapping a kernel VA 491 */ 492 493 static inline pt_entry_t * 494 vtopte(vaddr_t va) 495 { 496 return (PTE_BASE + pl1_i(va)); 497 } 498 499 static inline pt_entry_t * 500 kvtopte(vaddr_t va) 501 { 502 #ifdef LARGEPAGES 503 { 504 pd_entry_t *pde; 505 506 pde = L1_BASE + pl2_i(va); 507 if (*pde & PG_PS) 508 return ((pt_entry_t *)pde); 509 } 510 #endif 511 512 return (PTE_BASE + pl1_i(va)); 513 } 514 515 #define PMAP_DIRECT_MAP(pa) ((vaddr_t)PMAP_DIRECT_BASE + (pa)) 516 #define PMAP_DIRECT_UNMAP(va) ((paddr_t)(va) - PMAP_DIRECT_BASE) 517 #define pmap_map_direct(pg) PMAP_DIRECT_MAP(VM_PAGE_TO_PHYS(pg)) 518 #define pmap_unmap_direct(va) PHYS_TO_VM_PAGE(PMAP_DIRECT_UNMAP(va)) 519 520 #define __HAVE_PMAP_DIRECT 521 522 #endif /* _KERNEL && !_LOCORE */ 523 524 #ifndef _LOCORE 525 struct pv_entry; 526 struct vm_page_md { 527 struct mutex pv_mtx; 528 struct pv_entry *pv_list; 529 }; 530 531 #define VM_MDPAGE_INIT(pg) do { \ 532 mtx_init(&(pg)->mdpage.pv_mtx, IPL_VM); \ 533 (pg)->mdpage.pv_list = NULL; \ 534 } while (0) 535 #endif /* !_LOCORE */ 536 537 #endif /* _MACHINE_PMAP_H_ */ 538