1 /* $OpenBSD: sio_pic.c,v 1.17 2000/11/25 00:39:05 art Exp $ */ 2 /* $NetBSD: sio_pic.c,v 1.28 2000/06/06 03:10:13 thorpej Exp $ */ 3 4 /*- 5 * Copyright (c) 1998, 2000 The NetBSD Foundation, Inc. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to The NetBSD Foundation 9 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 10 * NASA Ames Research Center. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 3. All advertising materials mentioning features or use of this software 21 * must display the following acknowledgement: 22 * This product includes software developed by the NetBSD 23 * Foundation, Inc. and its contributors. 24 * 4. Neither the name of The NetBSD Foundation nor the names of its 25 * contributors may be used to endorse or promote products derived 26 * from this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 29 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 30 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 31 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 32 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 33 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 34 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 35 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 36 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 37 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 38 * POSSIBILITY OF SUCH DAMAGE. 39 */ 40 41 /* 42 * Copyright (c) 1995, 1996 Carnegie-Mellon University. 43 * All rights reserved. 44 * 45 * Author: Chris G. Demetriou 46 * 47 * Permission to use, copy, modify and distribute this software and 48 * its documentation is hereby granted, provided that both the copyright 49 * notice and this permission notice appear in all copies of the 50 * software, derivative works or modified versions, and any portions 51 * thereof, and that both notices appear in supporting documentation. 52 * 53 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 54 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 55 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 56 * 57 * Carnegie Mellon requests users of this software to return to 58 * 59 * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU 60 * School of Computer Science 61 * Carnegie Mellon University 62 * Pittsburgh PA 15213-3890 63 * 64 * any improvements or extensions that they make and grant Carnegie the 65 * rights to redistribute these changes. 66 */ 67 68 #include <sys/param.h> 69 #include <sys/systm.h> 70 #include <sys/device.h> 71 #include <sys/malloc.h> 72 #include <sys/syslog.h> 73 74 #include <machine/intr.h> 75 #include <machine/bus.h> 76 77 #include <dev/pci/pcireg.h> 78 #include <dev/pci/pcivar.h> 79 #include <dev/pci/pcidevs.h> 80 81 #include <dev/pci/cy82c693reg.h> 82 #include <dev/pci/cy82c693var.h> 83 84 #include <dev/isa/isareg.h> 85 #include <dev/isa/isavar.h> 86 #include <alpha/pci/siovar.h> 87 88 #include "sio.h" 89 90 /* 91 * To add to the long history of wonderful PROM console traits, 92 * AlphaStation PROMs don't reset themselves completely on boot! 93 * Therefore, if an interrupt was turned on when the kernel was 94 * started, we're not going to EVER turn it off... I don't know 95 * what will happen if new interrupts (that the PROM console doesn't 96 * want) are turned on. I'll burn that bridge when I come to it. 97 */ 98 #define BROKEN_PROM_CONSOLE 99 100 /* 101 * Private functions and variables. 102 */ 103 104 bus_space_tag_t sio_iot; 105 pci_chipset_tag_t sio_pc; 106 bus_space_handle_t sio_ioh_icu1, sio_ioh_icu2; 107 108 #define ICU_LEN 16 /* number of ISA IRQs */ 109 110 static struct alpha_shared_intr *sio_intr; 111 112 #ifndef STRAY_MAX 113 #define STRAY_MAX 5 114 #endif 115 116 #ifdef BROKEN_PROM_CONSOLE 117 /* 118 * If prom console is broken, must remember the initial interrupt 119 * settings and enforce them. WHEE! 120 */ 121 u_int8_t initial_ocw1[2]; 122 u_int8_t initial_elcr[2]; 123 #endif 124 125 void sio_setirqstat __P((int, int, int)); 126 127 u_int8_t (*sio_read_elcr) __P((int)); 128 void (*sio_write_elcr) __P((int, u_int8_t)); 129 static void specific_eoi __P((int)); 130 #ifdef BROKEN_PROM_CONSOLE 131 void sio_intr_shutdown __P((void *)); 132 #endif 133 134 /******************** i82378 SIO ELCR functions ********************/ 135 136 int i82378_setup_elcr __P((void)); 137 u_int8_t i82378_read_elcr __P((int)); 138 void i82378_write_elcr __P((int, u_int8_t)); 139 140 bus_space_handle_t sio_ioh_elcr; 141 142 int 143 i82378_setup_elcr() 144 { 145 int rv; 146 147 /* 148 * We could probe configuration space to see that there's 149 * actually an SIO present, but we are using this as a 150 * fall-back in case nothing else matches. 151 */ 152 153 rv = bus_space_map(sio_iot, 0x4d0, 2, 0, &sio_ioh_elcr); 154 155 if (rv == 0) { 156 sio_read_elcr = i82378_read_elcr; 157 sio_write_elcr = i82378_write_elcr; 158 } 159 160 return (rv); 161 } 162 163 u_int8_t 164 i82378_read_elcr(elcr) 165 int elcr; 166 { 167 168 return (bus_space_read_1(sio_iot, sio_ioh_elcr, elcr)); 169 } 170 171 void 172 i82378_write_elcr(elcr, val) 173 int elcr; 174 u_int8_t val; 175 { 176 177 bus_space_write_1(sio_iot, sio_ioh_elcr, elcr, val); 178 } 179 180 /******************** Cypress CY82C693 ELCR functions ********************/ 181 182 int cy82c693_setup_elcr __P((void)); 183 u_int8_t cy82c693_read_elcr __P((int)); 184 void cy82c693_write_elcr __P((int, u_int8_t)); 185 186 const struct cy82c693_handle *sio_cy82c693_handle; 187 188 int 189 cy82c693_setup_elcr() 190 { 191 int device, maxndevs; 192 pcitag_t tag; 193 pcireg_t id; 194 195 /* 196 * Search PCI configuration space for a Cypress CY82C693. 197 * 198 * Note we can make some assumptions about our bus number 199 * here, because: 200 * 201 * (1) there can be at most one ISA/EISA bridge per PCI bus, and 202 * 203 * (2) any ISA/EISA bridges must be attached to primary PCI 204 * busses (i.e. bus zero). 205 */ 206 207 maxndevs = pci_bus_maxdevs(sio_pc, 0); 208 209 for (device = 0; device < maxndevs; device++) { 210 tag = pci_make_tag(sio_pc, 0, device, 0); 211 id = pci_conf_read(sio_pc, tag, PCI_ID_REG); 212 213 /* Invalid vendor ID value? */ 214 if (PCI_VENDOR(id) == PCI_VENDOR_INVALID) 215 continue; 216 /* XXX Not invalid, but we've done this ~forever. */ 217 if (PCI_VENDOR(id) == 0) 218 continue; 219 220 if (PCI_VENDOR(id) != PCI_VENDOR_CONTAQ || 221 PCI_PRODUCT(id) != PCI_PRODUCT_CONTAQ_82C693) 222 continue; 223 224 /* 225 * Found one! 226 */ 227 228 #if 0 229 printf("cy82c693_setup_elcr: found 82C693 at device %d\n", 230 device); 231 #endif 232 233 sio_cy82c693_handle = cy82c693_init(sio_iot); 234 sio_read_elcr = cy82c693_read_elcr; 235 sio_write_elcr = cy82c693_write_elcr; 236 237 return (0); 238 } 239 240 /* 241 * Didn't find a CY82C693. 242 */ 243 return (ENODEV); 244 } 245 246 u_int8_t 247 cy82c693_read_elcr(elcr) 248 int elcr; 249 { 250 251 return (cy82c693_read(sio_cy82c693_handle, CONFIG_ELCR1 + elcr)); 252 } 253 254 void 255 cy82c693_write_elcr(elcr, val) 256 int elcr; 257 u_int8_t val; 258 { 259 260 cy82c693_write(sio_cy82c693_handle, CONFIG_ELCR1 + elcr, val); 261 } 262 263 /******************** ELCR access function configuration ********************/ 264 265 /* 266 * Put the Intel SIO at the end, so we fall back on it if we don't 267 * find anything else. If any of the non-Intel functions find a 268 * matching device, but are unable to map it for whatever reason, 269 * they should panic. 270 */ 271 272 int (*sio_elcr_setup_funcs[]) __P((void)) = { 273 cy82c693_setup_elcr, 274 i82378_setup_elcr, 275 NULL, 276 }; 277 278 /******************** Shared SIO/Cypress functions ********************/ 279 280 void 281 sio_setirqstat(irq, enabled, type) 282 int irq, enabled; 283 int type; 284 { 285 u_int8_t ocw1[2], elcr[2]; 286 int icu, bit; 287 288 #if 0 289 printf("sio_setirqstat: irq %d: %s, %s\n", irq, 290 enabled ? "enabled" : "disabled", isa_intr_typename(type)); 291 #endif 292 293 icu = irq / 8; 294 bit = irq % 8; 295 296 ocw1[0] = bus_space_read_1(sio_iot, sio_ioh_icu1, 1); 297 ocw1[1] = bus_space_read_1(sio_iot, sio_ioh_icu2, 1); 298 elcr[0] = (*sio_read_elcr)(0); /* XXX */ 299 elcr[1] = (*sio_read_elcr)(1); /* XXX */ 300 301 /* 302 * interrupt enable: set bit to mask (disable) interrupt. 303 */ 304 if (enabled) 305 ocw1[icu] &= ~(1 << bit); 306 else 307 ocw1[icu] |= 1 << bit; 308 309 /* 310 * interrupt type select: set bit to get level-triggered. 311 */ 312 if (type == IST_LEVEL) 313 elcr[icu] |= 1 << bit; 314 else 315 elcr[icu] &= ~(1 << bit); 316 317 #ifdef not_here 318 /* see the init function... */ 319 ocw1[0] &= ~0x04; /* always enable IRQ2 on first PIC */ 320 elcr[0] &= ~0x07; /* IRQ[0-2] must be edge-triggered */ 321 elcr[1] &= ~0x21; /* IRQ[13,8] must be edge-triggered */ 322 #endif 323 324 bus_space_write_1(sio_iot, sio_ioh_icu1, 1, ocw1[0]); 325 bus_space_write_1(sio_iot, sio_ioh_icu2, 1, ocw1[1]); 326 (*sio_write_elcr)(0, elcr[0]); /* XXX */ 327 (*sio_write_elcr)(1, elcr[1]); /* XXX */ 328 } 329 330 void 331 sio_intr_setup(pc, iot) 332 pci_chipset_tag_t pc; 333 bus_space_tag_t iot; 334 { 335 #ifdef notyet 336 char *cp; 337 #endif 338 int i; 339 340 sio_iot = iot; 341 sio_pc = pc; 342 343 if (bus_space_map(sio_iot, IO_ICU1, 2, 0, &sio_ioh_icu1) || 344 bus_space_map(sio_iot, IO_ICU2, 2, 0, &sio_ioh_icu2)) 345 panic("sio_intr_setup: can't map ICU I/O ports"); 346 347 for (i = 0; sio_elcr_setup_funcs[i] != NULL; i++) 348 if ((*sio_elcr_setup_funcs[i])() == 0) 349 break; 350 if (sio_elcr_setup_funcs[i] == NULL) 351 panic("sio_intr_setup: can't map ELCR"); 352 353 #ifdef BROKEN_PROM_CONSOLE 354 /* 355 * Remember the initial values, so we can restore them later. 356 */ 357 initial_ocw1[0] = bus_space_read_1(sio_iot, sio_ioh_icu1, 1); 358 initial_ocw1[1] = bus_space_read_1(sio_iot, sio_ioh_icu2, 1); 359 initial_elcr[0] = (*sio_read_elcr)(0); /* XXX */ 360 initial_elcr[1] = (*sio_read_elcr)(1); /* XXX */ 361 shutdownhook_establish(sio_intr_shutdown, 0); 362 #endif 363 364 sio_intr = alpha_shared_intr_alloc(ICU_LEN); 365 366 /* 367 * set up initial values for interrupt enables. 368 */ 369 for (i = 0; i < ICU_LEN; i++) { 370 alpha_shared_intr_set_maxstrays(sio_intr, i, STRAY_MAX); 371 372 #ifdef notyet 373 cp = alpha_shared_intr_string(sio_intr, i); 374 sprintf(cp, "irq %d", i); 375 evcnt_attach_dynamic(alpha_shared_intr_evcnt(sio_intr, i), 376 EVCNT_TYPE_INTR, NULL, "isa", cp); 377 #endif 378 379 switch (i) { 380 case 0: 381 case 1: 382 case 8: 383 case 13: 384 /* 385 * IRQs 0, 1, 8, and 13 must always be 386 * edge-triggered. 387 */ 388 sio_setirqstat(i, 0, IST_EDGE); 389 alpha_shared_intr_set_dfltsharetype(sio_intr, i, 390 IST_EDGE); 391 specific_eoi(i); 392 break; 393 394 case 2: 395 /* 396 * IRQ 2 must be edge-triggered, and should be 397 * enabled (otherwise IRQs 8-15 are ignored). 398 */ 399 sio_setirqstat(i, 1, IST_EDGE); 400 alpha_shared_intr_set_dfltsharetype(sio_intr, i, 401 IST_UNUSABLE); 402 break; 403 404 default: 405 /* 406 * Otherwise, disable the IRQ and set its 407 * type to (effectively) "unknown." 408 */ 409 sio_setirqstat(i, 0, IST_NONE); 410 alpha_shared_intr_set_dfltsharetype(sio_intr, i, 411 IST_NONE); 412 specific_eoi(i); 413 break; 414 } 415 } 416 } 417 418 #ifdef BROKEN_PROM_CONSOLE 419 void 420 sio_intr_shutdown(arg) 421 void *arg; 422 { 423 /* 424 * Restore the initial values, to make the PROM happy. 425 */ 426 bus_space_write_1(sio_iot, sio_ioh_icu1, 1, initial_ocw1[0]); 427 bus_space_write_1(sio_iot, sio_ioh_icu2, 1, initial_ocw1[1]); 428 (*sio_write_elcr)(0, initial_elcr[0]); /* XXX */ 429 (*sio_write_elcr)(1, initial_elcr[1]); /* XXX */ 430 } 431 #endif 432 433 const char * 434 sio_intr_string(v, irq) 435 void *v; 436 int irq; 437 { 438 static char irqstr[12]; /* 8 + 2 + NULL + sanity */ 439 440 if (irq == 0 || irq >= ICU_LEN || irq == 2) 441 panic("sio_intr_string: bogus isa irq 0x%x\n", irq); 442 443 sprintf(irqstr, "isa irq %d", irq); 444 return (irqstr); 445 } 446 447 #ifdef notyet 448 const struct evcnt * 449 sio_intr_evcnt(v, irq) 450 void *v; 451 int irq; 452 { 453 454 if (irq == 0 || irq >= ICU_LEN || irq == 2) 455 panic("sio_intr_evcnt: bogus isa irq 0x%x\n", irq); 456 457 return (alpha_shared_intr_evcnt(sio_intr, irq)); 458 } 459 #endif 460 461 void * 462 sio_intr_establish(v, irq, type, level, fn, arg, name) 463 void *v, *arg; 464 int irq; 465 int type; 466 int level; 467 int (*fn)(void *); 468 char *name; 469 { 470 void *cookie; 471 472 if (irq > ICU_LEN || type == IST_NONE) 473 panic("sio_intr_establish: bogus irq or type"); 474 475 cookie = alpha_shared_intr_establish(sio_intr, irq, type, level, fn, 476 arg, name); 477 478 if (cookie) 479 sio_setirqstat(irq, alpha_shared_intr_isactive(sio_intr, irq), 480 alpha_shared_intr_get_sharetype(sio_intr, irq)); 481 482 return (cookie); 483 } 484 485 void 486 sio_intr_disestablish(v, cookie) 487 void *v; 488 void *cookie; 489 { 490 struct alpha_shared_intrhand *ih = cookie; 491 int s, ist, irq = ih->ih_num; 492 493 s = splhigh(); 494 495 /* Remove it from the link. */ 496 alpha_shared_intr_disestablish(sio_intr, cookie, "isa irq"); 497 498 /* 499 * Decide if we should disable the interrupt. We must ensure 500 * that: 501 * 502 * - An initially-enabled interrupt is never disabled. 503 * - An initially-LT interrupt is never untyped. 504 */ 505 if (alpha_shared_intr_isactive(sio_intr, irq) == 0) { 506 /* 507 * IRQs 0, 1, 8, and 13 must always be edge-triggered 508 * (see setup). 509 */ 510 switch (irq) { 511 case 0: 512 case 1: 513 case 8: 514 case 13: 515 /* 516 * If the interrupt was initially level-triggered 517 * a warning was printed in setup. 518 */ 519 ist = IST_EDGE; 520 break; 521 522 default: 523 ist = IST_NONE; 524 break; 525 } 526 sio_setirqstat(irq, 0, ist); 527 alpha_shared_intr_set_dfltsharetype(sio_intr, irq, ist); 528 } 529 530 splx(s); 531 } 532 533 void 534 sio_iointr(framep, vec) 535 void *framep; 536 unsigned long vec; 537 { 538 int irq; 539 540 irq = (vec - 0x800) >> 4; 541 #ifdef DIAGNOSTIC 542 if (irq > ICU_LEN || irq < 0) 543 panic("sio_iointr: irq out of range (%d)", irq); 544 #endif 545 546 if (!alpha_shared_intr_dispatch(sio_intr, irq)) 547 alpha_shared_intr_stray(sio_intr, irq, "isa irq"); 548 549 /* 550 * Some versions of the machines which use the SIO 551 * (or is it some PALcode revisions on those machines?) 552 * require the non-specific EOI to be fed to the PIC(s) 553 * by the interrupt handler. 554 */ 555 specific_eoi(irq); 556 } 557 558 #define LEGAL_IRQ(x) ((x) >= 0 && (x) < ICU_LEN && (x) != 2) 559 560 #ifdef notyet 561 int 562 sio_intr_alloc(v, mask, type, irq) 563 void *v; 564 int mask; 565 int type; 566 int *irq; 567 { 568 int i, tmp, bestirq, count; 569 struct alpha_shared_intrhand **p, *q; 570 571 if (type == IST_NONE) 572 panic("intr_alloc: bogus type"); 573 574 bestirq = -1; 575 count = -1; 576 577 /* some interrupts should never be dynamically allocated */ 578 mask &= 0xdef8; 579 580 /* 581 * XXX some interrupts will be used later (6 for fdc, 12 for pms). 582 * the right answer is to do "breadth-first" searching of devices. 583 */ 584 mask &= 0xefbf; 585 586 for (i = 0; i < ICU_LEN; i++) { 587 if (LEGAL_IRQ(i) == 0 || (mask & (1<<i)) == 0) 588 continue; 589 590 switch(sio_intr[i].intr_sharetype) { 591 case IST_NONE: 592 /* 593 * if nothing's using the irq, just return it 594 */ 595 *irq = i; 596 return (0); 597 598 case IST_EDGE: 599 case IST_LEVEL: 600 if (type != sio_intr[i].intr_sharetype) 601 continue; 602 /* 603 * if the irq is shareable, count the number of other 604 * handlers, and if it's smaller than the last irq like 605 * this, remember it 606 * 607 * XXX We should probably also consider the 608 * interrupt level and stick IPL_TTY with other 609 * IPL_TTY, etc. 610 */ 611 for (p = &TAILQ_FIRST(&sio_intr[i].intr_q), tmp = 0; 612 (q = *p) != NULL; p = &TAILQ_NEXT(q, ih_q), tmp++) 613 ; 614 if ((bestirq == -1) || (count > tmp)) { 615 bestirq = i; 616 count = tmp; 617 } 618 break; 619 620 case IST_PULSE: 621 /* this just isn't shareable */ 622 continue; 623 } 624 } 625 626 if (bestirq == -1) 627 return (1); 628 629 *irq = bestirq; 630 631 return (0); 632 } 633 #endif 634 635 static void 636 specific_eoi(irq) 637 int irq; 638 { 639 if (irq > 7) 640 bus_space_write_1(sio_iot, 641 sio_ioh_icu2, 0, 0x20 | (irq & 0x07)); /* XXX */ 642 bus_space_write_1(sio_iot, sio_ioh_icu1, 0, 0x20 | (irq > 7 ? 2 : irq)); 643 } 644