xref: /openbsd-src/sys/arch/alpha/pci/pci_eb64plus.c (revision f2da64fbbbf1b03f09f390ab01267c93dfd77c4c)
1 /* $OpenBSD: pci_eb64plus.c,v 1.15 2015/07/26 05:09:44 miod Exp $ */
2 /* $NetBSD: pci_eb64plus.c,v 1.10 2001/07/27 00:25:20 thorpej Exp $ */
3 
4 /*-
5  * Copyright (c) 1998 The NetBSD Foundation, Inc.
6  * All rights reserved.
7  *
8  * This code is derived from software contributed to The NetBSD Foundation
9  * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
10  * NASA Ames Research Center.
11  *
12  * Redistribution and use in source and binary forms, with or without
13  * modification, are permitted provided that the following conditions
14  * are met:
15  * 1. Redistributions of source code must retain the above copyright
16  *    notice, this list of conditions and the following disclaimer.
17  * 2. Redistributions in binary form must reproduce the above copyright
18  *    notice, this list of conditions and the following disclaimer in the
19  *    documentation and/or other materials provided with the distribution.
20  *
21  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
22  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
23  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
24  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
25  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31  * POSSIBILITY OF SUCH DAMAGE.
32  */
33 
34 /*
35  * Copyright (c) 1995, 1996 Carnegie-Mellon University.
36  * All rights reserved.
37  *
38  * Author: Chris G. Demetriou
39  *
40  * Permission to use, copy, modify and distribute this software and
41  * its documentation is hereby granted, provided that both the copyright
42  * notice and this permission notice appear in all copies of the
43  * software, derivative works or modified versions, and any portions
44  * thereof, and that both notices appear in supporting documentation.
45  *
46  * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
47  * CONDITION.  CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
48  * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
49  *
50  * Carnegie Mellon requests users of this software to return to
51  *
52  *  Software Distribution Coordinator  or  Software.Distribution@CS.CMU.EDU
53  *  School of Computer Science
54  *  Carnegie Mellon University
55  *  Pittsburgh PA 15213-3890
56  *
57  * any improvements or extensions that they make and grant Carnegie the
58  * rights to redistribute these changes.
59  */
60 
61 #include <sys/types.h>
62 #include <sys/param.h>
63 #include <sys/time.h>
64 #include <sys/systm.h>
65 #include <sys/errno.h>
66 #include <sys/malloc.h>
67 #include <sys/device.h>
68 #include <sys/syslog.h>
69 
70 #include <uvm/uvm_extern.h>
71 
72 #include <machine/autoconf.h>
73 
74 #include <dev/pci/pcireg.h>
75 #include <dev/pci/pcivar.h>
76 #include <dev/pci/ppbreg.h>
77 
78 #include <alpha/pci/apecsreg.h>
79 #include <alpha/pci/apecsvar.h>
80 
81 #include <alpha/pci/pci_eb64plus.h>
82 
83 #include "sio.h"
84 #if NSIO
85 #include <alpha/pci/siovar.h>
86 #endif
87 
88 int	dec_eb64plus_intr_map(struct pci_attach_args *, pci_intr_handle_t *);
89 const char *dec_eb64plus_intr_string(void *, pci_intr_handle_t);
90 void	*dec_eb64plus_intr_establish(void *, pci_intr_handle_t,
91 	    int, int (*func)(void *), void *, const char *);
92 void	dec_eb64plus_intr_disestablish(void *, void *);
93 
94 #define	EB64PLUS_MAX_IRQ	32
95 #define	PCI_STRAY_MAX		5
96 
97 struct alpha_shared_intr *eb64plus_pci_intr;
98 
99 bus_space_tag_t eb64plus_intrgate_iot;
100 bus_space_handle_t eb64plus_intrgate_ioh;
101 
102 void	eb64plus_iointr(void *arg, unsigned long vec);
103 extern void	eb64plus_intr_enable(int irq);  /* pci_eb64plus_intr.S */
104 extern void	eb64plus_intr_disable(int irq); /* pci_eb64plus_intr.S */
105 
106 void
107 pci_eb64plus_pickintr(acp)
108 	struct apecs_config *acp;
109 {
110 	bus_space_tag_t iot = &acp->ac_iot;
111 	pci_chipset_tag_t pc = &acp->ac_pc;
112 	int i;
113 
114         pc->pc_intr_v = acp;
115         pc->pc_intr_map = dec_eb64plus_intr_map;
116         pc->pc_intr_string = dec_eb64plus_intr_string;
117         pc->pc_intr_establish = dec_eb64plus_intr_establish;
118         pc->pc_intr_disestablish = dec_eb64plus_intr_disestablish;
119 
120 	/* Not supported on the EB64+. */
121 	pc->pc_pciide_compat_intr_establish = NULL;
122 
123 	eb64plus_intrgate_iot = iot;
124 	if (bus_space_map(eb64plus_intrgate_iot, 0x804, 3, 0,
125 	    &eb64plus_intrgate_ioh) != 0)
126 		panic("pci_eb64plus_pickintr: couldn't map interrupt PLD");
127 	for (i = 0; i < EB64PLUS_MAX_IRQ; i++)
128 		eb64plus_intr_disable(i);
129 
130 	eb64plus_pci_intr = alpha_shared_intr_alloc(EB64PLUS_MAX_IRQ);
131 	for (i = 0; i < EB64PLUS_MAX_IRQ; i++) {
132 		alpha_shared_intr_set_maxstrays(eb64plus_pci_intr, i,
133 			PCI_STRAY_MAX);
134 	}
135 
136 #if NSIO > 0
137 	sio_intr_setup(pc, iot);
138 #endif
139 }
140 
141 int
142 dec_eb64plus_intr_map(pa, ihp)
143 	struct pci_attach_args *pa;
144         pci_intr_handle_t *ihp;
145 {
146 	int buspin, line = pa->pa_intrline;
147 
148 	/*
149 	 * The console places the interrupt mapping in the "line" value.
150 	 * We trust it whenever possible.
151 	 */
152 	if (line >= 0 && line < EB64PLUS_MAX_IRQ) {
153 		*ihp = line;
154 		return 0;
155 	}
156 
157 	if (pa->pa_bridgetag) {
158 		buspin = PPB_INTERRUPT_SWIZZLE(pa->pa_rawintrpin,
159 		    pa->pa_device);
160 		if (pa->pa_bridgeih[buspin - 1] != 0) {
161 			*ihp = pa->pa_bridgeih[buspin - 1];
162 			return 0;
163 		}
164 	}
165 
166 	return 1;
167 }
168 
169 const char *
170 dec_eb64plus_intr_string(acv, ih)
171 	void *acv;
172 	pci_intr_handle_t ih;
173 {
174         static char irqstr[15];          /* 11 + 2 + NULL + sanity */
175 
176         if (ih >= EB64PLUS_MAX_IRQ)
177                 panic("dec_eb64plus_intr_string: bogus eb64+ IRQ 0x%lx", ih);
178         snprintf(irqstr, sizeof irqstr, "eb64+ irq %ld", ih);
179         return (irqstr);
180 }
181 
182 void *
183 dec_eb64plus_intr_establish(acv, ih, level, func, arg, name)
184         void *acv;
185         pci_intr_handle_t ih;
186         int level;
187         int (*func)(void *);
188 	void *arg;
189 	const char *name;
190 {
191 	void *cookie;
192 
193 	if (ih >= EB64PLUS_MAX_IRQ)
194 		panic("dec_eb64plus_intr_establish: bogus eb64+ IRQ 0x%lx",
195 		    ih);
196 
197 	cookie = alpha_shared_intr_establish(eb64plus_pci_intr, ih, IST_LEVEL,
198 	    level, func, arg, name);
199 
200 	if (cookie != NULL &&
201 	    alpha_shared_intr_firstactive(eb64plus_pci_intr, ih)) {
202 		scb_set(0x900 + SCB_IDXTOVEC(ih), eb64plus_iointr, NULL);
203 		eb64plus_intr_enable(ih);
204 	}
205 	return (cookie);
206 }
207 
208 void
209 dec_eb64plus_intr_disestablish(acv, cookie)
210         void *acv, *cookie;
211 {
212 	struct alpha_shared_intrhand *ih = cookie;
213 	unsigned int irq = ih->ih_num;
214 	int s;
215 
216 	s = splhigh();
217 
218 	alpha_shared_intr_disestablish(eb64plus_pci_intr, cookie);
219 	if (alpha_shared_intr_isactive(eb64plus_pci_intr, irq) == 0) {
220 		eb64plus_intr_disable(irq);
221 		alpha_shared_intr_set_dfltsharetype(eb64plus_pci_intr, irq,
222 		    IST_NONE);
223 		scb_free(0x900 + SCB_IDXTOVEC(irq));
224 	}
225 
226 	splx(s);
227 }
228 
229 void
230 eb64plus_iointr(arg, vec)
231 	void *arg;
232 	unsigned long vec;
233 {
234 	int irq;
235 
236 	irq = SCB_VECTOIDX(vec - 0x900);
237 
238 	if (!alpha_shared_intr_dispatch(eb64plus_pci_intr, irq)) {
239 		alpha_shared_intr_stray(eb64plus_pci_intr, irq,
240 		    "eb64+ irq");
241 		if (ALPHA_SHARED_INTR_DISABLE(eb64plus_pci_intr, irq))
242 			eb64plus_intr_disable(irq);
243 	} else
244 		alpha_shared_intr_reset_strays(eb64plus_pci_intr, irq);
245 }
246 
247 #if 0		/* THIS DOES NOT WORK!  see pci_eb64plus_intr.S. */
248 u_int8_t eb64plus_intr_mask[3] = { 0xff, 0xff, 0xff };
249 
250 void
251 eb64plus_intr_enable(irq)
252 	int irq;
253 {
254 	int byte = (irq / 8), bit = (irq % 8);
255 
256 #if 1
257 	printf("eb64plus_intr_enable: enabling %d (%d:%d)\n", irq, byte, bit);
258 #endif
259 	eb64plus_intr_mask[byte] &= ~(1 << bit);
260 
261 	bus_space_write_1(eb64plus_intrgate_iot, eb64plus_intrgate_ioh, byte,
262 	    eb64plus_intr_mask[byte]);
263 }
264 
265 void
266 eb64plus_intr_disable(irq)
267 	int irq;
268 {
269 	int byte = (irq / 8), bit = (irq % 8);
270 
271 #if 1
272 	printf("eb64plus_intr_disable: disabling %d (%d:%d)\n", irq, byte, bit);
273 #endif
274 	eb64plus_intr_mask[byte] |= (1 << bit);
275 
276 	bus_space_write_1(eb64plus_intrgate_iot, eb64plus_intrgate_ioh, byte,
277 	    eb64plus_intr_mask[byte]);
278 }
279 #endif
280