1 /* $OpenBSD: pci_eb164.c,v 1.27 2015/07/26 05:09:44 miod Exp $ */ 2 /* $NetBSD: pci_eb164.c,v 1.27 2000/06/06 00:50:15 thorpej Exp $ */ 3 4 /*- 5 * Copyright (c) 1998 The NetBSD Foundation, Inc. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to The NetBSD Foundation 9 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 10 * NASA Ames Research Center. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * Copyright (c) 1995, 1996 Carnegie-Mellon University. 36 * All rights reserved. 37 * 38 * Author: Chris G. Demetriou 39 * 40 * Permission to use, copy, modify and distribute this software and 41 * its documentation is hereby granted, provided that both the copyright 42 * notice and this permission notice appear in all copies of the 43 * software, derivative works or modified versions, and any portions 44 * thereof, and that both notices appear in supporting documentation. 45 * 46 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 47 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 48 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 49 * 50 * Carnegie Mellon requests users of this software to return to 51 * 52 * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU 53 * School of Computer Science 54 * Carnegie Mellon University 55 * Pittsburgh PA 15213-3890 56 * 57 * any improvements or extensions that they make and grant Carnegie the 58 * rights to redistribute these changes. 59 */ 60 61 #include <sys/types.h> 62 #include <sys/param.h> 63 #include <sys/time.h> 64 #include <sys/systm.h> 65 #include <sys/errno.h> 66 #include <sys/malloc.h> 67 #include <sys/device.h> 68 #include <sys/syslog.h> 69 70 #include <machine/autoconf.h> 71 #include <machine/rpb.h> 72 73 #include <dev/pci/pcireg.h> 74 #include <dev/pci/pcivar.h> 75 #include <dev/pci/ppbreg.h> 76 #include <dev/pci/pciidereg.h> 77 #include <dev/pci/pciidevar.h> 78 79 #include <alpha/pci/ciareg.h> 80 #include <alpha/pci/ciavar.h> 81 82 #include <alpha/pci/pci_eb164.h> 83 84 #include "sio.h" 85 #if NSIO 86 #include <alpha/pci/siovar.h> 87 #endif 88 89 int dec_eb164_intr_map(struct pci_attach_args *, pci_intr_handle_t *); 90 const char *dec_eb164_intr_string(void *, pci_intr_handle_t); 91 int dec_eb164_intr_line(void *, pci_intr_handle_t); 92 void *dec_eb164_intr_establish(void *, pci_intr_handle_t, 93 int, int (*func)(void *), void *, const char *); 94 void dec_eb164_intr_disestablish(void *, void *); 95 96 void *dec_eb164_pciide_compat_intr_establish(void *, struct device *, 97 struct pci_attach_args *, int, int (*)(void *), void *); 98 void dec_eb164_pciide_compat_intr_disestablish(void *, void *); 99 100 #define EB164_SIO_IRQ 4 101 #define EB164_MAX_IRQ 24 102 #define PCI_STRAY_MAX 5 103 104 struct alpha_shared_intr *eb164_pci_intr; 105 106 bus_space_tag_t eb164_intrgate_iot; 107 bus_space_handle_t eb164_intrgate_ioh; 108 109 void eb164_iointr(void *arg, unsigned long vec); 110 extern void eb164_intr_enable(int irq); /* pci_eb164_intr.S */ 111 extern void eb164_intr_disable(int irq); /* pci_eb164_intr.S */ 112 113 void 114 pci_eb164_pickintr(ccp) 115 struct cia_config *ccp; 116 { 117 bus_space_tag_t iot = &ccp->cc_iot; 118 pci_chipset_tag_t pc = &ccp->cc_pc; 119 int i; 120 121 pc->pc_intr_v = ccp; 122 pc->pc_intr_map = dec_eb164_intr_map; 123 pc->pc_intr_string = dec_eb164_intr_string; 124 pc->pc_intr_line = dec_eb164_intr_line; 125 pc->pc_intr_establish = dec_eb164_intr_establish; 126 pc->pc_intr_disestablish = dec_eb164_intr_disestablish; 127 128 pc->pc_pciide_compat_intr_establish = 129 dec_eb164_pciide_compat_intr_establish; 130 pc->pc_pciide_compat_intr_disestablish = 131 dec_eb164_pciide_compat_intr_disestablish; 132 133 eb164_intrgate_iot = iot; 134 if (bus_space_map(eb164_intrgate_iot, 0x804, 3, 0, 135 &eb164_intrgate_ioh) != 0) 136 panic("pci_eb164_pickintr: couldn't map interrupt PLD"); 137 for (i = 0; i < EB164_MAX_IRQ; i++) 138 eb164_intr_disable(i); 139 140 eb164_pci_intr = alpha_shared_intr_alloc(EB164_MAX_IRQ); 141 for (i = 0; i < EB164_MAX_IRQ; i++) { 142 /* 143 * Systems with a Pyxis seem to have problems with 144 * stray interrupts, so just ignore them. Sigh, 145 * I hate buggy hardware. 146 */ 147 alpha_shared_intr_set_maxstrays(eb164_pci_intr, i, 148 (ccp->cc_flags & CCF_ISPYXIS) ? 0 : PCI_STRAY_MAX); 149 } 150 151 #if NSIO 152 sio_intr_setup(pc, iot); 153 eb164_intr_enable(EB164_SIO_IRQ); 154 #endif 155 } 156 157 int 158 dec_eb164_intr_map(pa, ihp) 159 struct pci_attach_args *pa; 160 pci_intr_handle_t *ihp; 161 { 162 int buspin, line = pa->pa_intrline; 163 u_int64_t variation; 164 165 /* 166 * 167 * The AlphaPC 164 and AlphaPC 164LX have a CMD PCI IDE controller 168 * at bus 0 device 11. These are wired to compatibility mode, 169 * so do not map their interrupts. 170 * 171 * The AlphaPC 164SX has PCI IDE on functions 1 and 2 of the 172 * Cypress PCI-ISA bridge at bus 0 device 8. These, too, are 173 * wired to compatibility mode. 174 * 175 * Real EB164s have ISA IDE on the Super I/O chip. 176 */ 177 variation = hwrpb->rpb_variation & SV_ST_MASK; 178 if (pa->pa_bus == 0) { 179 if (variation >= SV_ST_ALPHAPC164_366 && 180 variation <= SV_ST_ALPHAPC164LX_600) { 181 if (pa->pa_device == 8) 182 panic("dec_eb164_intr_map: SIO device"); 183 if (pa->pa_device == 11) 184 return (1); 185 } else if (variation >= SV_ST_ALPHAPC164SX_400 && 186 variation <= SV_ST_ALPHAPC164SX_600) { 187 if (pa->pa_device == 8) { 188 if (pa->pa_function == 0) 189 panic("dec_eb164_intr_map: SIO device"); 190 return (1); 191 } 192 } else { 193 if (pa->pa_device == 8) 194 panic("dec_eb164_intr_map: SIO device"); 195 } 196 } 197 198 /* 199 * The console places the interrupt mapping in the "line" value. 200 * We trust it whenever possible. 201 */ 202 if (line >= 0 && line < EB164_MAX_IRQ) { 203 *ihp = line; 204 return 0; 205 } 206 207 if (pa->pa_bridgetag) { 208 buspin = PPB_INTERRUPT_SWIZZLE(pa->pa_rawintrpin, 209 pa->pa_device); 210 if (pa->pa_bridgeih[buspin - 1] != 0) { 211 *ihp = pa->pa_bridgeih[buspin - 1]; 212 return 0; 213 } 214 } 215 216 return 1; 217 } 218 219 const char * 220 dec_eb164_intr_string(ccv, ih) 221 void *ccv; 222 pci_intr_handle_t ih; 223 { 224 #if 0 225 struct cia_config *ccp = ccv; 226 #endif 227 static char irqstr[15]; /* 11 + 2 + NULL + sanity */ 228 229 if (ih >= EB164_MAX_IRQ) 230 panic("dec_eb164_intr_string: bogus eb164 IRQ 0x%lx", ih); 231 snprintf(irqstr, sizeof irqstr, "eb164 irq %ld", ih); 232 return (irqstr); 233 } 234 235 int 236 dec_eb164_intr_line(ccv, ih) 237 void *ccv; 238 pci_intr_handle_t ih; 239 { 240 return (ih); 241 } 242 243 void * 244 dec_eb164_intr_establish(ccv, ih, level, func, arg, name) 245 void *ccv, *arg; 246 pci_intr_handle_t ih; 247 int level; 248 int (*func)(void *); 249 const char *name; 250 { 251 #if 0 252 struct cia_config *ccp = ccv; 253 #endif 254 void *cookie; 255 256 if (ih >= EB164_MAX_IRQ) 257 panic("dec_eb164_intr_establish: bogus eb164 IRQ 0x%lx", ih); 258 259 cookie = alpha_shared_intr_establish(eb164_pci_intr, ih, IST_LEVEL, 260 level, func, arg, name); 261 262 if (cookie != NULL && 263 alpha_shared_intr_firstactive(eb164_pci_intr, ih)) { 264 scb_set(0x900 + SCB_IDXTOVEC(ih), eb164_iointr, NULL); 265 eb164_intr_enable(ih); 266 } 267 return (cookie); 268 } 269 270 void 271 dec_eb164_intr_disestablish(ccv, cookie) 272 void *ccv, *cookie; 273 { 274 #if 0 275 struct cia_config *ccp = ccv; 276 #endif 277 struct alpha_shared_intrhand *ih = cookie; 278 unsigned int irq = ih->ih_num; 279 int s; 280 281 s = splhigh(); 282 283 alpha_shared_intr_disestablish(eb164_pci_intr, cookie); 284 if (alpha_shared_intr_isactive(eb164_pci_intr, irq) == 0) { 285 eb164_intr_disable(irq); 286 alpha_shared_intr_set_dfltsharetype(eb164_pci_intr, irq, 287 IST_NONE); 288 scb_free(0x900 + SCB_IDXTOVEC(irq)); 289 } 290 291 splx(s); 292 } 293 294 void * 295 dec_eb164_pciide_compat_intr_establish(v, dev, pa, chan, func, arg) 296 void *v; 297 struct device *dev; 298 struct pci_attach_args *pa; 299 int chan; 300 int (*func)(void *); 301 void *arg; 302 { 303 pci_chipset_tag_t pc = pa->pa_pc; 304 void *cookie = NULL; 305 int bus, irq; 306 307 pci_decompose_tag(pc, pa->pa_tag, &bus, NULL, NULL); 308 309 /* 310 * If this isn't PCI bus #0, all bets are off. 311 */ 312 if (bus != 0) 313 return (NULL); 314 315 irq = PCIIDE_COMPAT_IRQ(chan); 316 #if NSIO 317 cookie = sio_intr_establish(NULL /*XXX*/, irq, IST_EDGE, IPL_BIO, 318 func, arg, dev->dv_xname); 319 if (cookie == NULL) 320 return (NULL); 321 #endif 322 return (cookie); 323 } 324 325 void 326 dec_eb164_pciide_compat_intr_disestablish(void *v, void *cookie) 327 { 328 sio_intr_disestablish(NULL, cookie); 329 } 330 331 void 332 eb164_iointr(arg, vec) 333 void *arg; 334 unsigned long vec; 335 { 336 int irq; 337 338 irq = SCB_VECTOIDX(vec - 0x900); 339 340 if (!alpha_shared_intr_dispatch(eb164_pci_intr, irq)) { 341 alpha_shared_intr_stray(eb164_pci_intr, irq, 342 "eb164 irq"); 343 if (ALPHA_SHARED_INTR_DISABLE(eb164_pci_intr, irq)) 344 eb164_intr_disable(irq); 345 } else 346 alpha_shared_intr_reset_strays(eb164_pci_intr, irq); 347 } 348 349 #if 0 /* THIS DOES NOT WORK! see pci_eb164_intr.S. */ 350 u_int8_t eb164_intr_mask[3] = { 0xff, 0xff, 0xff }; 351 352 void 353 eb164_intr_enable(irq) 354 int irq; 355 { 356 int byte = (irq / 8), bit = (irq % 8); 357 358 #if 1 359 printf("eb164_intr_enable: enabling %d (%d:%d)\n", irq, byte, bit); 360 #endif 361 eb164_intr_mask[byte] &= ~(1 << bit); 362 363 bus_space_write_1(eb164_intrgate_iot, eb164_intrgate_ioh, byte, 364 eb164_intr_mask[byte]); 365 } 366 367 void 368 eb164_intr_disable(irq) 369 int irq; 370 { 371 int byte = (irq / 8), bit = (irq % 8); 372 373 #if 1 374 printf("eb164_intr_disable: disabling %d (%d:%d)\n", irq, byte, bit); 375 #endif 376 eb164_intr_mask[byte] |= (1 << bit); 377 378 bus_space_write_1(eb164_intrgate_iot, eb164_intrgate_ioh, byte, 379 eb164_intr_mask[byte]); 380 } 381 #endif 382