1 /* $OpenBSD: pci_1000.c,v 1.11 2015/07/26 05:09:44 miod Exp $ */ 2 /* $NetBSD: pci_1000.c,v 1.12 2001/07/27 00:25:20 thorpej Exp $ */ 3 4 /* 5 * Copyright (c) 1998 The NetBSD Foundation, Inc. 6 * All rights reserved. 7 * 8 * This code is based on pci_kn20aa.c, written by Chris G. Demetriou at 9 * Carnegie-Mellon University. Platform support for Mikasa and Mikasa/Pinnacle 10 * (Pinkasa) by Ross Harvey with copyright assignment by permission of Avalon 11 * Computer Systems, Inc. 12 * 13 * Redistribution and use in source and binary forms, with or without 14 * modification, are permitted provided that the following conditions 15 * are met: 16 * 1. Redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer. 18 * 2. Redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 23 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 24 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 25 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 32 * POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 /* 36 * Copyright (c) 1995, 1996 Carnegie-Mellon University. 37 * All rights reserved. 38 * 39 * Author: Chris G. Demetriou 40 * 41 * Permission to use, copy, modify and distribute this software and 42 * its documentation is hereby granted, provided that both the copyright 43 * notice and this permission notice appear in all copies of the 44 * software, derivative works or modified versions, and any portions 45 * thereof, and that both notices appear in supporting documentation. 46 * 47 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 48 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 49 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 50 * 51 * Carnegie Mellon requests users of this software to return to 52 * 53 * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU 54 * School of Computer Science 55 * Carnegie Mellon University 56 * Pittsburgh PA 15213-3890 57 * 58 * any improvements or extensions that they make and grant Carnegie the 59 * rights to redistribute these changes. 60 */ 61 62 #include <sys/types.h> 63 #include <sys/param.h> 64 #include <sys/time.h> 65 #include <sys/systm.h> 66 #include <sys/errno.h> 67 #include <sys/malloc.h> 68 #include <sys/device.h> 69 70 #include <uvm/uvm_extern.h> 71 72 #include <machine/autoconf.h> 73 74 #include <dev/pci/pcireg.h> 75 #include <dev/pci/pcivar.h> 76 #include <dev/pci/ppbreg.h> 77 78 #include <alpha/pci/pci_1000.h> 79 80 #include "sio.h" 81 #if NSIO > 0 || NPCEB > 0 82 #include <alpha/pci/siovar.h> 83 #endif 84 85 static bus_space_tag_t another_mystery_icu_iot; 86 static bus_space_handle_t another_mystery_icu_ioh; 87 88 int dec_1000_intr_map(struct pci_attach_args *, pci_intr_handle_t *); 89 const char *dec_1000_intr_string(void *, pci_intr_handle_t); 90 int dec_1000_intr_line(void *, pci_intr_handle_t); 91 void *dec_1000_intr_establish(void *, pci_intr_handle_t, 92 int, int (*func)(void *), void *, const char *); 93 void dec_1000_intr_disestablish(void *, void *); 94 95 #define PCI_NIRQ 16 96 #define PCI_STRAY_MAX 5 97 98 struct alpha_shared_intr *dec_1000_pci_intr; 99 100 void dec_1000_iointr(void *arg, unsigned long vec); 101 void dec_1000_enable_intr(int irq); 102 void dec_1000_disable_intr(int irq); 103 void pci_1000_imi(void); 104 105 void 106 pci_1000_pickintr(core, iot, memt, pc) 107 void *core; 108 bus_space_tag_t iot, memt; 109 pci_chipset_tag_t pc; 110 { 111 int i; 112 113 another_mystery_icu_iot = iot; 114 115 if (bus_space_map(iot, 0x536, 2, 0, &another_mystery_icu_ioh)) 116 panic("pci_1000_pickintr"); 117 pc->pc_intr_v = core; 118 pc->pc_intr_map = dec_1000_intr_map; 119 pc->pc_intr_string = dec_1000_intr_string; 120 pc->pc_intr_line = dec_1000_intr_line; 121 pc->pc_intr_establish = dec_1000_intr_establish; 122 pc->pc_intr_disestablish = dec_1000_intr_disestablish; 123 124 pc->pc_pciide_compat_intr_establish = NULL; 125 pc->pc_pciide_compat_intr_disestablish = NULL; 126 127 dec_1000_pci_intr = 128 alpha_shared_intr_alloc(PCI_NIRQ); 129 for (i = 0; i < PCI_NIRQ; i++) { 130 alpha_shared_intr_set_maxstrays(dec_1000_pci_intr, i, 131 PCI_STRAY_MAX); 132 } 133 134 pci_1000_imi(); 135 #if NSIO > 0 || NPCEB > 0 136 sio_intr_setup(pc, iot); 137 #endif 138 } 139 140 int 141 dec_1000_intr_map(pa, ihp) 142 struct pci_attach_args *pa; 143 pci_intr_handle_t *ihp; 144 { 145 pcitag_t bustag = pa->pa_intrtag; 146 int buspin, device, line = pa->pa_intrline; 147 148 /* 149 * The console places the interrupt mapping in the "line" value. 150 * We trust it whenever possible. 151 */ 152 if (line >= 0 && line < PCI_NIRQ) { 153 *ihp = line; 154 return 0; 155 } 156 157 if (pa->pa_bridgetag) { 158 buspin = PPB_INTERRUPT_SWIZZLE(pa->pa_rawintrpin, 159 pa->pa_device); 160 if (pa->pa_bridgeih[buspin - 1] == 0) 161 return 1; 162 163 *ihp = pa->pa_bridgeih[buspin - 1]; 164 return 0; 165 } 166 167 buspin = pa->pa_intrpin; 168 pci_decompose_tag(pa->pa_pc, bustag, NULL, &device, NULL); 169 170 switch (device) { 171 case 6: 172 if (buspin != 1) 173 break; 174 *ihp = 0xc; /* integrated ncr scsi */ 175 return 0; 176 case 11: 177 case 12: 178 case 13: 179 *ihp = (device - 11) * 4 + buspin - 1; 180 return 0; 181 } 182 183 return 1; 184 } 185 186 const char * 187 dec_1000_intr_string(ccv, ih) 188 void *ccv; 189 pci_intr_handle_t ih; 190 { 191 static const char irqmsg_fmt[] = "dec_1000 irq %ld"; 192 static char irqstr[sizeof irqmsg_fmt]; 193 194 if (ih >= PCI_NIRQ) 195 panic("dec_1000_intr_string: bogus dec_1000 IRQ 0x%lx", ih); 196 197 snprintf(irqstr, sizeof irqstr, irqmsg_fmt, ih); 198 return (irqstr); 199 } 200 201 int 202 dec_1000_intr_line(ccv, ih) 203 void *ccv; 204 pci_intr_handle_t ih; 205 { 206 #if NSIO > 0 207 return sio_intr_line(NULL /*XXX*/, ih); 208 #else 209 return (ih); 210 #endif 211 } 212 213 void * 214 dec_1000_intr_establish(ccv, ih, level, func, arg, name) 215 void *ccv; 216 pci_intr_handle_t ih; 217 int level; 218 int (*func)(void *); 219 void *arg; 220 const char *name; 221 { 222 void *cookie; 223 224 if (ih >= PCI_NIRQ) 225 panic("dec_1000_intr_establish: IRQ too high, 0x%lx", ih); 226 227 cookie = alpha_shared_intr_establish(dec_1000_pci_intr, ih, IST_LEVEL, 228 level, func, arg, name); 229 230 if (cookie != NULL && 231 alpha_shared_intr_firstactive(dec_1000_pci_intr, ih)) { 232 scb_set(0x900 + SCB_IDXTOVEC(ih), dec_1000_iointr, NULL); 233 dec_1000_enable_intr(ih); 234 } 235 return (cookie); 236 } 237 238 void 239 dec_1000_intr_disestablish(ccv, cookie) 240 void *ccv, *cookie; 241 { 242 struct alpha_shared_intrhand *ih = cookie; 243 unsigned int irq = ih->ih_num; 244 int s; 245 246 s = splhigh(); 247 248 alpha_shared_intr_disestablish(dec_1000_pci_intr, cookie); 249 if (alpha_shared_intr_isactive(dec_1000_pci_intr, irq) == 0) { 250 dec_1000_disable_intr(irq); 251 alpha_shared_intr_set_dfltsharetype(dec_1000_pci_intr, irq, 252 IST_NONE); 253 scb_free(0x900 + SCB_IDXTOVEC(irq)); 254 } 255 256 splx(s); 257 } 258 259 void 260 dec_1000_iointr(arg, vec) 261 void *arg; 262 unsigned long vec; 263 { 264 int irq; 265 266 irq = SCB_VECTOIDX(vec - 0x900); 267 268 if (!alpha_shared_intr_dispatch(dec_1000_pci_intr, irq)) { 269 alpha_shared_intr_stray(dec_1000_pci_intr, irq, 270 "dec_1000 irq"); 271 if (ALPHA_SHARED_INTR_DISABLE(dec_1000_pci_intr, irq)) 272 dec_1000_disable_intr(irq); 273 } else 274 alpha_shared_intr_reset_strays(dec_1000_pci_intr, irq); 275 } 276 277 /* 278 * Read and write the mystery ICU IMR registers 279 */ 280 281 #define IR() bus_space_read_2(another_mystery_icu_iot, \ 282 another_mystery_icu_ioh, 0) 283 284 #define IW(v) bus_space_write_2(another_mystery_icu_iot, \ 285 another_mystery_icu_ioh, 0, (v)) 286 287 /* 288 * Enable and disable interrupts at the ICU level 289 */ 290 291 void 292 dec_1000_enable_intr(irq) 293 int irq; 294 { 295 IW(IR() | 1 << irq); 296 } 297 298 void 299 dec_1000_disable_intr(irq) 300 int irq; 301 { 302 IW(IR() & ~(1 << irq)); 303 } 304 /* 305 * Initialize mystery ICU 306 */ 307 void 308 pci_1000_imi() 309 { 310 IW(0); /* XXX ?? */ 311 } 312