xref: /openbsd-src/share/man/man9/pci_conf_read.9 (revision f1dd7b858388b4a23f4f67a4957ec5ff656ebbe8)
1.\"	$OpenBSD: pci_conf_read.9,v 1.13 2021/05/01 16:11:10 visa Exp $
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3.\" Copyright (c) 2005 Michael Shalayeff
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18.Dd $Mdocdate: May 1 2021 $
19.Dt PCI_CONF_READ 9
20.Os
21.Sh NAME
22.Nm pci_make_tag ,
23.Nm pci_decompose_tag ,
24.Nm pci_conf_read ,
25.Nm pci_conf_write
26.Nd PCI config space manipulation functions
27.Sh SYNOPSIS
28.In alpha/pci/pci_machdep.h
29.In i386/pci/pci_machdep.h
30.In powerpc/pci/pci_machdep.h
31.In machine/pci_machdep.h
32.Ft pcitag_t
33.Fn pci_make_tag "pci_chipset_tag_t pc" "int bus" "int dev" "int func"
34.Ft void
35.Fn pci_decompose_tag "pci_chipset_tag_t pc" "pcitag_t tag" "int *busp" \
36"int *devp" "int *funcp"
37.Ft pcireg_t
38.Fn pci_conf_read "pci_chipset_tag_t pc" "pcitag_t tag" "int reg"
39.Ft void
40.Fn pci_conf_write "pci_chipset_tag_t pc" "pcitag_t tag" "int reg" \
41"pcireg_t val"
42.Sh DESCRIPTION
43These functions provide a way to access PCI configuration space.
44.Pp
45The following types are defined in the machine dependent include file
46.In pci_machdep.h .
47.Pp
48.Bl -tag -width pci_chipset_tag_t -offset indent -compact
49.It pci_chipset_tag_t
50a PCI chipset descriptor;
51.It pcitag_t
52a PCI device tag;
53.It pcireg_t
54a PCI register datum.
55.El
56.Pp
57In order to access PCI configuration space, a device tag shall be made using
58.Nm pci_make_tag
59given the PCI chipset tag
60.Ar pc
61and the device specification in a tuple of
62.Ar bus ,
63.Ar device ,
64.Ar function .
65The PCI tag composition is a PCI chipset dependent operation
66although often as simple as a shift and logical OR combination.
67.Pp
68The
69.Nm pci_decompose_tag
70provides a reverse operation.
71Once a tag is composed, it is possible to perform configuration
72space read and write with
73.Nm pci_conf_read
74and
75.Nm pci_conf_write ,
76respectively.
77Access to PCI configuration space is only provided for whole
78.Nm pcireg_t
79items, which is usually a 32-bit integer.
80Access to non-existent PCI devices do not (or should not) generate
81any kinds of faults or interruptions and thus allow for an easy device
82scanning by cycling through all possible device and function numbers
83for a given bus.
84.Pp
85Below is an overview of defined PCI configuration space registers for
86devices:
87.Bl -tag -width 0xff -offset indent
88.It 0x00
89Vendor (lower word) and Product (higher word) identification
90(see
91.Pa /sys/dev/pci/pcidevs
92for a comprehensive list).
93.It 0x04
94Commands and Status register.
95.It 0x08
96PCI device's class and subclass IDs.
97See
98.Pa /sys/dev/pci/pcireg.h
99for PCI_CLASS_* and PCI_SUBCLASS_* definitions.
100.It 0x0c
101Specify (low byte to high): cache line size, PCI latency timer, header type,
102and BIST.
103.It 0x10 - 0x28
104Base address registers for I/O and memory space mapped registers.
105.It 0x28
106CardBus CIS register.
107.It 0x2c
108Similar to 0x00 register's definitions for a subsystem identification.
109.It 0x34
110A pointer to the capabilities list.
111Each item is an offset in the configuration space itself.
112.It 0x3c
113Interrupt line and pin numbers.
114.El
115.Sh SEE ALSO
116.Xr cardbus 4 ,
117.Xr pci 4 ,
118.Xr pci_intr_map 9
119.Sh HISTORY
120These functions first appeared in
121.Ox 1.2 .
122.\" .Sh AUTHORS
123