1.\" $OpenBSD: pcibios.4,v 1.23 2008/07/01 04:14:57 ray Exp $ 2.\" $NetBSD: pcibios.4,v 1.7 2000/08/03 13:32:39 soda Exp $ 3.\" 4.\" Copyright (c) 2000 Michael Shalayeff, All rights reserved. 5.\" Copyright (c) 1999, 2000 The NetBSD Foundation, Inc. 6.\" All rights reserved. 7.\" 8.\" This code is derived from software contributed to The NetBSD Foundation 9.\" by Lennart Augustsson. 10.\" 11.\" Redistribution and use in source and binary forms, with or without 12.\" modification, are permitted provided that the following conditions 13.\" are met: 14.\" 1. Redistributions of source code must retain the above copyright 15.\" notice, this list of conditions and the following disclaimer. 16.\" 2. Redistributions in binary form must reproduce the above copyright 17.\" notice, this list of conditions and the following disclaimer in the 18.\" documentation and/or other materials provided with the distribution. 19.\" 20.\" THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21.\" ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22.\" TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23.\" PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24.\" BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25.\" CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26.\" SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27.\" INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28.\" CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29.\" ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30.\" POSSIBILITY OF SUCH DAMAGE. 31.\" 32.Dd $Mdocdate: July 1 2008 $ 33.Dt PCIBIOS 4 i386 34.Os 35.Sh NAME 36.Nm pcibios 37.Nd introduction to PCI BIOS support 38.Sh SYNOPSIS 39.Cd "pcibios0 at bios0 flags 0x0000" 40.\" .Cd "#option PCIBIOS_IRQS_HINT=0x0a00 #IRQ 9,11" 41.\" .Cd "#option PCIBIOS_INTR_FIXUP_FORCE" 42.Sh DESCRIPTION 43.Ox 44provides support for setting up PCI controllers, bridges, and devices 45using information extracted from the BIOS. 46.Pp 47Ideally, the boot firmware of a machine (a.k.a. BIOS) should set 48up all PCI devices; assigning them I/O and memory addresses and 49interrupts. 50Alas, this does not always happen, so there is some 51PC specific code that can do the initialization when 52.Ox 53boots. 54.Pp 55Flags is a bit mask each bit of which specifies a fixup procedure to 56omit. 57The following list specifies these procedures and gives 58flags bit values to disable them in case they cause problems. 59.Bl -tag -width 0x0000 60.It 0x0001 61Fixup PCI I/O and memory addresses. 62.Pp 63Some BIOS implementations don't allocate I/O space and 64memory space for all PCI devices. 65Especially, a BIOS which has 66.Qq PnP OS mode 67enabled shows this behavior. 68Since necessary space isn't allocated, those devices 69will not work without special handling. 70.Pp 71Without this flag force allocation of I/O space and memory space 72instead of relying upon the BIOS to do so. 73.Pp 74If necessary space is already correctly assigned to the devices, 75this option leaves the space as is. 76.Pp 77Although many BIOS implementations leave CardBus bridges' 78space unallocated, the CardBus bridge device driver doesn't 79require this option, since the driver allocates necessary space 80by itself. 81.It 0x0002 82Fixup PCI bus numbering; needed for many 83.Xr cardbus 4 84bridges. 85.Pp 86Each PCI bus and CardBus should have a unique bus number. 87But some BIOS implementations don't assign a bus number 88for subordinate PCI buses. 89And many BIOS implementations don't assign a bus number for CardBuses. 90.Pp 91A typical symptom of this is the following boot message: 92.D1 Sy cardbus0 at cardslot0: bus 0 device 0... 93Please note that this cardbus0 has a bus number 94.Sq 0 , 95but normally the bus number 0 is used by the machine's 96primary PCI bus. 97Thus, this bus number for cardbus is incorrect 98.Pq not assigned . 99In this situation, a device located in cardbus0 doesn't 100show correct device ID, 101because its bus number 0 incorrectly refers to the primary 102PCI bus, and a device ID in the primary PCI bus is shown 103in the boot message instead of the device's ID in the cardbus0. 104.Pp 105Without this flag force assignment of bus numbers for all subordinate 106PCI buses and CardBuses. 107.Pp 108Since this procedure renumbers all PCI buses and CardBuses, 109all bus numbers of subordinate buses become different 110when this option is enabled. 111.It 0x0004 112Fixup PCI interrupt routing. 113.Pp 114Some BIOS implementations don't assign an interrupt for 115some devices. 116.Pp 117This procedure assigns an interrupt for such devices instead 118of relying upon the BIOS to do so. 119.Pp 120If the BIOS has already assigned an interrupt to a device, this 121procedure leaves the interrupt as is. 122.It 0x0008 123Make PCI interrupt routing fixup work with unknown interrupt routers. 124If this flag is specified and a PCI interrupt routing table entry 125indicates that only one IRQ is available for the entry, the IRQ is 126assumed to be already connected to the device, and the corresponding PCI 127Interrupt Configuration Register will be configured accordingly. 128.Pp 129Without this flag, if a PCI interrupt router is not known, interrupt 130configuration will not be modified. 131.It 0x0010 132Be verbose when performing 133.Nm 134tasks. 135Included in these diagnostics are: PCI device address fixup tables, 136interrupt fixup reports, and other diagnostic and non-fatal messages. 137.It 0x0020 138Make the PCI interrupt routing fixup procedure verbose. 139.It 0x0040 140Some buggy BIOS implementations provide inconsistent information between 141the PCI Interrupt Configuration Register and the PCI Interrupt Routing table. 142In such cases, the PCI Interrupt Configuration Register takes precedence 143by default. 144If this flag is specified the PCI Interrupt Routing table takes precedence. 145.El 146.\" .It Nm PCIBIOS_IRQS_HINT 147.\" hint for IRQ use. 148.\" When the 149.\" .Em PCIBIOS_INTR_FIXUP 150.\" cannot guess an adequate IRQ for a device, the hint is used. 151.\" .Pp 152.\" The value is a logical or of power-of-2s of allowable interrupts: 153.\" .Bl -column "XX-0xffff" "XX-0xffff" "XX-0xffff" "XX-0xffff" -compact -offset 2n 154.\" .It Em "IRQ Value" Em "\tIRQ Value" Em "\tIRQ Value" Em "\tIRQ Value" 155.\" .It "\& 0 0x0001" "\t 4 0x0010" "\t 8 0x0100" "\t12 0x1000" 156.\" .It "\& 1 0x0002" "\t 5 0x0020" "\t 9 0x0200" "\t13 0x2000" 157.\" .It "\& 2 0x0004" "\t 6 0x0040" "\t10 0x0400" "\t14 0x4000" 158.\" .It "\& 3 0x0008" "\t 7 0x0080" "\t11 0x0800" "\t15 0x8000" 159.\" .El 160.\" For example, 161.\" .Qq Sy option PCIBIOS_IRQS_HINT=0x0a00 162.\" allows IRQ 9 and IRQ 11. 163.\" 164.\" The kernel global variable 165.\" .Va pcibios_irqs_hint 166.\" holds this value, 167.\" so a user can override this value without kernel recompilation. 168.\" For example: 169.\" .Bl -bullet -compact 170.\" .It 171.\" To specify this value on the fly, type the following command 172.\" at the boot prompt to drop into DDB (the in-kernel debugger; 173.\" you have to specify 174.\" .Qq Sy option DDB 175.\" to make kernel with DDB): 176.\" .Dl Ic boot -d 177.\" And type the following command on 178.\" .Qq Sy db> 179.\" prompt: 180.\" .Dl Ic write pcibios_irqs_hint 0x0a00 181.\" Then type the following to continue to boot: 182.\" .Dl Ic c 183.\" .It 184.\" To modify kernel image without kernel recompilation, 185.\" run the following command on shell: 186.\" .Dl Ic gdb --write /netbsd 187.\" And type the following commands at the 188.\" .Qq Sy (gdb) 189.\" prompt: 190.\" .Dl Ic set pcibios_irqs_hint=0xa00 191.\" .Dl Ic quit 192.\" .El 193.\" 194.Sh SEE ALSO 195.Xr bios 4 , 196.Xr intro 4 , 197.Xr pci 4 , 198.Xr pci_conf_read 9 , 199.Xr pci_intr_map 9 200.Sh HISTORY 201The 202.Nm 203code appeared in 204.Nx 1.5 . 205.Ox 206support was added in 207.Ox 2.8 . 208In contrast to 209.Nx 210implementation 211.Nm 212in 213.Ox 214is a real device, where options control is done through the 215.Nm flags 216which are modifiable through the 217.Xr boot_config 8 218interface. 219For 220.Ox 2.9 221the PCI interrupt routing establishment sequence was redone to only 222fixup and route interrupts when attaching interrupts for a particular PCI 223device. 224.Sh BUGS 225The 226.Em PCIBIOS Address Fixup 227option may conflict with the PCI CardBus driver's own 228address fixup. 229