1.\" $OpenBSD: ahc.4,v 1.38 2010/07/03 03:59:16 krw Exp $ 2.\" $NetBSD: ahc.4,v 1.1.2.1 1996/08/25 17:22:14 thorpej Exp $ 3.\" 4.\" Copyright (c) 1995, 1996 5.\" Justin T. Gibbs. All rights reserved. 6.\" 7.\" Redistribution and use in source and binary forms, with or without 8.\" modification, are permitted provided that the following conditions 9.\" are met: 10.\" 1. Redistributions of source code must retain the above copyright 11.\" notice, this list of conditions and the following disclaimer. 12.\" 2. Redistributions in binary form must reproduce the above copyright 13.\" notice, this list of conditions and the following disclaimer in the 14.\" documentation and/or other materials provided with the distribution. 15.\" 3. The name of the author may not be used to endorse or promote products 16.\" derived from this software without specific prior written permission. 17.\" 18.\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19.\" IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20.\" OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21.\" IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 22.\" INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 23.\" NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24.\" DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25.\" THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26.\" (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 27.\" THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28.\" 29.\" 30.Dd $Mdocdate: July 3 2010 $ 31.Dt AHC 4 32.Os 33.Sh NAME 34.Nm ahc 35.Nd Adaptec VL/EISA/PCI SCSI interface 36.Sh SYNOPSIS 37.Cd "ahc0 at isa? " Pq VL 38.Cd "ahc* at eisa? " Pq EISA 39.Cd "ahc* at pci? " Pq PCI 40.Cd "scsibus* at ahc?" 41.Cd "option AHC_ALLOW_MEMIO" 42.Cd "option AHC_TMODE_ENABLE" 43.Sh DESCRIPTION 44This driver provides access to the 45.Tn SCSI 46bus(es) connected to Adaptec 47.Tn AIC7770 , 48.Tn AIC7850 , 49.Tn AIC7860 , 50.Tn AIC7870 , 51.Tn AIC7880 , 52.Tn AIC7890 , 53.Tn AIC7891 , 54.Tn AIC7892 , 55.Tn AIC7895 , 56.Tn AIC7896 , 57.Tn AIC7897 58and 59.Tn AIC7899 60host adapter chips. 61These chips are found on many motherboards as well as the following 62Adaptec SCSI controller cards: 63.Tn 274X(W) , 64.Tn 274X(T) , 65.Tn 284X , 66.Tn 2910 , 67.Tn 2915 , 68.Tn 2920 , 69.Tn 2930C , 70.Tn 2930U2 , 71.Tn 2940 , 72.Tn 2940J , 73.Tn 2940N , 74.Tn 2940U , 75.Tn 2940AU , 76.Tn 2940UW , 77.Tn 2940UW Dual , 78.Tn 2940UW Pro , 79.Tn 2940U2W , 80.Tn 2940U2B , 81.Tn 2950U2W , 82.Tn 2950U2B , 83.Tn 19160B , 84.Tn 29160B , 85.Tn 29160N , 86.Tn 3940 , 87.Tn 3940U , 88.Tn 3940AU , 89.Tn 3940UW , 90.Tn 3940AUW , 91.Tn 3940U2W , 92.Tn 3950U2 , 93.Tn 3960 , 94.Tn 39160 , 95.Tn 3985 , 96and 97.Tn 4944UW . 98.Pp 99Driver features include support for twin and wide buses, 100fast, ultra, ultra2 and ultra160 synchronous transfers depending on 101controller type, tagged queuing, and SCB paging, and target mode. 102.Pp 103Memory mapped I/O can be enabled for PCI devices with the 104.Dq Dv AHC_ALLOW_MEMIO 105configuration option. 106Memory mapped I/O is more efficient than the alternative, programmed I/O. 107Most PCI BIOSes will map devices so that either technique for communicating 108with the card is available. 109In some cases, 110usually when the PCI device is sitting behind a PCI->PCI bridge, 111the BIOS may fail to properly initialize the chip for memory mapped I/O. 112The typical symptom of this problem is a system hang if memory mapped I/O 113is attempted. 114Most modern motherboards perform the initialization correctly and work fine 115with this option enabled. 116This is the default mode of operation on every architecture except i386. 117.Pp 118Individual controllers may be configured to operate in the target role through 119the 120.Dq Dv AHC_TMODE_ENABLE 121configuration option. 122The value assigned to this option should be a bitmap of all units where target 123mode is desired. 124For example, a value of 0x25, would enable target mode on units 0, 2, and 5. 125A value of 0x8a enables it for units 1, 3, and 7. 126.Pp 127Per target configuration performed in the 128.Tn SCSI-Select 129menu, accessible at boot 130in 131.No non- Ns Tn EISA 132models, 133or through an 134.Tn EISA 135configuration utility for 136.Tn EISA 137models, 138is honored by this driver. 139This includes synchronous/asynchronous transfers, 140maximum synchronous negotiation rate, 141wide transfers, 142disconnection, 143the host adapter's SCSI ID, 144and, 145in the case of 146.Tn EISA 147Twin Channel controllers, 148the primary channel selection. 149For systems that store non-volatile settings in a system specific manner 150rather than a serial eeprom directly connected to the aic7xxx controller, 151the 152.Tn BIOS 153must be enabled for the driver to access this information. 154This restriction applies to all 155.Tn EISA 156and many motherboard configurations. 157.Pp 158Note that I/O addresses are determined automatically by the probe routines, 159but care should be taken when using a 284x 160.Pq Tn VESA No local bus controller 161in an 162.Tn EISA 163system. 164The jumpers setting the I/O area for the 284x should match the 165.Tn EISA 166slot into which the card is inserted to prevent conflicts with other 167.Tn EISA 168cards. 169.Pp 170Performance and feature sets vary throughout the aic7xxx product line. 171The following table provides a comparison of the different chips supported by 172the 173.Nm 174driver. 175Note that wide and twin channel features, although always supported by a 176particular chip, may be disabled in a particular motherboard or card design. 177.Bd -literal 178.Em "Chip MIPS Bus MaxSync MaxWidth SCBs Features" 179aic7770 10 EISA/VL 10MHz 16Bit 4 1 180aic7850 10 PCI/32 10MHz 8Bit 3 181aic7860 10 PCI/32 20MHz 8Bit 3 182aic7870 10 PCI/32 10MHz 16Bit 16 183aic7880 10 PCI/32 20MHz 16Bit 16 184aic7890 20 PCI/32 40MHz 16Bit 16 3 4 5 6 7 8 185aic7891 20 PCI/64 40MHz 16Bit 16 3 4 5 6 7 8 186aic7892 20 PCI/64 80MHz 16Bit 16 3 4 5 6 7 8 187aic7895 15 PCI/32 20MHz 16Bit 16 2 3 4 5 188aic7895C 15 PCI/32 20MHz 16Bit 16 2 3 4 5 8 189aic7896 20 PCI/32 40MHz 16Bit 16 2 3 4 5 6 7 8 190aic7897 20 PCI/64 40MHz 16Bit 16 2 3 4 5 6 7 8 191aic7899 20 PCI/64 80MHz 16Bit 16 2 3 4 5 6 7 8 192.Ed 193.Pp 194.Bl -enum -compact 195.It 196Multiplexed Twin Channel Device - One controller servicing two buses. 197.It 198Multi-function Twin Channel Device - Two controllers on one chip. 199.It 200Command Channel Secondary DMA Engine - Allows scatter gather list and 201SCB prefetch. 202.It 20364 Byte SCB Support - SCSI CDB is embedded in the SCB to eliminate an extra DMA. 204.It 205Block Move Instruction Support - Doubles the speed of certain sequencer 206operations. 207.It 208.Sq Bayonet 209style Scatter Gather Engine - Improves S/G prefetch performance. 210.It 211Queuing Registers - Allows queuing of new transactions without pausing the 212sequencer. 213.It 214Ultra160 support. 215.It 216Multiple Target IDs - Allows the controller to respond to selection as a target 217on multiple SCSI IDs. 218.El 219.Sh SCSI CONTROL BLOCKS (SCBs) 220Every transaction sent to a device on the SCSI bus is assigned a 221.Sq SCSI Control Block 222(SCB). 223The SCB contains all of the information required by the controller to process a 224transaction. 225The chip feature table lists the number of SCBs that can be stored in on-chip 226memory. 227All chips with model numbers greater than or equal to 7870 allow for the 228on-chip SCB space to be augmented with external SRAM up to a maximum of 255 229SCBs. 230Very few Adaptec controller configurations have external SRAM. 231.Pp 232If external SRAM is not available, 233SCBs are a limited resource. 234Using the SCBs in a straight forward manner would only allow the driver to 235handle as many concurrent transactions as there are physical SCBs. 236To fully utilize the SCSI bus and the devices on it, 237requires much more concurrency. 238The solution to this problem is 239.Em SCB Paging , 240a concept similar to memory paging. 241SCB paging takes advantage of the fact that devices usually disconnect from the 242SCSI bus for long periods of time without talking to the controller. 243The SCBs for disconnected transactions are only of use to the controller when 244the transfer is resumed. 245When the host queues another transaction for the controller to execute, 246the controller firmware will use a free SCB if one is available. 247Otherwise, the state of the most recently disconnected (and therefore most 248likely to stay disconnected) SCB is saved, via DMA, to host memory, 249and the local SCB reused to start the new transaction. 250This allows the controller to queue up to 255 transactions regardless of the 251amount of SCB space. 252Since the local SCB space serves as a cache for disconnected transactions, 253the more SCB space available, the less host bus traffic consumed saving and 254restoring SCB data. 255.Sh SEE ALSO 256.Xr ahd 4 , 257.Xr cd 4 , 258.Xr ch 4 , 259.Xr eisa 4 , 260.Xr intro 4 , 261.Xr isa 4 , 262.Xr pci 4 , 263.Xr scsi 4 , 264.Xr sd 4 , 265.Xr st 4 , 266.Xr uk 4 267.Sh AUTHORS 268The core 269.Nm 270driver, the 271.Tn AIC7xxx 272sequencer-code assembler, and the firmware running on the aic7xxx chips 273were written by 274.An Justin T. Gibbs . 275.Pp 276The 277.Ox 278platform dependent code was written by Steve P. Murphree, Jr and Kenneth 279R. Westerback. 280.Sh BUGS 281Some Quantum drives (at least the Empire 2100 and 1080s) will not run on an 282.Tn AIC7870 283Rev B in synchronous mode at 10MHz. 284Controllers with this problem have a 42 MHz clock crystal on them and run 285slightly above 10MHz. 286This confuses the drive and hangs the bus. 287Setting a maximum synchronous negotiation rate of 8MHz in the 288.Tn SCSI-Select 289utility will allow normal operation. 290.Pp 291Although the Ultra2 and Ultra160 products have sufficient instruction RAM space 292to support both the initiator and target roles concurrently, 293this configuration is disabled in favor of allowing the target role to respond 294on multiple target ids. 295A method for configuring dual role mode should be provided. 296.Pp 297Tagged Queuing is not supported in target mode. 298.Pp 299Reselection in target mode fails to function correctly on all high voltage 300differential boards as shipped by Adaptec. 301Information on how to modify HVD board to work correctly in target mode is 302available from Adaptec. 303