1 /* $OpenBSD: fpu_implode.c,v 1.2 2007/02/12 19:47:10 jason Exp $ */ 2 3 /* 4 * Copyright (c) 1992, 1993 5 * The Regents of the University of California. All rights reserved. 6 * 7 * This software was developed by the Computer Systems Engineering group 8 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 9 * contributed to Berkeley. 10 * 11 * All advertising materials mentioning features or use of this software 12 * must display the following acknowledgement: 13 * This product includes software developed by the University of 14 * California, Lawrence Berkeley Laboratory. 15 * 16 * Redistribution and use in source and binary forms, with or without 17 * modification, are permitted provided that the following conditions 18 * are met: 19 * 1. Redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer. 21 * 2. Redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution. 24 * 3. All advertising materials mentioning features or use of this software 25 * must display the following acknowledgement: 26 * This product includes software developed by the University of 27 * California, Berkeley and its contributors. 28 * 4. Neither the name of the University nor the names of its contributors 29 * may be used to endorse or promote products derived from this software 30 * without specific prior written permission. 31 * 32 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 33 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 34 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 35 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 36 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 37 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 38 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 39 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 40 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 41 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 42 * SUCH DAMAGE. 43 * 44 * @(#)fpu_implode.c 8.1 (Berkeley) 6/11/93 45 * $NetBSD: fpu_implode.c,v 1.8 2001/08/26 05:44:46 eeh Exp $ 46 */ 47 48 #include <sys/cdefs.h> 49 #if 0 50 __FBSDID("$FreeBSD: src/lib/libc/sparc64/fpu/fpu_implode.c,v 1.5 2002/04/27 21:56:28 jake Exp $"); 51 #endif 52 53 /* 54 * FPU subroutines: `implode' internal format numbers into the machine's 55 * `packed binary' format. 56 */ 57 58 #include <sys/param.h> 59 60 #include <machine/frame.h> 61 #include <machine/fsr.h> 62 #include <machine/ieee.h> 63 #include <machine/instr.h> 64 65 #include "fpu_arith.h" 66 #include "fpu_emu.h" 67 #include "fpu_extern.h" 68 69 static int round(struct fpemu *, struct fpn *); 70 static int toinf(struct fpemu *, int); 71 72 #define FSR_GET_RD(fsr) (((fsr) >> FSR_RD_SHIFT) & FSR_RD_MASK) 73 74 /* 75 * Round a number (algorithm from Motorola MC68882 manual, modified for 76 * our internal format). Set inexact exception if rounding is required. 77 * Return true iff we rounded up. 78 * 79 * After rounding, we discard the guard and round bits by shifting right 80 * 2 bits (a la fpu_shr(), but we do not bother with fp->fp_sticky). 81 * This saves effort later. 82 * 83 * Note that we may leave the value 2.0 in fp->fp_mant; it is the caller's 84 * responsibility to fix this if necessary. 85 */ 86 static int 87 round(struct fpemu *fe, struct fpn *fp) 88 { 89 u_int m0, m1, m2, m3; 90 int gr, s; 91 92 m0 = fp->fp_mant[0]; 93 m1 = fp->fp_mant[1]; 94 m2 = fp->fp_mant[2]; 95 m3 = fp->fp_mant[3]; 96 gr = m3 & 3; 97 s = fp->fp_sticky; 98 99 /* mant >>= FP_NG */ 100 m3 = (m3 >> FP_NG) | (m2 << (32 - FP_NG)); 101 m2 = (m2 >> FP_NG) | (m1 << (32 - FP_NG)); 102 m1 = (m1 >> FP_NG) | (m0 << (32 - FP_NG)); 103 m0 >>= FP_NG; 104 105 if ((gr | s) == 0) /* result is exact: no rounding needed */ 106 goto rounddown; 107 108 fe->fe_cx |= FSR_NX; /* inexact */ 109 110 /* Go to rounddown to round down; break to round up. */ 111 switch (FSR_GET_RD(fe->fe_fsr)) { 112 case FSR_RD_RN: 113 default: 114 /* 115 * Round only if guard is set (gr & 2). If guard is set, 116 * but round & sticky both clear, then we want to round 117 * but have a tie, so round to even, i.e., add 1 iff odd. 118 */ 119 if ((gr & 2) == 0) 120 goto rounddown; 121 if ((gr & 1) || fp->fp_sticky || (m3 & 1)) 122 break; 123 goto rounddown; 124 125 case FSR_RD_RZ: 126 /* Round towards zero, i.e., down. */ 127 goto rounddown; 128 129 case FSR_RD_RM: 130 /* Round towards -Inf: up if negative, down if positive. */ 131 if (fp->fp_sign) 132 break; 133 goto rounddown; 134 135 case FSR_RD_RP: 136 /* Round towards +Inf: up if positive, down otherwise. */ 137 if (!fp->fp_sign) 138 break; 139 goto rounddown; 140 } 141 142 /* Bump low bit of mantissa, with carry. */ 143 FPU_ADDS(m3, m3, 1); 144 FPU_ADDCS(m2, m2, 0); 145 FPU_ADDCS(m1, m1, 0); 146 FPU_ADDC(m0, m0, 0); 147 fp->fp_mant[0] = m0; 148 fp->fp_mant[1] = m1; 149 fp->fp_mant[2] = m2; 150 fp->fp_mant[3] = m3; 151 return (1); 152 153 rounddown: 154 fp->fp_mant[0] = m0; 155 fp->fp_mant[1] = m1; 156 fp->fp_mant[2] = m2; 157 fp->fp_mant[3] = m3; 158 return (0); 159 } 160 161 /* 162 * For overflow: return true if overflow is to go to +/-Inf, according 163 * to the sign of the overflowing result. If false, overflow is to go 164 * to the largest magnitude value instead. 165 */ 166 static int 167 toinf(struct fpemu *fe, int sign) 168 { 169 int inf; 170 171 /* look at rounding direction */ 172 switch (FSR_GET_RD(fe->fe_fsr)) { 173 default: 174 case FSR_RD_RN: /* the nearest value is always Inf */ 175 inf = 1; 176 break; 177 178 case FSR_RD_RZ: /* toward 0 => never towards Inf */ 179 inf = 0; 180 break; 181 182 case FSR_RD_RP: /* toward +Inf iff positive */ 183 inf = sign == 0; 184 break; 185 186 case FSR_RD_RM: /* toward -Inf iff negative */ 187 inf = sign; 188 break; 189 } 190 return (inf); 191 } 192 193 /* 194 * fpn -> int (int value returned as return value). 195 * 196 * N.B.: this conversion always rounds towards zero (this is a peculiarity 197 * of the SPARC instruction set). 198 */ 199 u_int 200 __fpu_ftoi(fe, fp) 201 struct fpemu *fe; 202 struct fpn *fp; 203 { 204 u_int i; 205 int sign, exp; 206 207 sign = fp->fp_sign; 208 switch (fp->fp_class) { 209 210 case FPC_ZERO: 211 return (0); 212 213 case FPC_NUM: 214 /* 215 * If exp >= 2^32, overflow. Otherwise shift value right 216 * into last mantissa word (this will not exceed 0xffffffff), 217 * shifting any guard and round bits out into the sticky 218 * bit. Then ``round'' towards zero, i.e., just set an 219 * inexact exception if sticky is set (see round()). 220 * If the result is > 0x80000000, or is positive and equals 221 * 0x80000000, overflow; otherwise the last fraction word 222 * is the result. 223 */ 224 if ((exp = fp->fp_exp) >= 32) 225 break; 226 /* NB: the following includes exp < 0 cases */ 227 if (__fpu_shr(fp, FP_NMANT - 1 - exp) != 0) 228 fe->fe_cx |= FSR_NX; 229 i = fp->fp_mant[3]; 230 if (i >= ((u_int)0x80000000 + sign)) 231 break; 232 return (sign ? -i : i); 233 234 default: /* Inf, qNaN, sNaN */ 235 break; 236 } 237 /* overflow: replace any inexact exception with invalid */ 238 fe->fe_cx = (fe->fe_cx & ~FSR_NX) | FSR_NV; 239 return (0x7fffffff + sign); 240 } 241 242 /* 243 * fpn -> extended int (high bits of int value returned as return value). 244 * 245 * N.B.: this conversion always rounds towards zero (this is a peculiarity 246 * of the SPARC instruction set). 247 */ 248 u_int 249 __fpu_ftox(fe, fp, res) 250 struct fpemu *fe; 251 struct fpn *fp; 252 u_int *res; 253 { 254 u_int64_t i; 255 int sign, exp; 256 257 sign = fp->fp_sign; 258 switch (fp->fp_class) { 259 260 case FPC_ZERO: 261 res[1] = 0; 262 return (0); 263 264 case FPC_NUM: 265 /* 266 * If exp >= 2^64, overflow. Otherwise shift value right 267 * into last mantissa word (this will not exceed 268 * 0xffffffffffffffff), shifting any guard and round bits out 269 * into the sticky bit. Then ``round'' towards zero, i.e., 270 * just set an inexact exception if sticky is set (see round()). 271 * If the result is > 0x8000000000000000, or is positive and 272 * equals 0x8000000000000000, overflow; otherwise the 273 * last fraction word is the result. 274 */ 275 if ((exp = fp->fp_exp) >= 64) 276 break; 277 /* NB: the following includes exp < 0 cases */ 278 if (__fpu_shr(fp, FP_NMANT - 1 - exp) != 0) 279 fe->fe_cx |= FSR_NX; 280 i = ((u_int64_t)fp->fp_mant[2]<<32)|fp->fp_mant[3]; 281 if (i >= ((u_int64_t)0x8000000000000000LL + sign)) 282 break; 283 if (sign) 284 i = -i; 285 res[1] = (int)i; 286 return (i >> 32); 287 288 default: /* Inf, qNaN, sNaN */ 289 break; 290 } 291 /* overflow: replace any inexact exception with invalid */ 292 fe->fe_cx = (fe->fe_cx & ~FSR_NX) | FSR_NV; 293 return (0x7fffffffffffffffLL + sign); 294 } 295 296 /* 297 * fpn -> single (32 bit single returned as return value). 298 * We assume <= 29 bits in a single-precision fraction (1.f part). 299 */ 300 u_int 301 __fpu_ftos(fe, fp) 302 struct fpemu *fe; 303 struct fpn *fp; 304 { 305 u_int sign = fp->fp_sign << 31; 306 int exp; 307 308 #define SNG_EXP(e) ((e) << SNG_FRACBITS) /* makes e an exponent */ 309 #define SNG_MASK (SNG_EXP(1) - 1) /* mask for fraction */ 310 311 /* Take care of non-numbers first. */ 312 if (ISNAN(fp)) { 313 /* 314 * Preserve upper bits of NaN, per SPARC V8 appendix N. 315 * Note that fp->fp_mant[0] has the quiet bit set, 316 * even if it is classified as a signalling NaN. 317 */ 318 (void) __fpu_shr(fp, FP_NMANT - 1 - SNG_FRACBITS); 319 exp = SNG_EXP_INFNAN; 320 goto done; 321 } 322 if (ISINF(fp)) 323 return (sign | SNG_EXP(SNG_EXP_INFNAN)); 324 if (ISZERO(fp)) 325 return (sign); 326 327 /* 328 * Normals (including subnormals). Drop all the fraction bits 329 * (including the explicit ``implied'' 1 bit) down into the 330 * single-precision range. If the number is subnormal, move 331 * the ``implied'' 1 into the explicit range as well, and shift 332 * right to introduce leading zeroes. Rounding then acts 333 * differently for normals and subnormals: the largest subnormal 334 * may round to the smallest normal (1.0 x 2^minexp), or may 335 * remain subnormal. In the latter case, signal an underflow 336 * if the result was inexact or if underflow traps are enabled. 337 * 338 * Rounding a normal, on the other hand, always produces another 339 * normal (although either way the result might be too big for 340 * single precision, and cause an overflow). If rounding a 341 * normal produces 2.0 in the fraction, we need not adjust that 342 * fraction at all, since both 1.0 and 2.0 are zero under the 343 * fraction mask. 344 * 345 * Note that the guard and round bits vanish from the number after 346 * rounding. 347 */ 348 if ((exp = fp->fp_exp + SNG_EXP_BIAS) <= 0) { /* subnormal */ 349 /* -NG for g,r; -SNG_FRACBITS-exp for fraction */ 350 (void) __fpu_shr(fp, FP_NMANT - FP_NG - SNG_FRACBITS - exp); 351 if (round(fe, fp) && fp->fp_mant[3] == SNG_EXP(1)) 352 return (sign | SNG_EXP(1) | 0); 353 if ((fe->fe_cx & FSR_NX) || 354 (fe->fe_fsr & (FSR_UF << FSR_TEM_SHIFT))) 355 fe->fe_cx |= FSR_UF; 356 return (sign | SNG_EXP(0) | fp->fp_mant[3]); 357 } 358 /* -FP_NG for g,r; -1 for implied 1; -SNG_FRACBITS for fraction */ 359 (void) __fpu_shr(fp, FP_NMANT - FP_NG - 1 - SNG_FRACBITS); 360 #ifdef DIAGNOSTIC 361 if ((fp->fp_mant[3] & SNG_EXP(1 << FP_NG)) == 0) 362 __utrap_panic("fpu_ftos"); 363 #endif 364 if (round(fe, fp) && fp->fp_mant[3] == SNG_EXP(2)) 365 exp++; 366 if (exp >= SNG_EXP_INFNAN) { 367 /* overflow to inf or to max single */ 368 fe->fe_cx |= FSR_OF | FSR_NX; 369 if (toinf(fe, sign)) 370 return (sign | SNG_EXP(SNG_EXP_INFNAN)); 371 return (sign | SNG_EXP(SNG_EXP_INFNAN - 1) | SNG_MASK); 372 } 373 done: 374 /* phew, made it */ 375 return (sign | SNG_EXP(exp) | (fp->fp_mant[3] & SNG_MASK)); 376 } 377 378 /* 379 * fpn -> double (32 bit high-order result returned; 32-bit low order result 380 * left in res[1]). Assumes <= 61 bits in double precision fraction. 381 * 382 * This code mimics fpu_ftos; see it for comments. 383 */ 384 u_int 385 __fpu_ftod(fe, fp, res) 386 struct fpemu *fe; 387 struct fpn *fp; 388 u_int *res; 389 { 390 u_int sign = fp->fp_sign << 31; 391 int exp; 392 393 #define DBL_EXP(e) ((e) << (DBL_FRACBITS & 31)) 394 #define DBL_MASK (DBL_EXP(1) - 1) 395 396 if (ISNAN(fp)) { 397 (void) __fpu_shr(fp, FP_NMANT - 1 - DBL_FRACBITS); 398 exp = DBL_EXP_INFNAN; 399 goto done; 400 } 401 if (ISINF(fp)) { 402 sign |= DBL_EXP(DBL_EXP_INFNAN); 403 goto zero; 404 } 405 if (ISZERO(fp)) { 406 zero: res[1] = 0; 407 return (sign); 408 } 409 410 if ((exp = fp->fp_exp + DBL_EXP_BIAS) <= 0) { 411 (void) __fpu_shr(fp, FP_NMANT - FP_NG - DBL_FRACBITS - exp); 412 if (round(fe, fp) && fp->fp_mant[2] == DBL_EXP(1)) { 413 res[1] = 0; 414 return (sign | DBL_EXP(1) | 0); 415 } 416 if ((fe->fe_cx & FSR_NX) || 417 (fe->fe_fsr & (FSR_UF << FSR_TEM_SHIFT))) 418 fe->fe_cx |= FSR_UF; 419 exp = 0; 420 goto done; 421 } 422 (void) __fpu_shr(fp, FP_NMANT - FP_NG - 1 - DBL_FRACBITS); 423 if (round(fe, fp) && fp->fp_mant[2] == DBL_EXP(2)) 424 exp++; 425 if (exp >= DBL_EXP_INFNAN) { 426 fe->fe_cx |= FSR_OF | FSR_NX; 427 if (toinf(fe, sign)) { 428 res[1] = 0; 429 return (sign | DBL_EXP(DBL_EXP_INFNAN) | 0); 430 } 431 res[1] = ~0; 432 return (sign | DBL_EXP(DBL_EXP_INFNAN) | DBL_MASK); 433 } 434 done: 435 res[1] = fp->fp_mant[3]; 436 return (sign | DBL_EXP(exp) | (fp->fp_mant[2] & DBL_MASK)); 437 } 438 439 /* 440 * fpn -> extended (32 bit high-order result returned; low-order fraction 441 * words left in res[1]..res[3]). Like ftod, which is like ftos ... but 442 * our internal format *is* extended precision, plus 2 bits for guard/round, 443 * so we can avoid a small bit of work. 444 */ 445 u_int 446 __fpu_ftoq(fe, fp, res) 447 struct fpemu *fe; 448 struct fpn *fp; 449 u_int *res; 450 { 451 u_int sign = fp->fp_sign << 31; 452 int exp; 453 454 #define EXT_EXP(e) ((e) << (EXT_FRACBITS & 31)) 455 #define EXT_MASK (EXT_EXP(1) - 1) 456 457 if (ISNAN(fp)) { 458 (void) __fpu_shr(fp, 2); /* since we are not rounding */ 459 exp = EXT_EXP_INFNAN; 460 goto done; 461 } 462 if (ISINF(fp)) { 463 sign |= EXT_EXP(EXT_EXP_INFNAN); 464 goto zero; 465 } 466 if (ISZERO(fp)) { 467 zero: res[1] = res[2] = res[3] = 0; 468 return (sign); 469 } 470 471 if ((exp = fp->fp_exp + EXT_EXP_BIAS) <= 0) { 472 (void) __fpu_shr(fp, FP_NMANT - FP_NG - EXT_FRACBITS - exp); 473 if (round(fe, fp) && fp->fp_mant[0] == EXT_EXP(1)) { 474 res[1] = res[2] = res[3] = 0; 475 return (sign | EXT_EXP(1) | 0); 476 } 477 if ((fe->fe_cx & FSR_NX) || 478 (fe->fe_fsr & (FSR_UF << FSR_TEM_SHIFT))) 479 fe->fe_cx |= FSR_UF; 480 exp = 0; 481 goto done; 482 } 483 /* Since internal == extended, no need to shift here. */ 484 if (round(fe, fp) && fp->fp_mant[0] == EXT_EXP(2)) 485 exp++; 486 if (exp >= EXT_EXP_INFNAN) { 487 fe->fe_cx |= FSR_OF | FSR_NX; 488 if (toinf(fe, sign)) { 489 res[1] = res[2] = res[3] = 0; 490 return (sign | EXT_EXP(EXT_EXP_INFNAN) | 0); 491 } 492 res[1] = res[2] = res[3] = ~0; 493 return (sign | EXT_EXP(EXT_EXP_INFNAN) | EXT_MASK); 494 } 495 done: 496 res[1] = fp->fp_mant[1]; 497 res[2] = fp->fp_mant[2]; 498 res[3] = fp->fp_mant[3]; 499 return (sign | EXT_EXP(exp) | (fp->fp_mant[0] & EXT_MASK)); 500 } 501 502 /* 503 * Implode an fpn, writing the result into the given space. 504 */ 505 void 506 __fpu_implode(fe, fp, type, space) 507 struct fpemu *fe; 508 struct fpn *fp; 509 int type; 510 u_int *space; 511 { 512 513 switch (type) { 514 515 case FTYPE_LNG: 516 space[0] = __fpu_ftox(fe, fp, space); 517 break; 518 519 case FTYPE_INT: 520 space[0] = __fpu_ftoi(fe, fp); 521 break; 522 523 case FTYPE_SNG: 524 space[0] = __fpu_ftos(fe, fp); 525 break; 526 527 case FTYPE_DBL: 528 space[0] = __fpu_ftod(fe, fp, space); 529 break; 530 531 case FTYPE_EXT: 532 /* funky rounding precision options ?? */ 533 space[0] = __fpu_ftoq(fe, fp, space); 534 break; 535 536 #ifdef DIAGNOSTIC 537 default: 538 __utrap_panic("fpu_implode"); 539 #endif 540 } 541 DPRINTF(FPE_REG, ("fpu_implode: %x %x %x %x\n", 542 space[0], space[1], space[2], space[3])); 543 } 544