1 /* $OpenBSD: fpu_implode.c,v 1.3 2012/12/05 23:19:59 deraadt Exp $ */ 2 3 /* 4 * Copyright (c) 1992, 1993 5 * The Regents of the University of California. All rights reserved. 6 * 7 * This software was developed by the Computer Systems Engineering group 8 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 9 * contributed to Berkeley. 10 * 11 * All advertising materials mentioning features or use of this software 12 * must display the following acknowledgement: 13 * This product includes software developed by the University of 14 * California, Lawrence Berkeley Laboratory. 15 * 16 * Redistribution and use in source and binary forms, with or without 17 * modification, are permitted provided that the following conditions 18 * are met: 19 * 1. Redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer. 21 * 2. Redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution. 24 * 3. All advertising materials mentioning features or use of this software 25 * must display the following acknowledgement: 26 * This product includes software developed by the University of 27 * California, Berkeley and its contributors. 28 * 4. Neither the name of the University nor the names of its contributors 29 * may be used to endorse or promote products derived from this software 30 * without specific prior written permission. 31 * 32 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 33 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 34 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 35 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 36 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 37 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 38 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 39 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 40 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 41 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 42 * SUCH DAMAGE. 43 * 44 * @(#)fpu_implode.c 8.1 (Berkeley) 6/11/93 45 * $NetBSD: fpu_implode.c,v 1.8 2001/08/26 05:44:46 eeh Exp $ 46 */ 47 48 #if 0 49 __FBSDID("$FreeBSD: src/lib/libc/sparc64/fpu/fpu_implode.c,v 1.5 2002/04/27 21:56:28 jake Exp $"); 50 #endif 51 52 /* 53 * FPU subroutines: `implode' internal format numbers into the machine's 54 * `packed binary' format. 55 */ 56 57 #include <sys/param.h> 58 59 #include <machine/frame.h> 60 #include <machine/fsr.h> 61 #include <machine/ieee.h> 62 #include <machine/instr.h> 63 64 #include "fpu_arith.h" 65 #include "fpu_emu.h" 66 #include "fpu_extern.h" 67 68 static int round(struct fpemu *, struct fpn *); 69 static int toinf(struct fpemu *, int); 70 71 #define FSR_GET_RD(fsr) (((fsr) >> FSR_RD_SHIFT) & FSR_RD_MASK) 72 73 /* 74 * Round a number (algorithm from Motorola MC68882 manual, modified for 75 * our internal format). Set inexact exception if rounding is required. 76 * Return true iff we rounded up. 77 * 78 * After rounding, we discard the guard and round bits by shifting right 79 * 2 bits (a la fpu_shr(), but we do not bother with fp->fp_sticky). 80 * This saves effort later. 81 * 82 * Note that we may leave the value 2.0 in fp->fp_mant; it is the caller's 83 * responsibility to fix this if necessary. 84 */ 85 static int 86 round(struct fpemu *fe, struct fpn *fp) 87 { 88 u_int m0, m1, m2, m3; 89 int gr, s; 90 91 m0 = fp->fp_mant[0]; 92 m1 = fp->fp_mant[1]; 93 m2 = fp->fp_mant[2]; 94 m3 = fp->fp_mant[3]; 95 gr = m3 & 3; 96 s = fp->fp_sticky; 97 98 /* mant >>= FP_NG */ 99 m3 = (m3 >> FP_NG) | (m2 << (32 - FP_NG)); 100 m2 = (m2 >> FP_NG) | (m1 << (32 - FP_NG)); 101 m1 = (m1 >> FP_NG) | (m0 << (32 - FP_NG)); 102 m0 >>= FP_NG; 103 104 if ((gr | s) == 0) /* result is exact: no rounding needed */ 105 goto rounddown; 106 107 fe->fe_cx |= FSR_NX; /* inexact */ 108 109 /* Go to rounddown to round down; break to round up. */ 110 switch (FSR_GET_RD(fe->fe_fsr)) { 111 case FSR_RD_RN: 112 default: 113 /* 114 * Round only if guard is set (gr & 2). If guard is set, 115 * but round & sticky both clear, then we want to round 116 * but have a tie, so round to even, i.e., add 1 iff odd. 117 */ 118 if ((gr & 2) == 0) 119 goto rounddown; 120 if ((gr & 1) || fp->fp_sticky || (m3 & 1)) 121 break; 122 goto rounddown; 123 124 case FSR_RD_RZ: 125 /* Round towards zero, i.e., down. */ 126 goto rounddown; 127 128 case FSR_RD_RM: 129 /* Round towards -Inf: up if negative, down if positive. */ 130 if (fp->fp_sign) 131 break; 132 goto rounddown; 133 134 case FSR_RD_RP: 135 /* Round towards +Inf: up if positive, down otherwise. */ 136 if (!fp->fp_sign) 137 break; 138 goto rounddown; 139 } 140 141 /* Bump low bit of mantissa, with carry. */ 142 FPU_ADDS(m3, m3, 1); 143 FPU_ADDCS(m2, m2, 0); 144 FPU_ADDCS(m1, m1, 0); 145 FPU_ADDC(m0, m0, 0); 146 fp->fp_mant[0] = m0; 147 fp->fp_mant[1] = m1; 148 fp->fp_mant[2] = m2; 149 fp->fp_mant[3] = m3; 150 return (1); 151 152 rounddown: 153 fp->fp_mant[0] = m0; 154 fp->fp_mant[1] = m1; 155 fp->fp_mant[2] = m2; 156 fp->fp_mant[3] = m3; 157 return (0); 158 } 159 160 /* 161 * For overflow: return true if overflow is to go to +/-Inf, according 162 * to the sign of the overflowing result. If false, overflow is to go 163 * to the largest magnitude value instead. 164 */ 165 static int 166 toinf(struct fpemu *fe, int sign) 167 { 168 int inf; 169 170 /* look at rounding direction */ 171 switch (FSR_GET_RD(fe->fe_fsr)) { 172 default: 173 case FSR_RD_RN: /* the nearest value is always Inf */ 174 inf = 1; 175 break; 176 177 case FSR_RD_RZ: /* toward 0 => never towards Inf */ 178 inf = 0; 179 break; 180 181 case FSR_RD_RP: /* toward +Inf iff positive */ 182 inf = sign == 0; 183 break; 184 185 case FSR_RD_RM: /* toward -Inf iff negative */ 186 inf = sign; 187 break; 188 } 189 return (inf); 190 } 191 192 /* 193 * fpn -> int (int value returned as return value). 194 * 195 * N.B.: this conversion always rounds towards zero (this is a peculiarity 196 * of the SPARC instruction set). 197 */ 198 u_int 199 __fpu_ftoi(fe, fp) 200 struct fpemu *fe; 201 struct fpn *fp; 202 { 203 u_int i; 204 int sign, exp; 205 206 sign = fp->fp_sign; 207 switch (fp->fp_class) { 208 209 case FPC_ZERO: 210 return (0); 211 212 case FPC_NUM: 213 /* 214 * If exp >= 2^32, overflow. Otherwise shift value right 215 * into last mantissa word (this will not exceed 0xffffffff), 216 * shifting any guard and round bits out into the sticky 217 * bit. Then ``round'' towards zero, i.e., just set an 218 * inexact exception if sticky is set (see round()). 219 * If the result is > 0x80000000, or is positive and equals 220 * 0x80000000, overflow; otherwise the last fraction word 221 * is the result. 222 */ 223 if ((exp = fp->fp_exp) >= 32) 224 break; 225 /* NB: the following includes exp < 0 cases */ 226 if (__fpu_shr(fp, FP_NMANT - 1 - exp) != 0) 227 fe->fe_cx |= FSR_NX; 228 i = fp->fp_mant[3]; 229 if (i >= ((u_int)0x80000000 + sign)) 230 break; 231 return (sign ? -i : i); 232 233 default: /* Inf, qNaN, sNaN */ 234 break; 235 } 236 /* overflow: replace any inexact exception with invalid */ 237 fe->fe_cx = (fe->fe_cx & ~FSR_NX) | FSR_NV; 238 return (0x7fffffff + sign); 239 } 240 241 /* 242 * fpn -> extended int (high bits of int value returned as return value). 243 * 244 * N.B.: this conversion always rounds towards zero (this is a peculiarity 245 * of the SPARC instruction set). 246 */ 247 u_int 248 __fpu_ftox(fe, fp, res) 249 struct fpemu *fe; 250 struct fpn *fp; 251 u_int *res; 252 { 253 u_int64_t i; 254 int sign, exp; 255 256 sign = fp->fp_sign; 257 switch (fp->fp_class) { 258 259 case FPC_ZERO: 260 res[1] = 0; 261 return (0); 262 263 case FPC_NUM: 264 /* 265 * If exp >= 2^64, overflow. Otherwise shift value right 266 * into last mantissa word (this will not exceed 267 * 0xffffffffffffffff), shifting any guard and round bits out 268 * into the sticky bit. Then ``round'' towards zero, i.e., 269 * just set an inexact exception if sticky is set (see round()). 270 * If the result is > 0x8000000000000000, or is positive and 271 * equals 0x8000000000000000, overflow; otherwise the 272 * last fraction word is the result. 273 */ 274 if ((exp = fp->fp_exp) >= 64) 275 break; 276 /* NB: the following includes exp < 0 cases */ 277 if (__fpu_shr(fp, FP_NMANT - 1 - exp) != 0) 278 fe->fe_cx |= FSR_NX; 279 i = ((u_int64_t)fp->fp_mant[2]<<32)|fp->fp_mant[3]; 280 if (i >= ((u_int64_t)0x8000000000000000LL + sign)) 281 break; 282 if (sign) 283 i = -i; 284 res[1] = (int)i; 285 return (i >> 32); 286 287 default: /* Inf, qNaN, sNaN */ 288 break; 289 } 290 /* overflow: replace any inexact exception with invalid */ 291 fe->fe_cx = (fe->fe_cx & ~FSR_NX) | FSR_NV; 292 return (0x7fffffffffffffffLL + sign); 293 } 294 295 /* 296 * fpn -> single (32 bit single returned as return value). 297 * We assume <= 29 bits in a single-precision fraction (1.f part). 298 */ 299 u_int 300 __fpu_ftos(fe, fp) 301 struct fpemu *fe; 302 struct fpn *fp; 303 { 304 u_int sign = fp->fp_sign << 31; 305 int exp; 306 307 #define SNG_EXP(e) ((e) << SNG_FRACBITS) /* makes e an exponent */ 308 #define SNG_MASK (SNG_EXP(1) - 1) /* mask for fraction */ 309 310 /* Take care of non-numbers first. */ 311 if (ISNAN(fp)) { 312 /* 313 * Preserve upper bits of NaN, per SPARC V8 appendix N. 314 * Note that fp->fp_mant[0] has the quiet bit set, 315 * even if it is classified as a signalling NaN. 316 */ 317 (void) __fpu_shr(fp, FP_NMANT - 1 - SNG_FRACBITS); 318 exp = SNG_EXP_INFNAN; 319 goto done; 320 } 321 if (ISINF(fp)) 322 return (sign | SNG_EXP(SNG_EXP_INFNAN)); 323 if (ISZERO(fp)) 324 return (sign); 325 326 /* 327 * Normals (including subnormals). Drop all the fraction bits 328 * (including the explicit ``implied'' 1 bit) down into the 329 * single-precision range. If the number is subnormal, move 330 * the ``implied'' 1 into the explicit range as well, and shift 331 * right to introduce leading zeroes. Rounding then acts 332 * differently for normals and subnormals: the largest subnormal 333 * may round to the smallest normal (1.0 x 2^minexp), or may 334 * remain subnormal. In the latter case, signal an underflow 335 * if the result was inexact or if underflow traps are enabled. 336 * 337 * Rounding a normal, on the other hand, always produces another 338 * normal (although either way the result might be too big for 339 * single precision, and cause an overflow). If rounding a 340 * normal produces 2.0 in the fraction, we need not adjust that 341 * fraction at all, since both 1.0 and 2.0 are zero under the 342 * fraction mask. 343 * 344 * Note that the guard and round bits vanish from the number after 345 * rounding. 346 */ 347 if ((exp = fp->fp_exp + SNG_EXP_BIAS) <= 0) { /* subnormal */ 348 /* -NG for g,r; -SNG_FRACBITS-exp for fraction */ 349 (void) __fpu_shr(fp, FP_NMANT - FP_NG - SNG_FRACBITS - exp); 350 if (round(fe, fp) && fp->fp_mant[3] == SNG_EXP(1)) 351 return (sign | SNG_EXP(1) | 0); 352 if ((fe->fe_cx & FSR_NX) || 353 (fe->fe_fsr & (FSR_UF << FSR_TEM_SHIFT))) 354 fe->fe_cx |= FSR_UF; 355 return (sign | SNG_EXP(0) | fp->fp_mant[3]); 356 } 357 /* -FP_NG for g,r; -1 for implied 1; -SNG_FRACBITS for fraction */ 358 (void) __fpu_shr(fp, FP_NMANT - FP_NG - 1 - SNG_FRACBITS); 359 #ifdef DIAGNOSTIC 360 if ((fp->fp_mant[3] & SNG_EXP(1 << FP_NG)) == 0) 361 __utrap_panic("fpu_ftos"); 362 #endif 363 if (round(fe, fp) && fp->fp_mant[3] == SNG_EXP(2)) 364 exp++; 365 if (exp >= SNG_EXP_INFNAN) { 366 /* overflow to inf or to max single */ 367 fe->fe_cx |= FSR_OF | FSR_NX; 368 if (toinf(fe, sign)) 369 return (sign | SNG_EXP(SNG_EXP_INFNAN)); 370 return (sign | SNG_EXP(SNG_EXP_INFNAN - 1) | SNG_MASK); 371 } 372 done: 373 /* phew, made it */ 374 return (sign | SNG_EXP(exp) | (fp->fp_mant[3] & SNG_MASK)); 375 } 376 377 /* 378 * fpn -> double (32 bit high-order result returned; 32-bit low order result 379 * left in res[1]). Assumes <= 61 bits in double precision fraction. 380 * 381 * This code mimics fpu_ftos; see it for comments. 382 */ 383 u_int 384 __fpu_ftod(fe, fp, res) 385 struct fpemu *fe; 386 struct fpn *fp; 387 u_int *res; 388 { 389 u_int sign = fp->fp_sign << 31; 390 int exp; 391 392 #define DBL_EXP(e) ((e) << (DBL_FRACBITS & 31)) 393 #define DBL_MASK (DBL_EXP(1) - 1) 394 395 if (ISNAN(fp)) { 396 (void) __fpu_shr(fp, FP_NMANT - 1 - DBL_FRACBITS); 397 exp = DBL_EXP_INFNAN; 398 goto done; 399 } 400 if (ISINF(fp)) { 401 sign |= DBL_EXP(DBL_EXP_INFNAN); 402 goto zero; 403 } 404 if (ISZERO(fp)) { 405 zero: res[1] = 0; 406 return (sign); 407 } 408 409 if ((exp = fp->fp_exp + DBL_EXP_BIAS) <= 0) { 410 (void) __fpu_shr(fp, FP_NMANT - FP_NG - DBL_FRACBITS - exp); 411 if (round(fe, fp) && fp->fp_mant[2] == DBL_EXP(1)) { 412 res[1] = 0; 413 return (sign | DBL_EXP(1) | 0); 414 } 415 if ((fe->fe_cx & FSR_NX) || 416 (fe->fe_fsr & (FSR_UF << FSR_TEM_SHIFT))) 417 fe->fe_cx |= FSR_UF; 418 exp = 0; 419 goto done; 420 } 421 (void) __fpu_shr(fp, FP_NMANT - FP_NG - 1 - DBL_FRACBITS); 422 if (round(fe, fp) && fp->fp_mant[2] == DBL_EXP(2)) 423 exp++; 424 if (exp >= DBL_EXP_INFNAN) { 425 fe->fe_cx |= FSR_OF | FSR_NX; 426 if (toinf(fe, sign)) { 427 res[1] = 0; 428 return (sign | DBL_EXP(DBL_EXP_INFNAN) | 0); 429 } 430 res[1] = ~0; 431 return (sign | DBL_EXP(DBL_EXP_INFNAN) | DBL_MASK); 432 } 433 done: 434 res[1] = fp->fp_mant[3]; 435 return (sign | DBL_EXP(exp) | (fp->fp_mant[2] & DBL_MASK)); 436 } 437 438 /* 439 * fpn -> extended (32 bit high-order result returned; low-order fraction 440 * words left in res[1]..res[3]). Like ftod, which is like ftos ... but 441 * our internal format *is* extended precision, plus 2 bits for guard/round, 442 * so we can avoid a small bit of work. 443 */ 444 u_int 445 __fpu_ftoq(fe, fp, res) 446 struct fpemu *fe; 447 struct fpn *fp; 448 u_int *res; 449 { 450 u_int sign = fp->fp_sign << 31; 451 int exp; 452 453 #define EXT_EXP(e) ((e) << (EXT_FRACBITS & 31)) 454 #define EXT_MASK (EXT_EXP(1) - 1) 455 456 if (ISNAN(fp)) { 457 (void) __fpu_shr(fp, 2); /* since we are not rounding */ 458 exp = EXT_EXP_INFNAN; 459 goto done; 460 } 461 if (ISINF(fp)) { 462 sign |= EXT_EXP(EXT_EXP_INFNAN); 463 goto zero; 464 } 465 if (ISZERO(fp)) { 466 zero: res[1] = res[2] = res[3] = 0; 467 return (sign); 468 } 469 470 if ((exp = fp->fp_exp + EXT_EXP_BIAS) <= 0) { 471 (void) __fpu_shr(fp, FP_NMANT - FP_NG - EXT_FRACBITS - exp); 472 if (round(fe, fp) && fp->fp_mant[0] == EXT_EXP(1)) { 473 res[1] = res[2] = res[3] = 0; 474 return (sign | EXT_EXP(1) | 0); 475 } 476 if ((fe->fe_cx & FSR_NX) || 477 (fe->fe_fsr & (FSR_UF << FSR_TEM_SHIFT))) 478 fe->fe_cx |= FSR_UF; 479 exp = 0; 480 goto done; 481 } 482 /* Since internal == extended, no need to shift here. */ 483 if (round(fe, fp) && fp->fp_mant[0] == EXT_EXP(2)) 484 exp++; 485 if (exp >= EXT_EXP_INFNAN) { 486 fe->fe_cx |= FSR_OF | FSR_NX; 487 if (toinf(fe, sign)) { 488 res[1] = res[2] = res[3] = 0; 489 return (sign | EXT_EXP(EXT_EXP_INFNAN) | 0); 490 } 491 res[1] = res[2] = res[3] = ~0; 492 return (sign | EXT_EXP(EXT_EXP_INFNAN) | EXT_MASK); 493 } 494 done: 495 res[1] = fp->fp_mant[1]; 496 res[2] = fp->fp_mant[2]; 497 res[3] = fp->fp_mant[3]; 498 return (sign | EXT_EXP(exp) | (fp->fp_mant[0] & EXT_MASK)); 499 } 500 501 /* 502 * Implode an fpn, writing the result into the given space. 503 */ 504 void 505 __fpu_implode(fe, fp, type, space) 506 struct fpemu *fe; 507 struct fpn *fp; 508 int type; 509 u_int *space; 510 { 511 512 switch (type) { 513 514 case FTYPE_LNG: 515 space[0] = __fpu_ftox(fe, fp, space); 516 break; 517 518 case FTYPE_INT: 519 space[0] = __fpu_ftoi(fe, fp); 520 break; 521 522 case FTYPE_SNG: 523 space[0] = __fpu_ftos(fe, fp); 524 break; 525 526 case FTYPE_DBL: 527 space[0] = __fpu_ftod(fe, fp, space); 528 break; 529 530 case FTYPE_EXT: 531 /* funky rounding precision options ?? */ 532 space[0] = __fpu_ftoq(fe, fp, space); 533 break; 534 535 #ifdef DIAGNOSTIC 536 default: 537 __utrap_panic("fpu_implode"); 538 #endif 539 } 540 DPRINTF(FPE_REG, ("fpu_implode: %x %x %x %x\n", 541 space[0], space[1], space[2], space[3])); 542 } 543