1 /* $OpenBSD: fpu_explode.c,v 1.1 2003/07/21 18:41:30 jason Exp $ */ 2 3 /* 4 * Copyright (c) 1992, 1993 5 * The Regents of the University of California. All rights reserved. 6 * 7 * This software was developed by the Computer Systems Engineering group 8 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 9 * contributed to Berkeley. 10 * 11 * All advertising materials mentioning features or use of this software 12 * must display the following acknowledgement: 13 * This product includes software developed by the University of 14 * California, Lawrence Berkeley Laboratory. 15 * 16 * Redistribution and use in source and binary forms, with or without 17 * modification, are permitted provided that the following conditions 18 * are met: 19 * 1. Redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer. 21 * 2. Redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution. 24 * 3. All advertising materials mentioning features or use of this software 25 * must display the following acknowledgement: 26 * This product includes software developed by the University of 27 * California, Berkeley and its contributors. 28 * 4. Neither the name of the University nor the names of its contributors 29 * may be used to endorse or promote products derived from this software 30 * without specific prior written permission. 31 * 32 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 33 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 34 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 35 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 36 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 37 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 38 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 39 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 40 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 41 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 42 * SUCH DAMAGE. 43 * 44 * @(#)fpu_explode.c 8.1 (Berkeley) 6/11/93 45 * $NetBSD: fpu_explode.c,v 1.5 2000/08/03 18:32:08 eeh Exp $ 46 */ 47 48 #include <sys/cdefs.h> 49 #if 0 50 __FBSDID("$FreeBSD: src/lib/libc/sparc64/fpu/fpu_explode.c,v 1.5 2002/05/11 21:20:04 jake Exp $"); 51 #endif 52 53 /* 54 * FPU subroutines: `explode' the machine's `packed binary' format numbers 55 * into our internal format. 56 */ 57 58 #include <sys/param.h> 59 60 #include <machine/frame.h> 61 #include <machine/fsr.h> 62 #include <machine/ieee.h> 63 #include <machine/instr.h> 64 65 #include "fpu_arith.h" 66 #include "fpu_emu.h" 67 #include "fpu_extern.h" 68 #include "fpu_reg.h" 69 70 /* 71 * N.B.: in all of the following, we assume the FP format is 72 * 73 * --------------------------- 74 * | s | exponent | fraction | 75 * --------------------------- 76 * 77 * (which represents -1**s * 1.fraction * 2**exponent), so that the 78 * sign bit is way at the top (bit 31), the exponent is next, and 79 * then the remaining bits mark the fraction. A zero exponent means 80 * zero or denormalized (0.fraction rather than 1.fraction), and the 81 * maximum possible exponent, 2bias+1, signals inf (fraction==0) or NaN. 82 * 83 * Since the sign bit is always the topmost bit---this holds even for 84 * integers---we set that outside all the *tof functions. Each function 85 * returns the class code for the new number (but note that we use 86 * FPC_QNAN for all NaNs; fpu_explode will fix this if appropriate). 87 */ 88 89 /* 90 * int -> fpn. 91 */ 92 int 93 __fpu_itof(fp, i) 94 struct fpn *fp; 95 u_int i; 96 { 97 98 if (i == 0) 99 return (FPC_ZERO); 100 /* 101 * The value FP_1 represents 2^FP_LG, so set the exponent 102 * there and let normalization fix it up. Convert negative 103 * numbers to sign-and-magnitude. Note that this relies on 104 * fpu_norm()'s handling of `supernormals'; see fpu_subr.c. 105 */ 106 fp->fp_exp = FP_LG; 107 fp->fp_mant[0] = (int)i < 0 ? -i : i; 108 fp->fp_mant[1] = 0; 109 fp->fp_mant[2] = 0; 110 fp->fp_mant[3] = 0; 111 __fpu_norm(fp); 112 return (FPC_NUM); 113 } 114 115 /* 116 * 64-bit int -> fpn. 117 */ 118 int 119 __fpu_xtof(fp, i) 120 struct fpn *fp; 121 u_int64_t i; 122 { 123 124 if (i == 0) 125 return (FPC_ZERO); 126 /* 127 * The value FP_1 represents 2^FP_LG, so set the exponent 128 * there and let normalization fix it up. Convert negative 129 * numbers to sign-and-magnitude. Note that this relies on 130 * fpu_norm()'s handling of `supernormals'; see fpu_subr.c. 131 */ 132 fp->fp_exp = FP_LG2; 133 *((int64_t*)fp->fp_mant) = (int64_t)i < 0 ? -i : i; 134 fp->fp_mant[2] = 0; 135 fp->fp_mant[3] = 0; 136 __fpu_norm(fp); 137 return (FPC_NUM); 138 } 139 140 #define mask(nbits) ((1L << (nbits)) - 1) 141 142 /* 143 * All external floating formats convert to internal in the same manner, 144 * as defined here. Note that only normals get an implied 1.0 inserted. 145 */ 146 #define FP_TOF(exp, expbias, allfrac, f0, f1, f2, f3) \ 147 if (exp == 0) { \ 148 if (allfrac == 0) \ 149 return (FPC_ZERO); \ 150 fp->fp_exp = 1 - expbias; \ 151 fp->fp_mant[0] = f0; \ 152 fp->fp_mant[1] = f1; \ 153 fp->fp_mant[2] = f2; \ 154 fp->fp_mant[3] = f3; \ 155 __fpu_norm(fp); \ 156 return (FPC_NUM); \ 157 } \ 158 if (exp == (2 * expbias + 1)) { \ 159 if (allfrac == 0) \ 160 return (FPC_INF); \ 161 fp->fp_mant[0] = f0; \ 162 fp->fp_mant[1] = f1; \ 163 fp->fp_mant[2] = f2; \ 164 fp->fp_mant[3] = f3; \ 165 return (FPC_QNAN); \ 166 } \ 167 fp->fp_exp = exp - expbias; \ 168 fp->fp_mant[0] = FP_1 | f0; \ 169 fp->fp_mant[1] = f1; \ 170 fp->fp_mant[2] = f2; \ 171 fp->fp_mant[3] = f3; \ 172 return (FPC_NUM) 173 174 /* 175 * 32-bit single precision -> fpn. 176 * We assume a single occupies at most (64-FP_LG) bits in the internal 177 * format: i.e., needs at most fp_mant[0] and fp_mant[1]. 178 */ 179 int 180 __fpu_stof(fp, i) 181 struct fpn *fp; 182 u_int i; 183 { 184 int exp; 185 u_int frac, f0, f1; 186 #define SNG_SHIFT (SNG_FRACBITS - FP_LG) 187 188 exp = (i >> (32 - 1 - SNG_EXPBITS)) & mask(SNG_EXPBITS); 189 frac = i & mask(SNG_FRACBITS); 190 f0 = frac >> SNG_SHIFT; 191 f1 = frac << (32 - SNG_SHIFT); 192 FP_TOF(exp, SNG_EXP_BIAS, frac, f0, f1, 0, 0); 193 } 194 195 /* 196 * 64-bit double -> fpn. 197 * We assume this uses at most (96-FP_LG) bits. 198 */ 199 int 200 __fpu_dtof(fp, i, j) 201 struct fpn *fp; 202 u_int i, j; 203 { 204 int exp; 205 u_int frac, f0, f1, f2; 206 #define DBL_SHIFT (DBL_FRACBITS - 32 - FP_LG) 207 208 exp = (i >> (32 - 1 - DBL_EXPBITS)) & mask(DBL_EXPBITS); 209 frac = i & mask(DBL_FRACBITS - 32); 210 f0 = frac >> DBL_SHIFT; 211 f1 = (frac << (32 - DBL_SHIFT)) | (j >> DBL_SHIFT); 212 f2 = j << (32 - DBL_SHIFT); 213 frac |= j; 214 FP_TOF(exp, DBL_EXP_BIAS, frac, f0, f1, f2, 0); 215 } 216 217 /* 218 * 128-bit extended -> fpn. 219 */ 220 int 221 __fpu_qtof(fp, i, j, k, l) 222 struct fpn *fp; 223 u_int i, j, k, l; 224 { 225 int exp; 226 u_int frac, f0, f1, f2, f3; 227 #define EXT_SHIFT (-(EXT_FRACBITS - 3 * 32 - FP_LG)) /* left shift! */ 228 229 /* 230 * Note that ext and fpn `line up', hence no shifting needed. 231 */ 232 exp = (i >> (32 - 1 - EXT_EXPBITS)) & mask(EXT_EXPBITS); 233 frac = i & mask(EXT_FRACBITS - 3 * 32); 234 f0 = (frac << EXT_SHIFT) | (j >> (32 - EXT_SHIFT)); 235 f1 = (j << EXT_SHIFT) | (k >> (32 - EXT_SHIFT)); 236 f2 = (k << EXT_SHIFT) | (l >> (32 - EXT_SHIFT)); 237 f3 = l << EXT_SHIFT; 238 frac |= j | k | l; 239 FP_TOF(exp, EXT_EXP_BIAS, frac, f0, f1, f2, f3); 240 } 241 242 /* 243 * Explode the contents of a / regpair / regquad. 244 * If the input is a signalling NaN, an NV (invalid) exception 245 * will be set. (Note that nothing but NV can occur until ALU 246 * operations are performed.) 247 */ 248 void 249 __fpu_explode(fe, fp, type, reg) 250 struct fpemu *fe; 251 struct fpn *fp; 252 int type, reg; 253 { 254 u_int32_t s = 0/* XXX gcc */, *sp; 255 u_int64_t l[2]; 256 257 if (type == FTYPE_LNG || type == FTYPE_DBL || type == FTYPE_EXT) { 258 l[0] = __fpu_getreg64(reg & ~1); 259 sp = (u_int32_t *)l; 260 fp->fp_sign = sp[0] >> 31; 261 fp->fp_sticky = 0; 262 switch (type) { 263 case FTYPE_LNG: 264 s = __fpu_xtof(fp, l[0]); 265 break; 266 case FTYPE_DBL: 267 s = __fpu_dtof(fp, sp[0], sp[1]); 268 break; 269 case FTYPE_EXT: 270 l[1] = __fpu_getreg64((reg & ~1) + 2); 271 s = __fpu_qtof(fp, sp[0], sp[1], sp[2], sp[3]); 272 break; 273 default: 274 #ifdef DIAGNOSTIC 275 __utrap_panic("fpu_explode"); 276 #endif 277 } 278 } else { 279 #ifdef DIAGNOSTIC 280 if (type != FTYPE_SNG) 281 __utrap_panic("fpu_explode"); 282 #endif 283 s = __fpu_getreg32(reg); 284 fp->fp_sign = s >> 31; 285 fp->fp_sticky = 0; 286 s = __fpu_stof(fp, s); 287 } 288 289 if (s == FPC_QNAN && (fp->fp_mant[0] & FP_QUIETBIT) == 0) { 290 /* 291 * Input is a signalling NaN. All operations that return 292 * an input NaN operand put it through a ``NaN conversion'', 293 * which basically just means ``turn on the quiet bit''. 294 * We do this here so that all NaNs internally look quiet 295 * (we can tell signalling ones by their class). 296 */ 297 fp->fp_mant[0] |= FP_QUIETBIT; 298 fe->fe_cx = FSR_NV; /* assert invalid operand */ 299 s = FPC_SNAN; 300 } 301 fp->fp_class = s; 302 DPRINTF(FPE_REG, ("fpu_explode: %%%c%d => ", (type == FTYPE_LNG) ? 'x' : 303 ((type == FTYPE_INT) ? 'i' : 304 ((type == FTYPE_SNG) ? 's' : 305 ((type == FTYPE_DBL) ? 'd' : 306 ((type == FTYPE_EXT) ? 'q' : '?')))), 307 reg)); 308 DUMPFPN(FPE_REG, fp); 309 DPRINTF(FPE_REG, ("\n")); 310 } 311