1*c87b03e5Sespie #ifndef __thumb__
2*c87b03e5Sespie /* There used to be a couple of bugs in the ARM's prologue and epilogue
3*c87b03e5Sespie generation for ISR routines. The wrong epilogue instruction would be
4*c87b03e5Sespie generated to restore the IP register if it had to be pushed onto the
5*c87b03e5Sespie stack, and the wrong offset was being computed for local variables if
6*c87b03e5Sespie r0 - r3 had to be saved. This tests for both of these cases. */
7*c87b03e5Sespie
8*c87b03e5Sespie int z = 9;
9*c87b03e5Sespie
10*c87b03e5Sespie int
bar(void)11*c87b03e5Sespie bar (void)
12*c87b03e5Sespie {
13*c87b03e5Sespie return z;
14*c87b03e5Sespie }
15*c87b03e5Sespie
16*c87b03e5Sespie int
foo(int a,int b,int c,int d,int e,int f,int g,int h)17*c87b03e5Sespie foo (int a, int b, int c, int d, int e, int f, int g, int h)
18*c87b03e5Sespie {
19*c87b03e5Sespie volatile int i = (a + b) - (g + h) + bar ();
20*c87b03e5Sespie volatile int j = (e + f) - (c + d);
21*c87b03e5Sespie
22*c87b03e5Sespie return a + b + c + d + e + f + g + h + i + j;
23*c87b03e5Sespie }
24*c87b03e5Sespie
25*c87b03e5Sespie int foo1 (int a, int b, int c, int d, int e, int f, int g, int h) __attribute__ ((interrupt ("IRQ")));
26*c87b03e5Sespie
27*c87b03e5Sespie int
foo1(int a,int b,int c,int d,int e,int f,int g,int h)28*c87b03e5Sespie foo1 (int a, int b, int c, int d, int e, int f, int g, int h)
29*c87b03e5Sespie {
30*c87b03e5Sespie volatile int i = (a + b) - (g + h) + bar ();
31*c87b03e5Sespie volatile int j = (e + f) - (c + d);
32*c87b03e5Sespie
33*c87b03e5Sespie return a + b + c + d + e + f + g + h + i + j;
34*c87b03e5Sespie }
35*c87b03e5Sespie #endif
36*c87b03e5Sespie
37*c87b03e5Sespie int
main(void)38*c87b03e5Sespie main (void)
39*c87b03e5Sespie {
40*c87b03e5Sespie #ifndef __thumb__
41*c87b03e5Sespie if (foo (1, 2, 3, 4, 5, 6, 7, 8) != 32)
42*c87b03e5Sespie abort ();
43*c87b03e5Sespie
44*c87b03e5Sespie if (foo1 (1, 2, 3, 4, 5, 6, 7, 8) != 32)
45*c87b03e5Sespie abort ();
46*c87b03e5Sespie #endif
47*c87b03e5Sespie exit (0);
48*c87b03e5Sespie }
49