1 /* Disassembly routines for TMS320C30 architecture 2 Copyright (C) 1998, 1999 Free Software Foundation, Inc. 3 Contributed by Steven Haworth (steve@pm.cse.rmit.edu.au) 4 5 This program is free software; you can redistribute it and/or modify 6 it under the terms of the GNU General Public License as published by 7 the Free Software Foundation; either version 2 of the License, or 8 (at your option) any later version. 9 10 This program is distributed in the hope that it will be useful, 11 but WITHOUT ANY WARRANTY; without even the implied warranty of 12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 GNU General Public License for more details. 14 15 You should have received a copy of the GNU General Public License 16 along with this program; if not, write to the Free Software 17 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 18 02111-1307, USA. */ 19 20 #include <errno.h> 21 #include <math.h> 22 #include "sysdep.h" 23 #include "dis-asm.h" 24 #include "opcode/tic30.h" 25 26 #define NORMAL_INSN 1 27 #define PARALLEL_INSN 2 28 29 /* Gets the type of instruction based on the top 2 or 3 bits of the 30 instruction word. */ 31 #define GET_TYPE(insn) (insn & 0x80000000 ? insn & 0xC0000000 : insn & 0xE0000000) 32 33 /* Instruction types. */ 34 #define TWO_OPERAND_1 0x00000000 35 #define TWO_OPERAND_2 0x40000000 36 #define THREE_OPERAND 0x20000000 37 #define PAR_STORE 0xC0000000 38 #define MUL_ADDS 0x80000000 39 #define BRANCHES 0x60000000 40 41 /* Specific instruction id bits. */ 42 #define NORMAL_IDEN 0x1F800000 43 #define PAR_STORE_IDEN 0x3E000000 44 #define MUL_ADD_IDEN 0x2C000000 45 #define BR_IMM_IDEN 0x1F000000 46 #define BR_COND_IDEN 0x1C3F0000 47 48 /* Addressing modes. */ 49 #define AM_REGISTER 0x00000000 50 #define AM_DIRECT 0x00200000 51 #define AM_INDIRECT 0x00400000 52 #define AM_IMM 0x00600000 53 54 #define P_FIELD 0x03000000 55 56 #define REG_AR0 0x08 57 #define LDP_INSN 0x08700000 58 59 /* TMS320C30 program counter for current instruction. */ 60 static unsigned int _pc; 61 62 struct instruction 63 { 64 int type; 65 template *tm; 66 partemplate *ptm; 67 }; 68 69 int get_tic30_instruction PARAMS ((unsigned long, struct instruction *)); 70 int print_two_operand 71 PARAMS ((disassemble_info *, unsigned long, struct instruction *)); 72 int print_three_operand 73 PARAMS ((disassemble_info *, unsigned long, struct instruction *)); 74 int print_par_insn 75 PARAMS ((disassemble_info *, unsigned long, struct instruction *)); 76 int print_branch 77 PARAMS ((disassemble_info *, unsigned long, struct instruction *)); 78 int get_indirect_operand PARAMS ((unsigned short, int, char *)); 79 int get_register_operand PARAMS ((unsigned char, char *)); 80 int cnvt_tmsfloat_ieee PARAMS ((unsigned long, int, float *)); 81 82 int 83 print_insn_tic30 (pc, info) 84 bfd_vma pc; 85 disassemble_info *info; 86 { 87 unsigned long insn_word; 88 struct instruction insn = 89 {0, NULL, NULL}; 90 bfd_vma bufaddr = pc - info->buffer_vma; 91 /* Obtain the current instruction word from the buffer. */ 92 insn_word = (*(info->buffer + bufaddr) << 24) | (*(info->buffer + bufaddr + 1) << 16) | 93 (*(info->buffer + bufaddr + 2) << 8) | *(info->buffer + bufaddr + 3); 94 _pc = pc / 4; 95 /* Get the instruction refered to by the current instruction word 96 and print it out based on its type. */ 97 if (!get_tic30_instruction (insn_word, &insn)) 98 return -1; 99 switch (GET_TYPE (insn_word)) 100 { 101 case TWO_OPERAND_1: 102 case TWO_OPERAND_2: 103 if (!print_two_operand (info, insn_word, &insn)) 104 return -1; 105 break; 106 case THREE_OPERAND: 107 if (!print_three_operand (info, insn_word, &insn)) 108 return -1; 109 break; 110 case PAR_STORE: 111 case MUL_ADDS: 112 if (!print_par_insn (info, insn_word, &insn)) 113 return -1; 114 break; 115 case BRANCHES: 116 if (!print_branch (info, insn_word, &insn)) 117 return -1; 118 break; 119 } 120 return 4; 121 } 122 123 int 124 get_tic30_instruction (insn_word, insn) 125 unsigned long insn_word; 126 struct instruction *insn; 127 { 128 switch (GET_TYPE (insn_word)) 129 { 130 case TWO_OPERAND_1: 131 case TWO_OPERAND_2: 132 case THREE_OPERAND: 133 insn->type = NORMAL_INSN; 134 { 135 template *current_optab = (template *) tic30_optab; 136 for (; current_optab < tic30_optab_end; current_optab++) 137 { 138 if (GET_TYPE (current_optab->base_opcode) == GET_TYPE (insn_word)) 139 { 140 if (current_optab->operands == 0) 141 { 142 if (current_optab->base_opcode == insn_word) 143 { 144 insn->tm = current_optab; 145 break; 146 } 147 } 148 else if ((current_optab->base_opcode & NORMAL_IDEN) == (insn_word & NORMAL_IDEN)) 149 { 150 insn->tm = current_optab; 151 break; 152 } 153 } 154 } 155 } 156 break; 157 case PAR_STORE: 158 insn->type = PARALLEL_INSN; 159 { 160 partemplate *current_optab = (partemplate *) tic30_paroptab; 161 for (; current_optab < tic30_paroptab_end; current_optab++) 162 { 163 if (GET_TYPE (current_optab->base_opcode) == GET_TYPE (insn_word)) 164 { 165 if ((current_optab->base_opcode & PAR_STORE_IDEN) == (insn_word & PAR_STORE_IDEN)) 166 { 167 insn->ptm = current_optab; 168 break; 169 } 170 } 171 } 172 } 173 break; 174 case MUL_ADDS: 175 insn->type = PARALLEL_INSN; 176 { 177 partemplate *current_optab = (partemplate *) tic30_paroptab; 178 for (; current_optab < tic30_paroptab_end; current_optab++) 179 { 180 if (GET_TYPE (current_optab->base_opcode) == GET_TYPE (insn_word)) 181 { 182 if ((current_optab->base_opcode & MUL_ADD_IDEN) == (insn_word & MUL_ADD_IDEN)) 183 { 184 insn->ptm = current_optab; 185 break; 186 } 187 } 188 } 189 } 190 break; 191 case BRANCHES: 192 insn->type = NORMAL_INSN; 193 { 194 template *current_optab = (template *) tic30_optab; 195 for (; current_optab < tic30_optab_end; current_optab++) 196 { 197 if (GET_TYPE (current_optab->base_opcode) == GET_TYPE (insn_word)) 198 { 199 if (current_optab->operand_types[0] & Imm24) 200 { 201 if ((current_optab->base_opcode & BR_IMM_IDEN) == (insn_word & BR_IMM_IDEN)) 202 { 203 insn->tm = current_optab; 204 break; 205 } 206 } 207 else if (current_optab->operands > 0) 208 { 209 if ((current_optab->base_opcode & BR_COND_IDEN) == (insn_word & BR_COND_IDEN)) 210 { 211 insn->tm = current_optab; 212 break; 213 } 214 } 215 else 216 { 217 if ((current_optab->base_opcode & (BR_COND_IDEN | 0x00800000)) == (insn_word & (BR_COND_IDEN | 0x00800000))) 218 { 219 insn->tm = current_optab; 220 break; 221 } 222 } 223 } 224 } 225 } 226 break; 227 default: 228 return 0; 229 } 230 return 1; 231 } 232 233 int 234 print_two_operand (info, insn_word, insn) 235 disassemble_info *info; 236 unsigned long insn_word; 237 struct instruction *insn; 238 { 239 char name[12]; 240 char operand[2][13] = 241 { 242 {0}, 243 {0}}; 244 float f_number; 245 246 if (insn->tm == NULL) 247 return 0; 248 strcpy (name, insn->tm->name); 249 if (insn->tm->opcode_modifier == AddressMode) 250 { 251 int src_op, dest_op; 252 /* Determine whether instruction is a store or a normal instruction. */ 253 if ((insn->tm->operand_types[1] & (Direct | Indirect)) == (Direct | Indirect)) 254 { 255 src_op = 1; 256 dest_op = 0; 257 } 258 else 259 { 260 src_op = 0; 261 dest_op = 1; 262 } 263 /* Get the destination register. */ 264 if (insn->tm->operands == 2) 265 get_register_operand ((insn_word & 0x001F0000) >> 16, operand[dest_op]); 266 /* Get the source operand based on addressing mode. */ 267 switch (insn_word & AddressMode) 268 { 269 case AM_REGISTER: 270 /* Check for the NOP instruction before getting the operand. */ 271 if ((insn->tm->operand_types[0] & NotReq) == 0) 272 get_register_operand ((insn_word & 0x0000001F), operand[src_op]); 273 break; 274 case AM_DIRECT: 275 sprintf (operand[src_op], "@0x%lX", (insn_word & 0x0000FFFF)); 276 break; 277 case AM_INDIRECT: 278 get_indirect_operand ((insn_word & 0x0000FFFF), 2, operand[src_op]); 279 break; 280 case AM_IMM: 281 /* Get the value of the immediate operand based on variable type. */ 282 switch (insn->tm->imm_arg_type) 283 { 284 case Imm_Float: 285 cnvt_tmsfloat_ieee ((insn_word & 0x0000FFFF), 2, &f_number); 286 sprintf (operand[src_op], "%2.2f", f_number); 287 break; 288 case Imm_SInt: 289 sprintf (operand[src_op], "%d", (short) (insn_word & 0x0000FFFF)); 290 break; 291 case Imm_UInt: 292 sprintf (operand[src_op], "%lu", (insn_word & 0x0000FFFF)); 293 break; 294 default: 295 return 0; 296 } 297 /* Handle special case for LDP instruction. */ 298 if ((insn_word & 0xFFFFFF00) == LDP_INSN) 299 { 300 strcpy (name, "ldp"); 301 sprintf (operand[0], "0x%06lX", (insn_word & 0x000000FF) << 16); 302 operand[1][0] = '\0'; 303 } 304 } 305 } 306 /* Handle case for stack and rotate instructions. */ 307 else if (insn->tm->operands == 1) 308 { 309 if (insn->tm->opcode_modifier == StackOp) 310 { 311 get_register_operand ((insn_word & 0x001F0000) >> 16, operand[0]); 312 } 313 } 314 /* Output instruction to stream. */ 315 info->fprintf_func (info->stream, " %s %s%c%s", name, 316 operand[0][0] ? operand[0] : "", 317 operand[1][0] ? ',' : ' ', 318 operand[1][0] ? operand[1] : ""); 319 return 1; 320 } 321 322 int 323 print_three_operand (info, insn_word, insn) 324 disassemble_info *info; 325 unsigned long insn_word; 326 struct instruction *insn; 327 { 328 char operand[3][13] = 329 { 330 {0}, 331 {0}, 332 {0}}; 333 334 if (insn->tm == NULL) 335 return 0; 336 switch (insn_word & AddressMode) 337 { 338 case AM_REGISTER: 339 get_register_operand ((insn_word & 0x000000FF), operand[0]); 340 get_register_operand ((insn_word & 0x0000FF00) >> 8, operand[1]); 341 break; 342 case AM_DIRECT: 343 get_register_operand ((insn_word & 0x000000FF), operand[0]); 344 get_indirect_operand ((insn_word & 0x0000FF00) >> 8, 1, operand[1]); 345 break; 346 case AM_INDIRECT: 347 get_indirect_operand ((insn_word & 0x000000FF), 1, operand[0]); 348 get_register_operand ((insn_word & 0x0000FF00) >> 8, operand[1]); 349 break; 350 case AM_IMM: 351 get_indirect_operand ((insn_word & 0x000000FF), 1, operand[0]); 352 get_indirect_operand ((insn_word & 0x0000FF00) >> 8, 1, operand[1]); 353 break; 354 default: 355 return 0; 356 } 357 if (insn->tm->operands == 3) 358 get_register_operand ((insn_word & 0x001F0000) >> 16, operand[2]); 359 info->fprintf_func (info->stream, " %s %s,%s%c%s", insn->tm->name, 360 operand[0], operand[1], 361 operand[2][0] ? ',' : ' ', 362 operand[2][0] ? operand[2] : ""); 363 return 1; 364 } 365 366 int 367 print_par_insn (info, insn_word, insn) 368 disassemble_info *info; 369 unsigned long insn_word; 370 struct instruction *insn; 371 { 372 size_t i, len; 373 char *name1, *name2; 374 char operand[2][3][13] = 375 { 376 { 377 {0}, 378 {0}, 379 {0}}, 380 { 381 {0}, 382 {0}, 383 {0}}}; 384 385 if (insn->ptm == NULL) 386 return 0; 387 /* Parse out the names of each of the parallel instructions from the 388 q_insn1_insn2 format. */ 389 name1 = (char *) strdup (insn->ptm->name + 2); 390 name2 = ""; 391 len = strlen (name1); 392 for (i = 0; i < len; i++) 393 { 394 if (name1[i] == '_') 395 { 396 name2 = &name1[i + 1]; 397 name1[i] = '\0'; 398 break; 399 } 400 } 401 /* Get the operands of the instruction based on the operand order. */ 402 switch (insn->ptm->oporder) 403 { 404 case OO_4op1: 405 get_indirect_operand ((insn_word & 0x000000FF), 1, operand[0][0]); 406 get_indirect_operand ((insn_word & 0x0000FF00) >> 8, 1, operand[1][1]); 407 get_register_operand ((insn_word >> 16) & 0x07, operand[1][0]); 408 get_register_operand ((insn_word >> 22) & 0x07, operand[0][1]); 409 break; 410 case OO_4op2: 411 get_indirect_operand ((insn_word & 0x000000FF), 1, operand[0][0]); 412 get_indirect_operand ((insn_word & 0x0000FF00) >> 8, 1, operand[1][0]); 413 get_register_operand ((insn_word >> 19) & 0x07, operand[1][1]); 414 get_register_operand ((insn_word >> 22) & 0x07, operand[0][1]); 415 break; 416 case OO_4op3: 417 get_indirect_operand ((insn_word & 0x000000FF), 1, operand[0][1]); 418 get_indirect_operand ((insn_word & 0x0000FF00) >> 8, 1, operand[1][1]); 419 get_register_operand ((insn_word >> 16) & 0x07, operand[1][0]); 420 get_register_operand ((insn_word >> 22) & 0x07, operand[0][0]); 421 break; 422 case OO_5op1: 423 get_indirect_operand ((insn_word & 0x000000FF), 1, operand[0][0]); 424 get_indirect_operand ((insn_word & 0x0000FF00) >> 8, 1, operand[1][1]); 425 get_register_operand ((insn_word >> 16) & 0x07, operand[1][0]); 426 get_register_operand ((insn_word >> 19) & 0x07, operand[0][1]); 427 get_register_operand ((insn_word >> 22) & 0x07, operand[0][2]); 428 break; 429 case OO_5op2: 430 get_indirect_operand ((insn_word & 0x000000FF), 1, operand[0][1]); 431 get_indirect_operand ((insn_word & 0x0000FF00) >> 8, 1, operand[1][1]); 432 get_register_operand ((insn_word >> 16) & 0x07, operand[1][0]); 433 get_register_operand ((insn_word >> 19) & 0x07, operand[0][0]); 434 get_register_operand ((insn_word >> 22) & 0x07, operand[0][2]); 435 break; 436 case OO_PField: 437 if (insn_word & 0x00800000) 438 get_register_operand (0x01, operand[0][2]); 439 else 440 get_register_operand (0x00, operand[0][2]); 441 if (insn_word & 0x00400000) 442 get_register_operand (0x03, operand[1][2]); 443 else 444 get_register_operand (0x02, operand[1][2]); 445 switch (insn_word & P_FIELD) 446 { 447 case 0x00000000: 448 get_indirect_operand ((insn_word & 0x000000FF), 1, operand[0][1]); 449 get_indirect_operand ((insn_word & 0x0000FF00) >> 8, 1, operand[0][0]); 450 get_register_operand ((insn_word >> 16) & 0x07, operand[1][1]); 451 get_register_operand ((insn_word >> 19) & 0x07, operand[1][0]); 452 break; 453 case 0x01000000: 454 get_indirect_operand ((insn_word & 0x000000FF), 1, operand[1][0]); 455 get_indirect_operand ((insn_word & 0x0000FF00) >> 8, 1, operand[0][0]); 456 get_register_operand ((insn_word >> 16) & 0x07, operand[1][1]); 457 get_register_operand ((insn_word >> 19) & 0x07, operand[0][1]); 458 break; 459 case 0x02000000: 460 get_indirect_operand ((insn_word & 0x000000FF), 1, operand[1][1]); 461 get_indirect_operand ((insn_word & 0x0000FF00) >> 8, 1, operand[1][0]); 462 get_register_operand ((insn_word >> 16) & 0x07, operand[0][1]); 463 get_register_operand ((insn_word >> 19) & 0x07, operand[0][0]); 464 break; 465 case 0x03000000: 466 get_indirect_operand ((insn_word & 0x000000FF), 1, operand[1][1]); 467 get_indirect_operand ((insn_word & 0x0000FF00) >> 8, 1, operand[0][0]); 468 get_register_operand ((insn_word >> 16) & 0x07, operand[1][0]); 469 get_register_operand ((insn_word >> 19) & 0x07, operand[0][1]); 470 break; 471 } 472 break; 473 default: 474 return 0; 475 } 476 info->fprintf_func (info->stream, " %s %s,%s%c%s", name1, 477 operand[0][0], operand[0][1], 478 operand[0][2][0] ? ',' : ' ', 479 operand[0][2][0] ? operand[0][2] : ""); 480 info->fprintf_func (info->stream, "\n\t\t\t|| %s %s,%s%c%s", name2, 481 operand[1][0], operand[1][1], 482 operand[1][2][0] ? ',' : ' ', 483 operand[1][2][0] ? operand[1][2] : ""); 484 free (name1); 485 return 1; 486 } 487 488 int 489 print_branch (info, insn_word, insn) 490 disassemble_info *info; 491 unsigned long insn_word; 492 struct instruction *insn; 493 { 494 char operand[2][13] = 495 { 496 {0}, 497 {0}}; 498 unsigned long address; 499 int print_label = 0; 500 501 if (insn->tm == NULL) 502 return 0; 503 /* Get the operands for 24-bit immediate jumps. */ 504 if (insn->tm->operand_types[0] & Imm24) 505 { 506 address = insn_word & 0x00FFFFFF; 507 sprintf (operand[0], "0x%lX", address); 508 print_label = 1; 509 } 510 /* Get the operand for the trap instruction. */ 511 else if (insn->tm->operand_types[0] & IVector) 512 { 513 address = insn_word & 0x0000001F; 514 sprintf (operand[0], "0x%lX", address); 515 } 516 else 517 { 518 address = insn_word & 0x0000FFFF; 519 /* Get the operands for the DB instructions. */ 520 if (insn->tm->operands == 2) 521 { 522 get_register_operand (((insn_word & 0x01C00000) >> 22) + REG_AR0, operand[0]); 523 if (insn_word & PCRel) 524 { 525 sprintf (operand[1], "%d", (short) address); 526 print_label = 1; 527 } 528 else 529 get_register_operand (insn_word & 0x0000001F, operand[1]); 530 } 531 /* Get the operands for the standard branches. */ 532 else if (insn->tm->operands == 1) 533 { 534 if (insn_word & PCRel) 535 { 536 address = (short) address; 537 sprintf (operand[0], "%ld", address); 538 print_label = 1; 539 } 540 else 541 get_register_operand (insn_word & 0x0000001F, operand[0]); 542 } 543 } 544 info->fprintf_func (info->stream, " %s %s%c%s", insn->tm->name, 545 operand[0][0] ? operand[0] : "", 546 operand[1][0] ? ',' : ' ', 547 operand[1][0] ? operand[1] : ""); 548 /* Print destination of branch in relation to current symbol. */ 549 if (print_label && info->symbols) 550 { 551 asymbol *sym = *info->symbols; 552 553 if ((insn->tm->opcode_modifier == PCRel) && (insn_word & PCRel)) 554 { 555 address = (_pc + 1 + (short) address) - ((sym->section->vma + sym->value) / 4); 556 /* Check for delayed instruction, if so adjust destination. */ 557 if (insn_word & 0x00200000) 558 address += 2; 559 } 560 else 561 { 562 address -= ((sym->section->vma + sym->value) / 4); 563 } 564 if (address == 0) 565 info->fprintf_func (info->stream, " <%s>", sym->name); 566 else 567 info->fprintf_func (info->stream, " <%s %c %d>", sym->name, 568 ((short) address < 0) ? '-' : '+', 569 abs (address)); 570 } 571 return 1; 572 } 573 574 int 575 get_indirect_operand (fragment, size, buffer) 576 unsigned short fragment; 577 int size; 578 char *buffer; 579 { 580 unsigned char mod; 581 unsigned arnum; 582 unsigned char disp; 583 584 if (buffer == NULL) 585 return 0; 586 /* Determine which bits identify the sections of the indirect operand based on the 587 size in bytes. */ 588 switch (size) 589 { 590 case 1: 591 mod = (fragment & 0x00F8) >> 3; 592 arnum = (fragment & 0x0007); 593 disp = 0; 594 break; 595 case 2: 596 mod = (fragment & 0xF800) >> 11; 597 arnum = (fragment & 0x0700) >> 8; 598 disp = (fragment & 0x00FF); 599 break; 600 default: 601 return 0; 602 } 603 { 604 const ind_addr_type *current_ind = tic30_indaddr_tab; 605 for (; current_ind < tic30_indaddrtab_end; current_ind++) 606 { 607 if (current_ind->modfield == mod) 608 { 609 if (current_ind->displacement == IMPLIED_DISP && size == 2) 610 { 611 continue; 612 } 613 else 614 { 615 size_t i, len; 616 int bufcnt; 617 618 len = strlen (current_ind->syntax); 619 for (i = 0, bufcnt = 0; i < len; i++, bufcnt++) 620 { 621 buffer[bufcnt] = current_ind->syntax[i]; 622 if (buffer[bufcnt - 1] == 'a' && buffer[bufcnt] == 'r') 623 buffer[++bufcnt] = arnum + '0'; 624 if (buffer[bufcnt] == '(' && current_ind->displacement == DISP_REQUIRED) 625 { 626 sprintf (&buffer[bufcnt + 1], "%u", disp); 627 bufcnt += strlen (&buffer[bufcnt + 1]); 628 } 629 } 630 buffer[bufcnt + 1] = '\0'; 631 break; 632 } 633 } 634 } 635 } 636 return 1; 637 } 638 639 int 640 get_register_operand (fragment, buffer) 641 unsigned char fragment; 642 char *buffer; 643 { 644 const reg *current_reg = tic30_regtab; 645 646 if (buffer == NULL) 647 return 0; 648 for (; current_reg < tic30_regtab_end; current_reg++) 649 { 650 if ((fragment & 0x1F) == current_reg->opcode) 651 { 652 strcpy (buffer, current_reg->name); 653 return 1; 654 } 655 } 656 return 0; 657 } 658 659 int 660 cnvt_tmsfloat_ieee (tmsfloat, size, ieeefloat) 661 unsigned long tmsfloat; 662 int size; 663 float *ieeefloat; 664 { 665 unsigned long exp, sign, mant; 666 667 if (size == 2) 668 { 669 if ((tmsfloat & 0x0000F000) == 0x00008000) 670 tmsfloat = 0x80000000; 671 else 672 { 673 tmsfloat <<= 16; 674 tmsfloat = (long) tmsfloat >> 4; 675 } 676 } 677 exp = tmsfloat & 0xFF000000; 678 if (exp == 0x80000000) 679 { 680 *ieeefloat = 0.0; 681 return 1; 682 } 683 exp += 0x7F000000; 684 sign = (tmsfloat & 0x00800000) << 8; 685 mant = tmsfloat & 0x007FFFFF; 686 if (exp == 0xFF000000) 687 { 688 if (mant == 0) 689 *ieeefloat = ERANGE; 690 if (sign == 0) 691 *ieeefloat = 1.0 / 0.0; 692 else 693 *ieeefloat = -1.0 / 0.0; 694 return 1; 695 } 696 exp >>= 1; 697 if (sign) 698 { 699 mant = (~mant) & 0x007FFFFF; 700 mant += 1; 701 exp += mant & 0x00800000; 702 exp &= 0x7F800000; 703 mant &= 0x007FFFFF; 704 } 705 if (tmsfloat == 0x80000000) 706 sign = mant = exp = 0; 707 tmsfloat = sign | exp | mant; 708 *ieeefloat = *((float *) &tmsfloat); 709 return 1; 710 } 711