1 /* Print SPARC instructions. 2 Copyright (C) 1989, 91-97, 1998 Free Software Foundation, Inc. 3 4 This program is free software; you can redistribute it and/or modify 5 it under the terms of the GNU General Public License as published by 6 the Free Software Foundation; either version 2 of the License, or 7 (at your option) any later version. 8 9 This program is distributed in the hope that it will be useful, 10 but WITHOUT ANY WARRANTY; without even the implied warranty of 11 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 GNU General Public License for more details. 13 14 You should have received a copy of the GNU General Public License 15 along with this program; if not, write to the Free Software 16 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ 17 18 #include <stdio.h> 19 20 #include "sysdep.h" 21 #include "opcode/sparc.h" 22 #include "dis-asm.h" 23 #include "libiberty.h" 24 #include "opintl.h" 25 26 /* Bitmask of v9 architectures. */ 27 #define MASK_V9 ((1 << SPARC_OPCODE_ARCH_V9) \ 28 | (1 << SPARC_OPCODE_ARCH_V9A)) 29 /* 1 if INSN is for v9 only. */ 30 #define V9_ONLY_P(insn) (! ((insn)->architecture & ~MASK_V9)) 31 /* 1 if INSN is for v9. */ 32 #define V9_P(insn) (((insn)->architecture & MASK_V9) != 0) 33 34 /* The sorted opcode table. */ 35 static const struct sparc_opcode **sorted_opcodes; 36 37 /* For faster lookup, after insns are sorted they are hashed. */ 38 /* ??? I think there is room for even more improvement. */ 39 40 #define HASH_SIZE 256 41 /* It is important that we only look at insn code bits as that is how the 42 opcode table is hashed. OPCODE_BITS is a table of valid bits for each 43 of the main types (0,1,2,3). */ 44 static int opcode_bits[4] = { 0x01c00000, 0x0, 0x01f80000, 0x01f80000 }; 45 #define HASH_INSN(INSN) \ 46 ((((INSN) >> 24) & 0xc0) | (((INSN) & opcode_bits[((INSN) >> 30) & 3]) >> 19)) 47 struct opcode_hash { 48 struct opcode_hash *next; 49 const struct sparc_opcode *opcode; 50 }; 51 static struct opcode_hash *opcode_hash_table[HASH_SIZE]; 52 53 static void build_hash_table 54 PARAMS ((const struct sparc_opcode **, struct opcode_hash **, int)); 55 static int is_delayed_branch PARAMS ((unsigned long)); 56 static int compare_opcodes PARAMS ((const PTR, const PTR)); 57 static int compute_arch_mask PARAMS ((unsigned long)); 58 59 /* Sign-extend a value which is N bits long. */ 60 #define SEX(value, bits) \ 61 ((((int)(value)) << ((8 * sizeof (int)) - bits)) \ 62 >> ((8 * sizeof (int)) - bits) ) 63 64 static char *reg_names[] = 65 { "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7", 66 "o0", "o1", "o2", "o3", "o4", "o5", "sp", "o7", 67 "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7", 68 "i0", "i1", "i2", "i3", "i4", "i5", "fp", "i7", 69 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", 70 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", 71 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", 72 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", 73 "f32", "f33", "f34", "f35", "f36", "f37", "f38", "f39", 74 "f40", "f41", "f42", "f43", "f44", "f45", "f46", "f47", 75 "f48", "f49", "f50", "f51", "f52", "f53", "f54", "f55", 76 "f56", "f57", "f58", "f59", "f60", "f61", "f62", "f63", 77 /* psr, wim, tbr, fpsr, cpsr are v8 only. */ 78 "y", "psr", "wim", "tbr", "pc", "npc", "fpsr", "cpsr" 79 }; 80 81 #define freg_names (®_names[4 * 8]) 82 83 /* These are ordered according to there register number in 84 rdpr and wrpr insns. */ 85 static char *v9_priv_reg_names[] = 86 { 87 "tpc", "tnpc", "tstate", "tt", "tick", "tba", "pstate", "tl", 88 "pil", "cwp", "cansave", "canrestore", "cleanwin", "otherwin", 89 "wstate", "fq" 90 /* "ver" - special cased */ 91 }; 92 93 /* These are ordered according to there register number in 94 rd and wr insns (-16). */ 95 static char *v9a_asr_reg_names[] = 96 { 97 "pcr", "pic", "dcr", "gsr", "set_softint", "clear_softint", 98 "softint", "tick_cmpr" 99 }; 100 101 /* Macros used to extract instruction fields. Not all fields have 102 macros defined here, only those which are actually used. */ 103 104 #define X_RD(i) (((i) >> 25) & 0x1f) 105 #define X_RS1(i) (((i) >> 14) & 0x1f) 106 #define X_LDST_I(i) (((i) >> 13) & 1) 107 #define X_ASI(i) (((i) >> 5) & 0xff) 108 #define X_RS2(i) (((i) >> 0) & 0x1f) 109 #define X_IMM(i,n) (((i) >> 0) & ((1 << (n)) - 1)) 110 #define X_SIMM(i,n) SEX (X_IMM ((i), (n)), (n)) 111 #define X_DISP22(i) (((i) >> 0) & 0x3fffff) 112 #define X_IMM22(i) X_DISP22 (i) 113 #define X_DISP30(i) (((i) >> 0) & 0x3fffffff) 114 115 /* These are for v9. */ 116 #define X_DISP16(i) (((((i) >> 20) & 3) << 14) | (((i) >> 0) & 0x3fff)) 117 #define X_DISP19(i) (((i) >> 0) & 0x7ffff) 118 #define X_MEMBAR(i) ((i) & 0x7f) 119 120 /* Here is the union which was used to extract instruction fields 121 before the shift and mask macros were written. 122 123 union sparc_insn 124 { 125 unsigned long int code; 126 struct 127 { 128 unsigned int anop:2; 129 #define op ldst.anop 130 unsigned int anrd:5; 131 #define rd ldst.anrd 132 unsigned int op3:6; 133 unsigned int anrs1:5; 134 #define rs1 ldst.anrs1 135 unsigned int i:1; 136 unsigned int anasi:8; 137 #define asi ldst.anasi 138 unsigned int anrs2:5; 139 #define rs2 ldst.anrs2 140 #define shcnt rs2 141 } ldst; 142 struct 143 { 144 unsigned int anop:2, anrd:5, op3:6, anrs1:5, i:1; 145 unsigned int IMM13:13; 146 #define imm13 IMM13.IMM13 147 } IMM13; 148 struct 149 { 150 unsigned int anop:2; 151 unsigned int a:1; 152 unsigned int cond:4; 153 unsigned int op2:3; 154 unsigned int DISP22:22; 155 #define disp22 branch.DISP22 156 #define imm22 disp22 157 } branch; 158 struct 159 { 160 unsigned int anop:2; 161 unsigned int a:1; 162 unsigned int z:1; 163 unsigned int rcond:3; 164 unsigned int op2:3; 165 unsigned int DISP16HI:2; 166 unsigned int p:1; 167 unsigned int _rs1:5; 168 unsigned int DISP16LO:14; 169 } branch16; 170 struct 171 { 172 unsigned int anop:2; 173 unsigned int adisp30:30; 174 #define disp30 call.adisp30 175 } call; 176 }; 177 178 */ 179 180 /* Nonzero if INSN is the opcode for a delayed branch. */ 181 static int 182 is_delayed_branch (insn) 183 unsigned long insn; 184 { 185 struct opcode_hash *op; 186 187 for (op = opcode_hash_table[HASH_INSN (insn)]; op; op = op->next) 188 { 189 CONST struct sparc_opcode *opcode = op->opcode; 190 if ((opcode->match & insn) == opcode->match 191 && (opcode->lose & insn) == 0) 192 return (opcode->flags & F_DELAYED); 193 } 194 return 0; 195 } 196 197 /* extern void qsort (); */ 198 199 /* Records current mask of SPARC_OPCODE_ARCH_FOO values, used to pass value 200 to compare_opcodes. */ 201 static unsigned int current_arch_mask; 202 203 /* Print one instruction from MEMADDR on INFO->STREAM. 204 205 We suffix the instruction with a comment that gives the absolute 206 address involved, as well as its symbolic form, if the instruction 207 is preceded by a findable `sethi' and it either adds an immediate 208 displacement to that register, or it is an `add' or `or' instruction 209 on that register. */ 210 211 int 212 print_insn_sparc (memaddr, info) 213 bfd_vma memaddr; 214 disassemble_info *info; 215 { 216 FILE *stream = info->stream; 217 bfd_byte buffer[4]; 218 unsigned long insn; 219 register struct opcode_hash *op; 220 /* Nonzero of opcode table has been initialized. */ 221 static int opcodes_initialized = 0; 222 /* bfd mach number of last call. */ 223 static unsigned long current_mach = 0; 224 bfd_vma (*getword) PARAMS ((const unsigned char *)); 225 226 if (!opcodes_initialized 227 || info->mach != current_mach) 228 { 229 int i; 230 231 current_arch_mask = compute_arch_mask (info->mach); 232 233 if (!opcodes_initialized) 234 sorted_opcodes = (const struct sparc_opcode **) 235 xmalloc (sparc_num_opcodes * sizeof (struct sparc_opcode *)); 236 /* Reset the sorted table so we can resort it. */ 237 for (i = 0; i < sparc_num_opcodes; ++i) 238 sorted_opcodes[i] = &sparc_opcodes[i]; 239 qsort ((char *) sorted_opcodes, sparc_num_opcodes, 240 sizeof (sorted_opcodes[0]), compare_opcodes); 241 242 build_hash_table (sorted_opcodes, opcode_hash_table, sparc_num_opcodes); 243 current_mach = info->mach; 244 opcodes_initialized = 1; 245 } 246 247 { 248 int status = 249 (*info->read_memory_func) (memaddr, buffer, sizeof (buffer), info); 250 if (status != 0) 251 { 252 (*info->memory_error_func) (status, memaddr, info); 253 return -1; 254 } 255 } 256 257 /* On SPARClite variants such as DANlite (sparc86x), instructions 258 are always big-endian even when the machine is in little-endian mode. */ 259 if (info->endian == BFD_ENDIAN_BIG || info->mach == bfd_mach_sparc_sparclite) 260 getword = bfd_getb32; 261 else 262 getword = bfd_getl32; 263 264 insn = getword (buffer); 265 266 info->insn_info_valid = 1; /* We do return this info */ 267 info->insn_type = dis_nonbranch; /* Assume non branch insn */ 268 info->branch_delay_insns = 0; /* Assume no delay */ 269 info->target = 0; /* Assume no target known */ 270 271 for (op = opcode_hash_table[HASH_INSN (insn)]; op; op = op->next) 272 { 273 CONST struct sparc_opcode *opcode = op->opcode; 274 275 /* If the insn isn't supported by the current architecture, skip it. */ 276 if (! (opcode->architecture & current_arch_mask)) 277 continue; 278 279 if ((opcode->match & insn) == opcode->match 280 && (opcode->lose & insn) == 0) 281 { 282 /* Nonzero means that we have found an instruction which has 283 the effect of adding or or'ing the imm13 field to rs1. */ 284 int imm_added_to_rs1 = 0; 285 int imm_ored_to_rs1 = 0; 286 287 /* Nonzero means that we have found a plus sign in the args 288 field of the opcode table. */ 289 int found_plus = 0; 290 291 /* Nonzero means we have an annulled branch. */ 292 int is_annulled = 0; 293 294 /* Do we have an `add' or `or' instruction combining an 295 immediate with rs1? */ 296 if (opcode->match == 0x80102000) /* or */ 297 imm_ored_to_rs1 = 1; 298 if (opcode->match == 0x80002000) /* add */ 299 imm_added_to_rs1 = 1; 300 301 if (X_RS1 (insn) != X_RD (insn) 302 && strchr (opcode->args, 'r') != 0) 303 /* Can't do simple format if source and dest are different. */ 304 continue; 305 if (X_RS2 (insn) != X_RD (insn) 306 && strchr (opcode->args, 'O') != 0) 307 /* Can't do simple format if source and dest are different. */ 308 continue; 309 310 (*info->fprintf_func) (stream, opcode->name); 311 312 { 313 register CONST char *s; 314 315 if (opcode->args[0] != ',') 316 (*info->fprintf_func) (stream, " "); 317 for (s = opcode->args; *s != '\0'; ++s) 318 { 319 while (*s == ',') 320 { 321 (*info->fprintf_func) (stream, ","); 322 ++s; 323 switch (*s) { 324 case 'a': 325 (*info->fprintf_func) (stream, "a"); 326 is_annulled = 1; 327 ++s; 328 continue; 329 case 'N': 330 (*info->fprintf_func) (stream, "pn"); 331 ++s; 332 continue; 333 334 case 'T': 335 (*info->fprintf_func) (stream, "pt"); 336 ++s; 337 continue; 338 339 default: 340 break; 341 } /* switch on arg */ 342 } /* while there are comma started args */ 343 344 (*info->fprintf_func) (stream, " "); 345 346 switch (*s) 347 { 348 case '+': 349 found_plus = 1; 350 351 /* note fall-through */ 352 default: 353 (*info->fprintf_func) (stream, "%c", *s); 354 break; 355 356 case '#': 357 (*info->fprintf_func) (stream, "0"); 358 break; 359 360 #define reg(n) (*info->fprintf_func) (stream, "%%%s", reg_names[n]) 361 case '1': 362 case 'r': 363 reg (X_RS1 (insn)); 364 break; 365 366 case '2': 367 case 'O': 368 reg (X_RS2 (insn)); 369 break; 370 371 case 'd': 372 reg (X_RD (insn)); 373 break; 374 #undef reg 375 376 #define freg(n) (*info->fprintf_func) (stream, "%%%s", freg_names[n]) 377 #define fregx(n) (*info->fprintf_func) (stream, "%%%s", freg_names[((n) & ~1) | (((n) & 1) << 5)]) 378 case 'e': 379 freg (X_RS1 (insn)); 380 break; 381 case 'v': /* double/even */ 382 case 'V': /* quad/multiple of 4 */ 383 fregx (X_RS1 (insn)); 384 break; 385 386 case 'f': 387 freg (X_RS2 (insn)); 388 break; 389 case 'B': /* double/even */ 390 case 'R': /* quad/multiple of 4 */ 391 fregx (X_RS2 (insn)); 392 break; 393 394 case 'g': 395 freg (X_RD (insn)); 396 break; 397 case 'H': /* double/even */ 398 case 'J': /* quad/multiple of 4 */ 399 fregx (X_RD (insn)); 400 break; 401 #undef freg 402 #undef fregx 403 404 #define creg(n) (*info->fprintf_func) (stream, "%%c%u", (unsigned int) (n)) 405 case 'b': 406 creg (X_RS1 (insn)); 407 break; 408 409 case 'c': 410 creg (X_RS2 (insn)); 411 break; 412 413 case 'D': 414 creg (X_RD (insn)); 415 break; 416 #undef creg 417 418 case 'h': 419 (*info->fprintf_func) (stream, "%%hi(%#x)", 420 (0xFFFFFFFF 421 & ((int) X_IMM22 (insn) << 10))); 422 break; 423 424 case 'i': /* 13 bit immediate */ 425 case 'I': /* 11 bit immediate */ 426 case 'j': /* 10 bit immediate */ 427 { 428 int imm; 429 430 if (*s == 'i') 431 imm = X_SIMM (insn, 13); 432 else if (*s == 'I') 433 imm = X_SIMM (insn, 11); 434 else 435 imm = X_SIMM (insn, 10); 436 437 /* Check to see whether we have a 1+i, and take 438 note of that fact. 439 440 Note: because of the way we sort the table, 441 we will be matching 1+i rather than i+1, 442 so it is OK to assume that i is after +, 443 not before it. */ 444 if (found_plus) 445 imm_added_to_rs1 = 1; 446 447 if (imm <= 9) 448 (*info->fprintf_func) (stream, "%d", imm); 449 else 450 (*info->fprintf_func) (stream, "%#x", imm); 451 } 452 break; 453 454 case 'X': /* 5 bit unsigned immediate */ 455 case 'Y': /* 6 bit unsigned immediate */ 456 { 457 int imm = X_IMM (insn, *s == 'X' ? 5 : 6); 458 459 if (imm <= 9) 460 (info->fprintf_func) (stream, "%d", imm); 461 else 462 (info->fprintf_func) (stream, "%#x", (unsigned) imm); 463 } 464 break; 465 466 case 'K': 467 { 468 int mask = X_MEMBAR (insn); 469 int bit = 0x40, printed_one = 0; 470 const char *name; 471 472 if (mask == 0) 473 (info->fprintf_func) (stream, "0"); 474 else 475 while (bit) 476 { 477 if (mask & bit) 478 { 479 if (printed_one) 480 (info->fprintf_func) (stream, "|"); 481 name = sparc_decode_membar (bit); 482 (info->fprintf_func) (stream, "%s", name); 483 printed_one = 1; 484 } 485 bit >>= 1; 486 } 487 break; 488 } 489 490 case 'k': 491 info->target = memaddr + SEX (X_DISP16 (insn), 16) * 4; 492 (*info->print_address_func) (info->target, info); 493 break; 494 495 case 'G': 496 info->target = memaddr + SEX (X_DISP19 (insn), 19) * 4; 497 (*info->print_address_func) (info->target, info); 498 break; 499 500 case '6': 501 case '7': 502 case '8': 503 case '9': 504 (*info->fprintf_func) (stream, "%%fcc%c", *s - '6' + '0'); 505 break; 506 507 case 'z': 508 (*info->fprintf_func) (stream, "%%icc"); 509 break; 510 511 case 'Z': 512 (*info->fprintf_func) (stream, "%%xcc"); 513 break; 514 515 case 'E': 516 (*info->fprintf_func) (stream, "%%ccr"); 517 break; 518 519 case 's': 520 (*info->fprintf_func) (stream, "%%fprs"); 521 break; 522 523 case 'o': 524 (*info->fprintf_func) (stream, "%%asi"); 525 break; 526 527 case 'W': 528 (*info->fprintf_func) (stream, "%%tick"); 529 break; 530 531 case 'P': 532 (*info->fprintf_func) (stream, "%%pc"); 533 break; 534 535 case '?': 536 if (X_RS1 (insn) == 31) 537 (*info->fprintf_func) (stream, "%%ver"); 538 else if ((unsigned) X_RS1 (insn) < 16) 539 (*info->fprintf_func) (stream, "%%%s", 540 v9_priv_reg_names[X_RS1 (insn)]); 541 else 542 (*info->fprintf_func) (stream, "%%reserved"); 543 break; 544 545 case '!': 546 if ((unsigned) X_RD (insn) < 15) 547 (*info->fprintf_func) (stream, "%%%s", 548 v9_priv_reg_names[X_RD (insn)]); 549 else 550 (*info->fprintf_func) (stream, "%%reserved"); 551 break; 552 553 case '/': 554 if (X_RS1 (insn) < 16 || X_RS1 (insn) > 23) 555 (*info->fprintf_func) (stream, "%%reserved"); 556 else 557 (*info->fprintf_func) (stream, "%%%s", 558 v9a_asr_reg_names[X_RS1 (insn)-16]); 559 break; 560 561 case '_': 562 if (X_RD (insn) < 16 || X_RD (insn) > 23) 563 (*info->fprintf_func) (stream, "%%reserved"); 564 else 565 (*info->fprintf_func) (stream, "%%%s", 566 v9a_asr_reg_names[X_RD (insn)-16]); 567 break; 568 569 case '*': 570 { 571 const char *name = sparc_decode_prefetch (X_RD (insn)); 572 573 if (name) 574 (*info->fprintf_func) (stream, "%s", name); 575 else 576 (*info->fprintf_func) (stream, "%d", X_RD (insn)); 577 break; 578 } 579 580 case 'M': 581 (*info->fprintf_func) (stream, "%%asr%d", X_RS1 (insn)); 582 break; 583 584 case 'm': 585 (*info->fprintf_func) (stream, "%%asr%d", X_RD (insn)); 586 break; 587 588 case 'L': 589 info->target = memaddr + SEX (X_DISP30 (insn), 30) * 4; 590 (*info->print_address_func) (info->target, info); 591 break; 592 593 case 'n': 594 (*info->fprintf_func) 595 (stream, "%#x", SEX (X_DISP22 (insn), 22)); 596 break; 597 598 case 'l': 599 info->target = memaddr + SEX (X_DISP22 (insn), 22) * 4; 600 (*info->print_address_func) (info->target, info); 601 break; 602 603 case 'A': 604 { 605 const char *name = sparc_decode_asi (X_ASI (insn)); 606 607 if (name) 608 (*info->fprintf_func) (stream, "%s", name); 609 else 610 (*info->fprintf_func) (stream, "(%d)", X_ASI (insn)); 611 break; 612 } 613 614 case 'C': 615 (*info->fprintf_func) (stream, "%%csr"); 616 break; 617 618 case 'F': 619 (*info->fprintf_func) (stream, "%%fsr"); 620 break; 621 622 case 'p': 623 (*info->fprintf_func) (stream, "%%psr"); 624 break; 625 626 case 'q': 627 (*info->fprintf_func) (stream, "%%fq"); 628 break; 629 630 case 'Q': 631 (*info->fprintf_func) (stream, "%%cq"); 632 break; 633 634 case 't': 635 (*info->fprintf_func) (stream, "%%tbr"); 636 break; 637 638 case 'w': 639 (*info->fprintf_func) (stream, "%%wim"); 640 break; 641 642 case 'x': 643 (*info->fprintf_func) (stream, "%d", 644 ((X_LDST_I (insn) << 8) 645 + X_ASI (insn))); 646 break; 647 648 case 'y': 649 (*info->fprintf_func) (stream, "%%y"); 650 break; 651 652 case 'u': 653 case 'U': 654 { 655 int val = *s == 'U' ? X_RS1 (insn) : X_RD (insn); 656 const char *name = sparc_decode_sparclet_cpreg (val); 657 658 if (name) 659 (*info->fprintf_func) (stream, "%s", name); 660 else 661 (*info->fprintf_func) (stream, "%%cpreg(%d)", val); 662 break; 663 } 664 } 665 } 666 } 667 668 /* If we are adding or or'ing something to rs1, then 669 check to see whether the previous instruction was 670 a sethi to the same register as in the sethi. 671 If so, attempt to print the result of the add or 672 or (in this context add and or do the same thing) 673 and its symbolic value. */ 674 if (imm_ored_to_rs1 || imm_added_to_rs1) 675 { 676 unsigned long prev_insn; 677 int errcode; 678 679 errcode = 680 (*info->read_memory_func) 681 (memaddr - 4, buffer, sizeof (buffer), info); 682 prev_insn = getword (buffer); 683 684 if (errcode == 0) 685 { 686 /* If it is a delayed branch, we need to look at the 687 instruction before the delayed branch. This handles 688 sequences such as 689 690 sethi %o1, %hi(_foo), %o1 691 call _printf 692 or %o1, %lo(_foo), %o1 693 */ 694 695 if (is_delayed_branch (prev_insn)) 696 { 697 errcode = (*info->read_memory_func) 698 (memaddr - 8, buffer, sizeof (buffer), info); 699 prev_insn = getword (buffer); 700 } 701 } 702 703 /* If there was a problem reading memory, then assume 704 the previous instruction was not sethi. */ 705 if (errcode == 0) 706 { 707 /* Is it sethi to the same register? */ 708 if ((prev_insn & 0xc1c00000) == 0x01000000 709 && X_RD (prev_insn) == X_RS1 (insn)) 710 { 711 (*info->fprintf_func) (stream, "\t! "); 712 info->target = 713 (0xFFFFFFFF & (int) X_IMM22 (prev_insn) << 10); 714 if (imm_added_to_rs1) 715 info->target += X_SIMM (insn, 13); 716 else 717 info->target |= X_SIMM (insn, 13); 718 (*info->print_address_func) (info->target, info); 719 info->insn_type = dis_dref; 720 info->data_size = 4; /* FIXME!!! */ 721 } 722 } 723 } 724 725 if (opcode->flags & (F_UNBR|F_CONDBR|F_JSR)) 726 { 727 /* FIXME -- check is_annulled flag */ 728 if (opcode->flags & F_UNBR) 729 info->insn_type = dis_branch; 730 if (opcode->flags & F_CONDBR) 731 info->insn_type = dis_condbranch; 732 if (opcode->flags & F_JSR) 733 info->insn_type = dis_jsr; 734 if (opcode->flags & F_DELAYED) 735 info->branch_delay_insns = 1; 736 } 737 738 return sizeof (buffer); 739 } 740 } 741 742 info->insn_type = dis_noninsn; /* Mark as non-valid instruction */ 743 (*info->fprintf_func) (stream, _("unknown")); 744 return sizeof (buffer); 745 } 746 747 /* Given BFD mach number, return a mask of SPARC_OPCODE_ARCH_FOO values. */ 748 749 static int 750 compute_arch_mask (mach) 751 unsigned long mach; 752 { 753 switch (mach) 754 { 755 case 0 : 756 case bfd_mach_sparc : 757 return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V8); 758 case bfd_mach_sparc_sparclet : 759 return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_SPARCLET); 760 case bfd_mach_sparc_sparclite : 761 case bfd_mach_sparc_sparclite_le : 762 /* sparclites insns are recognized by default (because that's how 763 they've always been treated, for better or worse). Kludge this by 764 indicating generic v8 is also selected. */ 765 return (SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_SPARCLITE) 766 | SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V8)); 767 case bfd_mach_sparc_v8plus : 768 case bfd_mach_sparc_v9 : 769 return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9); 770 case bfd_mach_sparc_v8plusa : 771 case bfd_mach_sparc_v9a : 772 return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9A); 773 } 774 abort (); 775 } 776 777 /* Compare opcodes A and B. */ 778 779 static int 780 compare_opcodes (a, b) 781 const PTR a; 782 const PTR b; 783 { 784 struct sparc_opcode *op0 = * (struct sparc_opcode **) a; 785 struct sparc_opcode *op1 = * (struct sparc_opcode **) b; 786 unsigned long int match0 = op0->match, match1 = op1->match; 787 unsigned long int lose0 = op0->lose, lose1 = op1->lose; 788 register unsigned int i; 789 790 /* If one (and only one) insn isn't supported by the current architecture, 791 prefer the one that is. If neither are supported, but they're both for 792 the same architecture, continue processing. Otherwise (both unsupported 793 and for different architectures), prefer lower numbered arch's (fudged 794 by comparing the bitmasks). */ 795 if (op0->architecture & current_arch_mask) 796 { 797 if (! (op1->architecture & current_arch_mask)) 798 return -1; 799 } 800 else 801 { 802 if (op1->architecture & current_arch_mask) 803 return 1; 804 else if (op0->architecture != op1->architecture) 805 return op0->architecture - op1->architecture; 806 } 807 808 /* If a bit is set in both match and lose, there is something 809 wrong with the opcode table. */ 810 if (match0 & lose0) 811 { 812 fprintf 813 (stderr, 814 /* xgettext:c-format */ 815 _("Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n"), 816 op0->name, match0, lose0); 817 op0->lose &= ~op0->match; 818 lose0 = op0->lose; 819 } 820 821 if (match1 & lose1) 822 { 823 fprintf 824 (stderr, 825 /* xgettext:c-format */ 826 _("Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n"), 827 op1->name, match1, lose1); 828 op1->lose &= ~op1->match; 829 lose1 = op1->lose; 830 } 831 832 /* Because the bits that are variable in one opcode are constant in 833 another, it is important to order the opcodes in the right order. */ 834 for (i = 0; i < 32; ++i) 835 { 836 unsigned long int x = 1 << i; 837 int x0 = (match0 & x) != 0; 838 int x1 = (match1 & x) != 0; 839 840 if (x0 != x1) 841 return x1 - x0; 842 } 843 844 for (i = 0; i < 32; ++i) 845 { 846 unsigned long int x = 1 << i; 847 int x0 = (lose0 & x) != 0; 848 int x1 = (lose1 & x) != 0; 849 850 if (x0 != x1) 851 return x1 - x0; 852 } 853 854 /* They are functionally equal. So as long as the opcode table is 855 valid, we can put whichever one first we want, on aesthetic grounds. */ 856 857 /* Our first aesthetic ground is that aliases defer to real insns. */ 858 { 859 int alias_diff = (op0->flags & F_ALIAS) - (op1->flags & F_ALIAS); 860 if (alias_diff != 0) 861 /* Put the one that isn't an alias first. */ 862 return alias_diff; 863 } 864 865 /* Except for aliases, two "identical" instructions had 866 better have the same opcode. This is a sanity check on the table. */ 867 i = strcmp (op0->name, op1->name); 868 if (i) 869 { 870 if (op0->flags & F_ALIAS) /* If they're both aliases, be arbitrary. */ 871 return i; 872 else 873 fprintf (stderr, 874 /* xgettext:c-format */ 875 _("Internal error: bad sparc-opcode.h: \"%s\" == \"%s\"\n"), 876 op0->name, op1->name); 877 } 878 879 /* Fewer arguments are preferred. */ 880 { 881 int length_diff = strlen (op0->args) - strlen (op1->args); 882 if (length_diff != 0) 883 /* Put the one with fewer arguments first. */ 884 return length_diff; 885 } 886 887 /* Put 1+i before i+1. */ 888 { 889 char *p0 = (char *) strchr (op0->args, '+'); 890 char *p1 = (char *) strchr (op1->args, '+'); 891 892 if (p0 && p1) 893 { 894 /* There is a plus in both operands. Note that a plus 895 sign cannot be the first character in args, 896 so the following [-1]'s are valid. */ 897 if (p0[-1] == 'i' && p1[1] == 'i') 898 /* op0 is i+1 and op1 is 1+i, so op1 goes first. */ 899 return 1; 900 if (p0[1] == 'i' && p1[-1] == 'i') 901 /* op0 is 1+i and op1 is i+1, so op0 goes first. */ 902 return -1; 903 } 904 } 905 906 /* Put 1,i before i,1. */ 907 { 908 int i0 = strncmp (op0->args, "i,1", 3) == 0; 909 int i1 = strncmp (op1->args, "i,1", 3) == 0; 910 911 if (i0 ^ i1) 912 return i0 - i1; 913 } 914 915 /* They are, as far as we can tell, identical. 916 Since qsort may have rearranged the table partially, there is 917 no way to tell which one was first in the opcode table as 918 written, so just say there are equal. */ 919 /* ??? This is no longer true now that we sort a vector of pointers, 920 not the table itself. */ 921 return 0; 922 } 923 924 /* Build a hash table from the opcode table. 925 OPCODE_TABLE is a sorted list of pointers into the opcode table. */ 926 927 static void 928 build_hash_table (opcode_table, hash_table, num_opcodes) 929 const struct sparc_opcode **opcode_table; 930 struct opcode_hash **hash_table; 931 int num_opcodes; 932 { 933 register int i; 934 int hash_count[HASH_SIZE]; 935 static struct opcode_hash *hash_buf = NULL; 936 937 /* Start at the end of the table and work backwards so that each 938 chain is sorted. */ 939 940 memset (hash_table, 0, HASH_SIZE * sizeof (hash_table[0])); 941 memset (hash_count, 0, HASH_SIZE * sizeof (hash_count[0])); 942 if (hash_buf != NULL) 943 free (hash_buf); 944 hash_buf = (struct opcode_hash *) xmalloc (sizeof (struct opcode_hash) * num_opcodes); 945 for (i = num_opcodes - 1; i >= 0; --i) 946 { 947 register int hash = HASH_INSN (opcode_table[i]->match); 948 register struct opcode_hash *h = &hash_buf[i]; 949 h->next = hash_table[hash]; 950 h->opcode = opcode_table[i]; 951 hash_table[hash] = h; 952 ++hash_count[hash]; 953 } 954 955 #if 0 /* for debugging */ 956 { 957 int min_count = num_opcodes, max_count = 0; 958 int total; 959 960 for (i = 0; i < HASH_SIZE; ++i) 961 { 962 if (hash_count[i] < min_count) 963 min_count = hash_count[i]; 964 if (hash_count[i] > max_count) 965 max_count = hash_count[i]; 966 total += hash_count[i]; 967 } 968 969 printf ("Opcode hash table stats: min %d, max %d, ave %f\n", 970 min_count, max_count, (double) total / HASH_SIZE); 971 } 972 #endif 973 } 974