1 /* Instruction opcode table for m32r. 2 3 THIS FILE IS MACHINE GENERATED WITH CGEN. 4 5 Copyright (C) 1996, 1997, 1998, 1999 Free Software Foundation, Inc. 6 7 This file is part of the GNU Binutils and/or GDB, the GNU debugger. 8 9 This program is free software; you can redistribute it and/or modify 10 it under the terms of the GNU General Public License as published by 11 the Free Software Foundation; either version 2, or (at your option) 12 any later version. 13 14 This program is distributed in the hope that it will be useful, 15 but WITHOUT ANY WARRANTY; without even the implied warranty of 16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 GNU General Public License for more details. 18 19 You should have received a copy of the GNU General Public License along 20 with this program; if not, write to the Free Software Foundation, Inc., 21 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. 22 23 */ 24 25 #include "sysdep.h" 26 #include "ansidecl.h" 27 #include "bfd.h" 28 #include "symcat.h" 29 #include "m32r-desc.h" 30 #include "m32r-opc.h" 31 32 /* The hash functions are recorded here to help keep assembler code out of 33 the disassembler and vice versa. */ 34 35 static int asm_hash_insn_p PARAMS ((const CGEN_INSN *)); 36 static unsigned int asm_hash_insn PARAMS ((const char *)); 37 static int dis_hash_insn_p PARAMS ((const CGEN_INSN *)); 38 static unsigned int dis_hash_insn PARAMS ((const char *, CGEN_INSN_INT)); 39 40 /* Instruction formats. */ 41 42 #define F(f) & m32r_cgen_ifld_table[CONCAT2 (M32R_,f)] 43 44 static const CGEN_IFMT ifmt_empty = { 45 0, 0, 0x0, { 0 } 46 }; 47 48 static const CGEN_IFMT ifmt_add = { 49 16, 16, 0xf0f0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 } 50 }; 51 52 static const CGEN_IFMT ifmt_add3 = { 53 32, 32, 0xf0f00000, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_SIMM16), 0 } 54 }; 55 56 static const CGEN_IFMT ifmt_and3 = { 57 32, 32, 0xf0f00000, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_UIMM16), 0 } 58 }; 59 60 static const CGEN_IFMT ifmt_or3 = { 61 32, 32, 0xf0f00000, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_UIMM16), 0 } 62 }; 63 64 static const CGEN_IFMT ifmt_addi = { 65 16, 16, 0xf000, { F (F_OP1), F (F_R1), F (F_SIMM8), 0 } 66 }; 67 68 static const CGEN_IFMT ifmt_addv3 = { 69 32, 32, 0xf0f00000, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_SIMM16), 0 } 70 }; 71 72 static const CGEN_IFMT ifmt_bc8 = { 73 16, 16, 0xff00, { F (F_OP1), F (F_R1), F (F_DISP8), 0 } 74 }; 75 76 static const CGEN_IFMT ifmt_bc24 = { 77 32, 32, 0xff000000, { F (F_OP1), F (F_R1), F (F_DISP24), 0 } 78 }; 79 80 static const CGEN_IFMT ifmt_beq = { 81 32, 32, 0xf0f00000, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_DISP16), 0 } 82 }; 83 84 static const CGEN_IFMT ifmt_beqz = { 85 32, 32, 0xfff00000, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_DISP16), 0 } 86 }; 87 88 static const CGEN_IFMT ifmt_cmp = { 89 16, 16, 0xf0f0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 } 90 }; 91 92 static const CGEN_IFMT ifmt_cmpi = { 93 32, 32, 0xfff00000, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_SIMM16), 0 } 94 }; 95 96 static const CGEN_IFMT ifmt_cmpz = { 97 16, 16, 0xfff0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 } 98 }; 99 100 static const CGEN_IFMT ifmt_div = { 101 32, 32, 0xf0f0ffff, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_SIMM16), 0 } 102 }; 103 104 static const CGEN_IFMT ifmt_jc = { 105 16, 16, 0xfff0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 } 106 }; 107 108 static const CGEN_IFMT ifmt_ld24 = { 109 32, 32, 0xf0000000, { F (F_OP1), F (F_R1), F (F_UIMM24), 0 } 110 }; 111 112 static const CGEN_IFMT ifmt_ldi16 = { 113 32, 32, 0xf0ff0000, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_SIMM16), 0 } 114 }; 115 116 static const CGEN_IFMT ifmt_machi_a = { 117 16, 16, 0xf070, { F (F_OP1), F (F_R1), F (F_ACC), F (F_OP23), F (F_R2), 0 } 118 }; 119 120 static const CGEN_IFMT ifmt_mvfachi = { 121 16, 16, 0xf0ff, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 } 122 }; 123 124 static const CGEN_IFMT ifmt_mvfachi_a = { 125 16, 16, 0xf0f3, { F (F_OP1), F (F_R1), F (F_OP2), F (F_ACCS), F (F_OP3), 0 } 126 }; 127 128 static const CGEN_IFMT ifmt_mvfc = { 129 16, 16, 0xf0f0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 } 130 }; 131 132 static const CGEN_IFMT ifmt_mvtachi = { 133 16, 16, 0xf0ff, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 } 134 }; 135 136 static const CGEN_IFMT ifmt_mvtachi_a = { 137 16, 16, 0xf0f3, { F (F_OP1), F (F_R1), F (F_OP2), F (F_ACCS), F (F_OP3), 0 } 138 }; 139 140 static const CGEN_IFMT ifmt_mvtc = { 141 16, 16, 0xf0f0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 } 142 }; 143 144 static const CGEN_IFMT ifmt_nop = { 145 16, 16, 0xffff, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 } 146 }; 147 148 static const CGEN_IFMT ifmt_rac_dsi = { 149 16, 16, 0xf3f2, { F (F_OP1), F (F_ACCD), F (F_BITS67), F (F_OP2), F (F_ACCS), F (F_BIT14), F (F_IMM1), 0 } 150 }; 151 152 static const CGEN_IFMT ifmt_seth = { 153 32, 32, 0xf0ff0000, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_HI16), 0 } 154 }; 155 156 static const CGEN_IFMT ifmt_slli = { 157 16, 16, 0xf0e0, { F (F_OP1), F (F_R1), F (F_SHIFT_OP2), F (F_UIMM5), 0 } 158 }; 159 160 static const CGEN_IFMT ifmt_st_d = { 161 32, 32, 0xf0f00000, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_SIMM16), 0 } 162 }; 163 164 static const CGEN_IFMT ifmt_trap = { 165 16, 16, 0xfff0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_UIMM4), 0 } 166 }; 167 168 static const CGEN_IFMT ifmt_satb = { 169 32, 32, 0xf0f0ffff, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_UIMM16), 0 } 170 }; 171 172 #undef F 173 174 #define A(a) (1 << CONCAT2 (CGEN_INSN_,a)) 175 #define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */ 176 #define OPERAND(op) CONCAT2 (M32R_OPERAND_,op) 177 #define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field)) 178 179 /* The instruction table. */ 180 181 static const CGEN_OPCODE m32r_cgen_insn_opcode_table[MAX_INSNS] = 182 { 183 /* Special null first entry. 184 A `num' value of zero is thus invalid. 185 Also, the special `invalid' insn resides here. */ 186 { { 0 } }, 187 /* add $dr,$sr */ 188 { 189 { 0, 0, 0, 0 }, 190 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, 191 & ifmt_add, { 0xa0 } 192 }, 193 /* add3 $dr,$sr,$hash$slo16 */ 194 { 195 { 0, 0, 0, 0 }, 196 { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (HASH), OP (SLO16), 0 } }, 197 & ifmt_add3, { 0x80a00000 } 198 }, 199 /* and $dr,$sr */ 200 { 201 { 0, 0, 0, 0 }, 202 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, 203 & ifmt_add, { 0xc0 } 204 }, 205 /* and3 $dr,$sr,$uimm16 */ 206 { 207 { 0, 0, 0, 0 }, 208 { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (UIMM16), 0 } }, 209 & ifmt_and3, { 0x80c00000 } 210 }, 211 /* or $dr,$sr */ 212 { 213 { 0, 0, 0, 0 }, 214 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, 215 & ifmt_add, { 0xe0 } 216 }, 217 /* or3 $dr,$sr,$hash$ulo16 */ 218 { 219 { 0, 0, 0, 0 }, 220 { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (HASH), OP (ULO16), 0 } }, 221 & ifmt_or3, { 0x80e00000 } 222 }, 223 /* xor $dr,$sr */ 224 { 225 { 0, 0, 0, 0 }, 226 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, 227 & ifmt_add, { 0xd0 } 228 }, 229 /* xor3 $dr,$sr,$uimm16 */ 230 { 231 { 0, 0, 0, 0 }, 232 { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (UIMM16), 0 } }, 233 & ifmt_and3, { 0x80d00000 } 234 }, 235 /* addi $dr,$simm8 */ 236 { 237 { 0, 0, 0, 0 }, 238 { { MNEM, ' ', OP (DR), ',', OP (SIMM8), 0 } }, 239 & ifmt_addi, { 0x4000 } 240 }, 241 /* addv $dr,$sr */ 242 { 243 { 0, 0, 0, 0 }, 244 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, 245 & ifmt_add, { 0x80 } 246 }, 247 /* addv3 $dr,$sr,$simm16 */ 248 { 249 { 0, 0, 0, 0 }, 250 { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (SIMM16), 0 } }, 251 & ifmt_addv3, { 0x80800000 } 252 }, 253 /* addx $dr,$sr */ 254 { 255 { 0, 0, 0, 0 }, 256 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, 257 & ifmt_add, { 0x90 } 258 }, 259 /* bc.s $disp8 */ 260 { 261 { 0, 0, 0, 0 }, 262 { { MNEM, ' ', OP (DISP8), 0 } }, 263 & ifmt_bc8, { 0x7c00 } 264 }, 265 /* bc.l $disp24 */ 266 { 267 { 0, 0, 0, 0 }, 268 { { MNEM, ' ', OP (DISP24), 0 } }, 269 & ifmt_bc24, { 0xfc000000 } 270 }, 271 /* beq $src1,$src2,$disp16 */ 272 { 273 { 0, 0, 0, 0 }, 274 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (DISP16), 0 } }, 275 & ifmt_beq, { 0xb0000000 } 276 }, 277 /* beqz $src2,$disp16 */ 278 { 279 { 0, 0, 0, 0 }, 280 { { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 } }, 281 & ifmt_beqz, { 0xb0800000 } 282 }, 283 /* bgez $src2,$disp16 */ 284 { 285 { 0, 0, 0, 0 }, 286 { { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 } }, 287 & ifmt_beqz, { 0xb0b00000 } 288 }, 289 /* bgtz $src2,$disp16 */ 290 { 291 { 0, 0, 0, 0 }, 292 { { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 } }, 293 & ifmt_beqz, { 0xb0d00000 } 294 }, 295 /* blez $src2,$disp16 */ 296 { 297 { 0, 0, 0, 0 }, 298 { { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 } }, 299 & ifmt_beqz, { 0xb0c00000 } 300 }, 301 /* bltz $src2,$disp16 */ 302 { 303 { 0, 0, 0, 0 }, 304 { { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 } }, 305 & ifmt_beqz, { 0xb0a00000 } 306 }, 307 /* bnez $src2,$disp16 */ 308 { 309 { 0, 0, 0, 0 }, 310 { { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 } }, 311 & ifmt_beqz, { 0xb0900000 } 312 }, 313 /* bl.s $disp8 */ 314 { 315 { 0, 0, 0, 0 }, 316 { { MNEM, ' ', OP (DISP8), 0 } }, 317 & ifmt_bc8, { 0x7e00 } 318 }, 319 /* bl.l $disp24 */ 320 { 321 { 0, 0, 0, 0 }, 322 { { MNEM, ' ', OP (DISP24), 0 } }, 323 & ifmt_bc24, { 0xfe000000 } 324 }, 325 /* bcl.s $disp8 */ 326 { 327 { 0, 0, 0, 0 }, 328 { { MNEM, ' ', OP (DISP8), 0 } }, 329 & ifmt_bc8, { 0x7800 } 330 }, 331 /* bcl.l $disp24 */ 332 { 333 { 0, 0, 0, 0 }, 334 { { MNEM, ' ', OP (DISP24), 0 } }, 335 & ifmt_bc24, { 0xf8000000 } 336 }, 337 /* bnc.s $disp8 */ 338 { 339 { 0, 0, 0, 0 }, 340 { { MNEM, ' ', OP (DISP8), 0 } }, 341 & ifmt_bc8, { 0x7d00 } 342 }, 343 /* bnc.l $disp24 */ 344 { 345 { 0, 0, 0, 0 }, 346 { { MNEM, ' ', OP (DISP24), 0 } }, 347 & ifmt_bc24, { 0xfd000000 } 348 }, 349 /* bne $src1,$src2,$disp16 */ 350 { 351 { 0, 0, 0, 0 }, 352 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (DISP16), 0 } }, 353 & ifmt_beq, { 0xb0100000 } 354 }, 355 /* bra.s $disp8 */ 356 { 357 { 0, 0, 0, 0 }, 358 { { MNEM, ' ', OP (DISP8), 0 } }, 359 & ifmt_bc8, { 0x7f00 } 360 }, 361 /* bra.l $disp24 */ 362 { 363 { 0, 0, 0, 0 }, 364 { { MNEM, ' ', OP (DISP24), 0 } }, 365 & ifmt_bc24, { 0xff000000 } 366 }, 367 /* bncl.s $disp8 */ 368 { 369 { 0, 0, 0, 0 }, 370 { { MNEM, ' ', OP (DISP8), 0 } }, 371 & ifmt_bc8, { 0x7900 } 372 }, 373 /* bncl.l $disp24 */ 374 { 375 { 0, 0, 0, 0 }, 376 { { MNEM, ' ', OP (DISP24), 0 } }, 377 & ifmt_bc24, { 0xf9000000 } 378 }, 379 /* cmp $src1,$src2 */ 380 { 381 { 0, 0, 0, 0 }, 382 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } }, 383 & ifmt_cmp, { 0x40 } 384 }, 385 /* cmpi $src2,$simm16 */ 386 { 387 { 0, 0, 0, 0 }, 388 { { MNEM, ' ', OP (SRC2), ',', OP (SIMM16), 0 } }, 389 & ifmt_cmpi, { 0x80400000 } 390 }, 391 /* cmpu $src1,$src2 */ 392 { 393 { 0, 0, 0, 0 }, 394 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } }, 395 & ifmt_cmp, { 0x50 } 396 }, 397 /* cmpui $src2,$simm16 */ 398 { 399 { 0, 0, 0, 0 }, 400 { { MNEM, ' ', OP (SRC2), ',', OP (SIMM16), 0 } }, 401 & ifmt_cmpi, { 0x80500000 } 402 }, 403 /* cmpeq $src1,$src2 */ 404 { 405 { 0, 0, 0, 0 }, 406 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } }, 407 & ifmt_cmp, { 0x60 } 408 }, 409 /* cmpz $src2 */ 410 { 411 { 0, 0, 0, 0 }, 412 { { MNEM, ' ', OP (SRC2), 0 } }, 413 & ifmt_cmpz, { 0x70 } 414 }, 415 /* div $dr,$sr */ 416 { 417 { 0, 0, 0, 0 }, 418 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, 419 & ifmt_div, { 0x90000000 } 420 }, 421 /* divu $dr,$sr */ 422 { 423 { 0, 0, 0, 0 }, 424 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, 425 & ifmt_div, { 0x90100000 } 426 }, 427 /* rem $dr,$sr */ 428 { 429 { 0, 0, 0, 0 }, 430 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, 431 & ifmt_div, { 0x90200000 } 432 }, 433 /* remu $dr,$sr */ 434 { 435 { 0, 0, 0, 0 }, 436 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, 437 & ifmt_div, { 0x90300000 } 438 }, 439 /* divh $dr,$sr */ 440 { 441 { 0, 0, 0, 0 }, 442 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, 443 & ifmt_div, { 0x90000010 } 444 }, 445 /* jc $sr */ 446 { 447 { 0, 0, 0, 0 }, 448 { { MNEM, ' ', OP (SR), 0 } }, 449 & ifmt_jc, { 0x1cc0 } 450 }, 451 /* jnc $sr */ 452 { 453 { 0, 0, 0, 0 }, 454 { { MNEM, ' ', OP (SR), 0 } }, 455 & ifmt_jc, { 0x1dc0 } 456 }, 457 /* jl $sr */ 458 { 459 { 0, 0, 0, 0 }, 460 { { MNEM, ' ', OP (SR), 0 } }, 461 & ifmt_jc, { 0x1ec0 } 462 }, 463 /* jmp $sr */ 464 { 465 { 0, 0, 0, 0 }, 466 { { MNEM, ' ', OP (SR), 0 } }, 467 & ifmt_jc, { 0x1fc0 } 468 }, 469 /* ld $dr,@$sr */ 470 { 471 { 0, 0, 0, 0 }, 472 { { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 } }, 473 & ifmt_add, { 0x20c0 } 474 }, 475 /* ld $dr,@($slo16,$sr) */ 476 { 477 { 0, 0, 0, 0 }, 478 { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 } }, 479 & ifmt_add3, { 0xa0c00000 } 480 }, 481 /* ldb $dr,@$sr */ 482 { 483 { 0, 0, 0, 0 }, 484 { { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 } }, 485 & ifmt_add, { 0x2080 } 486 }, 487 /* ldb $dr,@($slo16,$sr) */ 488 { 489 { 0, 0, 0, 0 }, 490 { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 } }, 491 & ifmt_add3, { 0xa0800000 } 492 }, 493 /* ldh $dr,@$sr */ 494 { 495 { 0, 0, 0, 0 }, 496 { { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 } }, 497 & ifmt_add, { 0x20a0 } 498 }, 499 /* ldh $dr,@($slo16,$sr) */ 500 { 501 { 0, 0, 0, 0 }, 502 { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 } }, 503 & ifmt_add3, { 0xa0a00000 } 504 }, 505 /* ldub $dr,@$sr */ 506 { 507 { 0, 0, 0, 0 }, 508 { { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 } }, 509 & ifmt_add, { 0x2090 } 510 }, 511 /* ldub $dr,@($slo16,$sr) */ 512 { 513 { 0, 0, 0, 0 }, 514 { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 } }, 515 & ifmt_add3, { 0xa0900000 } 516 }, 517 /* lduh $dr,@$sr */ 518 { 519 { 0, 0, 0, 0 }, 520 { { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 } }, 521 & ifmt_add, { 0x20b0 } 522 }, 523 /* lduh $dr,@($slo16,$sr) */ 524 { 525 { 0, 0, 0, 0 }, 526 { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 } }, 527 & ifmt_add3, { 0xa0b00000 } 528 }, 529 /* ld $dr,@$sr+ */ 530 { 531 { 0, 0, 0, 0 }, 532 { { MNEM, ' ', OP (DR), ',', '@', OP (SR), '+', 0 } }, 533 & ifmt_add, { 0x20e0 } 534 }, 535 /* ld24 $dr,$uimm24 */ 536 { 537 { 0, 0, 0, 0 }, 538 { { MNEM, ' ', OP (DR), ',', OP (UIMM24), 0 } }, 539 & ifmt_ld24, { 0xe0000000 } 540 }, 541 /* ldi8 $dr,$simm8 */ 542 { 543 { 0, 0, 0, 0 }, 544 { { MNEM, ' ', OP (DR), ',', OP (SIMM8), 0 } }, 545 & ifmt_addi, { 0x6000 } 546 }, 547 /* ldi16 $dr,$hash$slo16 */ 548 { 549 { 0, 0, 0, 0 }, 550 { { MNEM, ' ', OP (DR), ',', OP (HASH), OP (SLO16), 0 } }, 551 & ifmt_ldi16, { 0x90f00000 } 552 }, 553 /* lock $dr,@$sr */ 554 { 555 { 0, 0, 0, 0 }, 556 { { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 } }, 557 & ifmt_add, { 0x20d0 } 558 }, 559 /* machi $src1,$src2 */ 560 { 561 { 0, 0, 0, 0 }, 562 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } }, 563 & ifmt_cmp, { 0x3040 } 564 }, 565 /* machi $src1,$src2,$acc */ 566 { 567 { 0, 0, 0, 0 }, 568 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } }, 569 & ifmt_machi_a, { 0x3040 } 570 }, 571 /* maclo $src1,$src2 */ 572 { 573 { 0, 0, 0, 0 }, 574 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } }, 575 & ifmt_cmp, { 0x3050 } 576 }, 577 /* maclo $src1,$src2,$acc */ 578 { 579 { 0, 0, 0, 0 }, 580 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } }, 581 & ifmt_machi_a, { 0x3050 } 582 }, 583 /* macwhi $src1,$src2 */ 584 { 585 { 0, 0, 0, 0 }, 586 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } }, 587 & ifmt_cmp, { 0x3060 } 588 }, 589 /* macwhi $src1,$src2,$acc */ 590 { 591 { 0, 0, 0, 0 }, 592 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } }, 593 & ifmt_machi_a, { 0x3060 } 594 }, 595 /* macwlo $src1,$src2 */ 596 { 597 { 0, 0, 0, 0 }, 598 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } }, 599 & ifmt_cmp, { 0x3070 } 600 }, 601 /* macwlo $src1,$src2,$acc */ 602 { 603 { 0, 0, 0, 0 }, 604 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } }, 605 & ifmt_machi_a, { 0x3070 } 606 }, 607 /* mul $dr,$sr */ 608 { 609 { 0, 0, 0, 0 }, 610 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, 611 & ifmt_add, { 0x1060 } 612 }, 613 /* mulhi $src1,$src2 */ 614 { 615 { 0, 0, 0, 0 }, 616 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } }, 617 & ifmt_cmp, { 0x3000 } 618 }, 619 /* mulhi $src1,$src2,$acc */ 620 { 621 { 0, 0, 0, 0 }, 622 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } }, 623 & ifmt_machi_a, { 0x3000 } 624 }, 625 /* mullo $src1,$src2 */ 626 { 627 { 0, 0, 0, 0 }, 628 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } }, 629 & ifmt_cmp, { 0x3010 } 630 }, 631 /* mullo $src1,$src2,$acc */ 632 { 633 { 0, 0, 0, 0 }, 634 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } }, 635 & ifmt_machi_a, { 0x3010 } 636 }, 637 /* mulwhi $src1,$src2 */ 638 { 639 { 0, 0, 0, 0 }, 640 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } }, 641 & ifmt_cmp, { 0x3020 } 642 }, 643 /* mulwhi $src1,$src2,$acc */ 644 { 645 { 0, 0, 0, 0 }, 646 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } }, 647 & ifmt_machi_a, { 0x3020 } 648 }, 649 /* mulwlo $src1,$src2 */ 650 { 651 { 0, 0, 0, 0 }, 652 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } }, 653 & ifmt_cmp, { 0x3030 } 654 }, 655 /* mulwlo $src1,$src2,$acc */ 656 { 657 { 0, 0, 0, 0 }, 658 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } }, 659 & ifmt_machi_a, { 0x3030 } 660 }, 661 /* mv $dr,$sr */ 662 { 663 { 0, 0, 0, 0 }, 664 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, 665 & ifmt_add, { 0x1080 } 666 }, 667 /* mvfachi $dr */ 668 { 669 { 0, 0, 0, 0 }, 670 { { MNEM, ' ', OP (DR), 0 } }, 671 & ifmt_mvfachi, { 0x50f0 } 672 }, 673 /* mvfachi $dr,$accs */ 674 { 675 { 0, 0, 0, 0 }, 676 { { MNEM, ' ', OP (DR), ',', OP (ACCS), 0 } }, 677 & ifmt_mvfachi_a, { 0x50f0 } 678 }, 679 /* mvfaclo $dr */ 680 { 681 { 0, 0, 0, 0 }, 682 { { MNEM, ' ', OP (DR), 0 } }, 683 & ifmt_mvfachi, { 0x50f1 } 684 }, 685 /* mvfaclo $dr,$accs */ 686 { 687 { 0, 0, 0, 0 }, 688 { { MNEM, ' ', OP (DR), ',', OP (ACCS), 0 } }, 689 & ifmt_mvfachi_a, { 0x50f1 } 690 }, 691 /* mvfacmi $dr */ 692 { 693 { 0, 0, 0, 0 }, 694 { { MNEM, ' ', OP (DR), 0 } }, 695 & ifmt_mvfachi, { 0x50f2 } 696 }, 697 /* mvfacmi $dr,$accs */ 698 { 699 { 0, 0, 0, 0 }, 700 { { MNEM, ' ', OP (DR), ',', OP (ACCS), 0 } }, 701 & ifmt_mvfachi_a, { 0x50f2 } 702 }, 703 /* mvfc $dr,$scr */ 704 { 705 { 0, 0, 0, 0 }, 706 { { MNEM, ' ', OP (DR), ',', OP (SCR), 0 } }, 707 & ifmt_mvfc, { 0x1090 } 708 }, 709 /* mvtachi $src1 */ 710 { 711 { 0, 0, 0, 0 }, 712 { { MNEM, ' ', OP (SRC1), 0 } }, 713 & ifmt_mvtachi, { 0x5070 } 714 }, 715 /* mvtachi $src1,$accs */ 716 { 717 { 0, 0, 0, 0 }, 718 { { MNEM, ' ', OP (SRC1), ',', OP (ACCS), 0 } }, 719 & ifmt_mvtachi_a, { 0x5070 } 720 }, 721 /* mvtaclo $src1 */ 722 { 723 { 0, 0, 0, 0 }, 724 { { MNEM, ' ', OP (SRC1), 0 } }, 725 & ifmt_mvtachi, { 0x5071 } 726 }, 727 /* mvtaclo $src1,$accs */ 728 { 729 { 0, 0, 0, 0 }, 730 { { MNEM, ' ', OP (SRC1), ',', OP (ACCS), 0 } }, 731 & ifmt_mvtachi_a, { 0x5071 } 732 }, 733 /* mvtc $sr,$dcr */ 734 { 735 { 0, 0, 0, 0 }, 736 { { MNEM, ' ', OP (SR), ',', OP (DCR), 0 } }, 737 & ifmt_mvtc, { 0x10a0 } 738 }, 739 /* neg $dr,$sr */ 740 { 741 { 0, 0, 0, 0 }, 742 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, 743 & ifmt_add, { 0x30 } 744 }, 745 /* nop */ 746 { 747 { 0, 0, 0, 0 }, 748 { { MNEM, 0 } }, 749 & ifmt_nop, { 0x7000 } 750 }, 751 /* not $dr,$sr */ 752 { 753 { 0, 0, 0, 0 }, 754 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, 755 & ifmt_add, { 0xb0 } 756 }, 757 /* rac */ 758 { 759 { 0, 0, 0, 0 }, 760 { { MNEM, 0 } }, 761 & ifmt_nop, { 0x5090 } 762 }, 763 /* rac $accd,$accs,$imm1 */ 764 { 765 { 0, 0, 0, 0 }, 766 { { MNEM, ' ', OP (ACCD), ',', OP (ACCS), ',', OP (IMM1), 0 } }, 767 & ifmt_rac_dsi, { 0x5090 } 768 }, 769 /* rach */ 770 { 771 { 0, 0, 0, 0 }, 772 { { MNEM, 0 } }, 773 & ifmt_nop, { 0x5080 } 774 }, 775 /* rach $accd,$accs,$imm1 */ 776 { 777 { 0, 0, 0, 0 }, 778 { { MNEM, ' ', OP (ACCD), ',', OP (ACCS), ',', OP (IMM1), 0 } }, 779 & ifmt_rac_dsi, { 0x5080 } 780 }, 781 /* rte */ 782 { 783 { 0, 0, 0, 0 }, 784 { { MNEM, 0 } }, 785 & ifmt_nop, { 0x10d6 } 786 }, 787 /* seth $dr,$hash$hi16 */ 788 { 789 { 0, 0, 0, 0 }, 790 { { MNEM, ' ', OP (DR), ',', OP (HASH), OP (HI16), 0 } }, 791 & ifmt_seth, { 0xd0c00000 } 792 }, 793 /* sll $dr,$sr */ 794 { 795 { 0, 0, 0, 0 }, 796 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, 797 & ifmt_add, { 0x1040 } 798 }, 799 /* sll3 $dr,$sr,$simm16 */ 800 { 801 { 0, 0, 0, 0 }, 802 { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (SIMM16), 0 } }, 803 & ifmt_addv3, { 0x90c00000 } 804 }, 805 /* slli $dr,$uimm5 */ 806 { 807 { 0, 0, 0, 0 }, 808 { { MNEM, ' ', OP (DR), ',', OP (UIMM5), 0 } }, 809 & ifmt_slli, { 0x5040 } 810 }, 811 /* sra $dr,$sr */ 812 { 813 { 0, 0, 0, 0 }, 814 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, 815 & ifmt_add, { 0x1020 } 816 }, 817 /* sra3 $dr,$sr,$simm16 */ 818 { 819 { 0, 0, 0, 0 }, 820 { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (SIMM16), 0 } }, 821 & ifmt_addv3, { 0x90a00000 } 822 }, 823 /* srai $dr,$uimm5 */ 824 { 825 { 0, 0, 0, 0 }, 826 { { MNEM, ' ', OP (DR), ',', OP (UIMM5), 0 } }, 827 & ifmt_slli, { 0x5020 } 828 }, 829 /* srl $dr,$sr */ 830 { 831 { 0, 0, 0, 0 }, 832 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, 833 & ifmt_add, { 0x1000 } 834 }, 835 /* srl3 $dr,$sr,$simm16 */ 836 { 837 { 0, 0, 0, 0 }, 838 { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (SIMM16), 0 } }, 839 & ifmt_addv3, { 0x90800000 } 840 }, 841 /* srli $dr,$uimm5 */ 842 { 843 { 0, 0, 0, 0 }, 844 { { MNEM, ' ', OP (DR), ',', OP (UIMM5), 0 } }, 845 & ifmt_slli, { 0x5000 } 846 }, 847 /* st $src1,@$src2 */ 848 { 849 { 0, 0, 0, 0 }, 850 { { MNEM, ' ', OP (SRC1), ',', '@', OP (SRC2), 0 } }, 851 & ifmt_cmp, { 0x2040 } 852 }, 853 /* st $src1,@($slo16,$src2) */ 854 { 855 { 0, 0, 0, 0 }, 856 { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SLO16), ',', OP (SRC2), ')', 0 } }, 857 & ifmt_st_d, { 0xa0400000 } 858 }, 859 /* stb $src1,@$src2 */ 860 { 861 { 0, 0, 0, 0 }, 862 { { MNEM, ' ', OP (SRC1), ',', '@', OP (SRC2), 0 } }, 863 & ifmt_cmp, { 0x2000 } 864 }, 865 /* stb $src1,@($slo16,$src2) */ 866 { 867 { 0, 0, 0, 0 }, 868 { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SLO16), ',', OP (SRC2), ')', 0 } }, 869 & ifmt_st_d, { 0xa0000000 } 870 }, 871 /* sth $src1,@$src2 */ 872 { 873 { 0, 0, 0, 0 }, 874 { { MNEM, ' ', OP (SRC1), ',', '@', OP (SRC2), 0 } }, 875 & ifmt_cmp, { 0x2020 } 876 }, 877 /* sth $src1,@($slo16,$src2) */ 878 { 879 { 0, 0, 0, 0 }, 880 { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SLO16), ',', OP (SRC2), ')', 0 } }, 881 & ifmt_st_d, { 0xa0200000 } 882 }, 883 /* st $src1,@+$src2 */ 884 { 885 { 0, 0, 0, 0 }, 886 { { MNEM, ' ', OP (SRC1), ',', '@', '+', OP (SRC2), 0 } }, 887 & ifmt_cmp, { 0x2060 } 888 }, 889 /* st $src1,@-$src2 */ 890 { 891 { 0, 0, 0, 0 }, 892 { { MNEM, ' ', OP (SRC1), ',', '@', '-', OP (SRC2), 0 } }, 893 & ifmt_cmp, { 0x2070 } 894 }, 895 /* sub $dr,$sr */ 896 { 897 { 0, 0, 0, 0 }, 898 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, 899 & ifmt_add, { 0x20 } 900 }, 901 /* subv $dr,$sr */ 902 { 903 { 0, 0, 0, 0 }, 904 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, 905 & ifmt_add, { 0x0 } 906 }, 907 /* subx $dr,$sr */ 908 { 909 { 0, 0, 0, 0 }, 910 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, 911 & ifmt_add, { 0x10 } 912 }, 913 /* trap $uimm4 */ 914 { 915 { 0, 0, 0, 0 }, 916 { { MNEM, ' ', OP (UIMM4), 0 } }, 917 & ifmt_trap, { 0x10f0 } 918 }, 919 /* unlock $src1,@$src2 */ 920 { 921 { 0, 0, 0, 0 }, 922 { { MNEM, ' ', OP (SRC1), ',', '@', OP (SRC2), 0 } }, 923 & ifmt_cmp, { 0x2050 } 924 }, 925 /* satb $dr,$sr */ 926 { 927 { 0, 0, 0, 0 }, 928 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, 929 & ifmt_satb, { 0x80600300 } 930 }, 931 /* sath $dr,$sr */ 932 { 933 { 0, 0, 0, 0 }, 934 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, 935 & ifmt_satb, { 0x80600200 } 936 }, 937 /* sat $dr,$sr */ 938 { 939 { 0, 0, 0, 0 }, 940 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, 941 & ifmt_satb, { 0x80600000 } 942 }, 943 /* pcmpbz $src2 */ 944 { 945 { 0, 0, 0, 0 }, 946 { { MNEM, ' ', OP (SRC2), 0 } }, 947 & ifmt_cmpz, { 0x370 } 948 }, 949 /* sadd */ 950 { 951 { 0, 0, 0, 0 }, 952 { { MNEM, 0 } }, 953 & ifmt_nop, { 0x50e4 } 954 }, 955 /* macwu1 $src1,$src2 */ 956 { 957 { 0, 0, 0, 0 }, 958 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } }, 959 & ifmt_cmp, { 0x50b0 } 960 }, 961 /* msblo $src1,$src2 */ 962 { 963 { 0, 0, 0, 0 }, 964 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } }, 965 & ifmt_cmp, { 0x50d0 } 966 }, 967 /* mulwu1 $src1,$src2 */ 968 { 969 { 0, 0, 0, 0 }, 970 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } }, 971 & ifmt_cmp, { 0x50a0 } 972 }, 973 /* maclh1 $src1,$src2 */ 974 { 975 { 0, 0, 0, 0 }, 976 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } }, 977 & ifmt_cmp, { 0x50c0 } 978 }, 979 /* sc */ 980 { 981 { 0, 0, 0, 0 }, 982 { { MNEM, 0 } }, 983 & ifmt_nop, { 0x7401 } 984 }, 985 /* snc */ 986 { 987 { 0, 0, 0, 0 }, 988 { { MNEM, 0 } }, 989 & ifmt_nop, { 0x7501 } 990 }, 991 }; 992 993 #undef A 994 #undef MNEM 995 #undef OPERAND 996 #undef OP 997 998 /* Formats for ALIAS macro-insns. */ 999 1000 #define F(f) & m32r_cgen_ifld_table[CONCAT2 (M32R_,f)] 1001 1002 static const CGEN_IFMT ifmt_bc8r = { 1003 16, 16, 0xff00, { F (F_OP1), F (F_R1), F (F_DISP8), 0 } 1004 }; 1005 1006 static const CGEN_IFMT ifmt_bc24r = { 1007 32, 32, 0xff000000, { F (F_OP1), F (F_R1), F (F_DISP24), 0 } 1008 }; 1009 1010 static const CGEN_IFMT ifmt_bl8r = { 1011 16, 16, 0xff00, { F (F_OP1), F (F_R1), F (F_DISP8), 0 } 1012 }; 1013 1014 static const CGEN_IFMT ifmt_bl24r = { 1015 32, 32, 0xff000000, { F (F_OP1), F (F_R1), F (F_DISP24), 0 } 1016 }; 1017 1018 static const CGEN_IFMT ifmt_bcl8r = { 1019 16, 16, 0xff00, { F (F_OP1), F (F_R1), F (F_DISP8), 0 } 1020 }; 1021 1022 static const CGEN_IFMT ifmt_bcl24r = { 1023 32, 32, 0xff000000, { F (F_OP1), F (F_R1), F (F_DISP24), 0 } 1024 }; 1025 1026 static const CGEN_IFMT ifmt_bnc8r = { 1027 16, 16, 0xff00, { F (F_OP1), F (F_R1), F (F_DISP8), 0 } 1028 }; 1029 1030 static const CGEN_IFMT ifmt_bnc24r = { 1031 32, 32, 0xff000000, { F (F_OP1), F (F_R1), F (F_DISP24), 0 } 1032 }; 1033 1034 static const CGEN_IFMT ifmt_bra8r = { 1035 16, 16, 0xff00, { F (F_OP1), F (F_R1), F (F_DISP8), 0 } 1036 }; 1037 1038 static const CGEN_IFMT ifmt_bra24r = { 1039 32, 32, 0xff000000, { F (F_OP1), F (F_R1), F (F_DISP24), 0 } 1040 }; 1041 1042 static const CGEN_IFMT ifmt_bncl8r = { 1043 16, 16, 0xff00, { F (F_OP1), F (F_R1), F (F_DISP8), 0 } 1044 }; 1045 1046 static const CGEN_IFMT ifmt_bncl24r = { 1047 32, 32, 0xff000000, { F (F_OP1), F (F_R1), F (F_DISP24), 0 } 1048 }; 1049 1050 static const CGEN_IFMT ifmt_ld_2 = { 1051 16, 16, 0xf0f0, { F (F_OP1), F (F_OP2), F (F_R1), F (F_R2), 0 } 1052 }; 1053 1054 static const CGEN_IFMT ifmt_ld_d2 = { 1055 32, 32, 0xf0f00000, { F (F_OP1), F (F_OP2), F (F_R1), F (F_R2), F (F_SIMM16), 0 } 1056 }; 1057 1058 static const CGEN_IFMT ifmt_ldb_2 = { 1059 16, 16, 0xf0f0, { F (F_OP1), F (F_OP2), F (F_R1), F (F_R2), 0 } 1060 }; 1061 1062 static const CGEN_IFMT ifmt_ldb_d2 = { 1063 32, 32, 0xf0f00000, { F (F_OP1), F (F_OP2), F (F_R1), F (F_R2), F (F_SIMM16), 0 } 1064 }; 1065 1066 static const CGEN_IFMT ifmt_ldh_2 = { 1067 16, 16, 0xf0f0, { F (F_OP1), F (F_OP2), F (F_R1), F (F_R2), 0 } 1068 }; 1069 1070 static const CGEN_IFMT ifmt_ldh_d2 = { 1071 32, 32, 0xf0f00000, { F (F_OP1), F (F_OP2), F (F_R1), F (F_R2), F (F_SIMM16), 0 } 1072 }; 1073 1074 static const CGEN_IFMT ifmt_ldub_2 = { 1075 16, 16, 0xf0f0, { F (F_OP1), F (F_OP2), F (F_R1), F (F_R2), 0 } 1076 }; 1077 1078 static const CGEN_IFMT ifmt_ldub_d2 = { 1079 32, 32, 0xf0f00000, { F (F_OP1), F (F_OP2), F (F_R1), F (F_R2), F (F_SIMM16), 0 } 1080 }; 1081 1082 static const CGEN_IFMT ifmt_lduh_2 = { 1083 16, 16, 0xf0f0, { F (F_OP1), F (F_OP2), F (F_R1), F (F_R2), 0 } 1084 }; 1085 1086 static const CGEN_IFMT ifmt_lduh_d2 = { 1087 32, 32, 0xf0f00000, { F (F_OP1), F (F_OP2), F (F_R1), F (F_R2), F (F_SIMM16), 0 } 1088 }; 1089 1090 static const CGEN_IFMT ifmt_pop = { 1091 16, 16, 0xf0ff, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 } 1092 }; 1093 1094 static const CGEN_IFMT ifmt_ldi8a = { 1095 16, 16, 0xf000, { F (F_OP1), F (F_R1), F (F_SIMM8), 0 } 1096 }; 1097 1098 static const CGEN_IFMT ifmt_ldi16a = { 1099 32, 32, 0xf0ff0000, { F (F_OP1), F (F_OP2), F (F_R2), F (F_R1), F (F_SIMM16), 0 } 1100 }; 1101 1102 static const CGEN_IFMT ifmt_rac_d = { 1103 16, 16, 0xf3ff, { F (F_OP1), F (F_ACCD), F (F_BITS67), F (F_OP2), F (F_ACCS), F (F_BIT14), F (F_IMM1), 0 } 1104 }; 1105 1106 static const CGEN_IFMT ifmt_rac_ds = { 1107 16, 16, 0xf3f3, { F (F_OP1), F (F_ACCD), F (F_BITS67), F (F_OP2), F (F_ACCS), F (F_BIT14), F (F_IMM1), 0 } 1108 }; 1109 1110 static const CGEN_IFMT ifmt_rach_d = { 1111 16, 16, 0xf3ff, { F (F_OP1), F (F_ACCD), F (F_BITS67), F (F_OP2), F (F_ACCS), F (F_BIT14), F (F_IMM1), 0 } 1112 }; 1113 1114 static const CGEN_IFMT ifmt_rach_ds = { 1115 16, 16, 0xf3f3, { F (F_OP1), F (F_ACCD), F (F_BITS67), F (F_OP2), F (F_ACCS), F (F_BIT14), F (F_IMM1), 0 } 1116 }; 1117 1118 static const CGEN_IFMT ifmt_st_2 = { 1119 16, 16, 0xf0f0, { F (F_OP1), F (F_OP2), F (F_R1), F (F_R2), 0 } 1120 }; 1121 1122 static const CGEN_IFMT ifmt_st_d2 = { 1123 32, 32, 0xf0f00000, { F (F_OP1), F (F_OP2), F (F_R1), F (F_R2), F (F_SIMM16), 0 } 1124 }; 1125 1126 static const CGEN_IFMT ifmt_stb_2 = { 1127 16, 16, 0xf0f0, { F (F_OP1), F (F_OP2), F (F_R1), F (F_R2), 0 } 1128 }; 1129 1130 static const CGEN_IFMT ifmt_stb_d2 = { 1131 32, 32, 0xf0f00000, { F (F_OP1), F (F_OP2), F (F_R1), F (F_R2), F (F_SIMM16), 0 } 1132 }; 1133 1134 static const CGEN_IFMT ifmt_sth_2 = { 1135 16, 16, 0xf0f0, { F (F_OP1), F (F_OP2), F (F_R1), F (F_R2), 0 } 1136 }; 1137 1138 static const CGEN_IFMT ifmt_sth_d2 = { 1139 32, 32, 0xf0f00000, { F (F_OP1), F (F_OP2), F (F_R1), F (F_R2), F (F_SIMM16), 0 } 1140 }; 1141 1142 static const CGEN_IFMT ifmt_push = { 1143 16, 16, 0xf0ff, { F (F_OP1), F (F_OP2), F (F_R1), F (F_R2), 0 } 1144 }; 1145 1146 #undef F 1147 1148 /* Each non-simple macro entry points to an array of expansion possibilities. */ 1149 1150 #define A(a) (1 << CONCAT2 (CGEN_INSN_,a)) 1151 #define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */ 1152 #define OPERAND(op) CONCAT2 (M32R_OPERAND_,op) 1153 #define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field)) 1154 1155 /* The macro instruction table. */ 1156 1157 static const CGEN_IBASE m32r_cgen_macro_insn_table[] = 1158 { 1159 /* bc $disp8 */ 1160 { 1161 -1, "bc8r", "bc", 16, 1162 { 0|A(RELAXABLE)|A(COND_CTI)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } } 1163 }, 1164 /* bc $disp24 */ 1165 { 1166 -1, "bc24r", "bc", 32, 1167 { 0|A(RELAX)|A(COND_CTI)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } } 1168 }, 1169 /* bl $disp8 */ 1170 { 1171 -1, "bl8r", "bl", 16, 1172 { 0|A(RELAXABLE)|A(FILL_SLOT)|A(UNCOND_CTI)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } } 1173 }, 1174 /* bl $disp24 */ 1175 { 1176 -1, "bl24r", "bl", 32, 1177 { 0|A(RELAX)|A(UNCOND_CTI)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } } 1178 }, 1179 /* bcl $disp8 */ 1180 { 1181 -1, "bcl8r", "bcl", 16, 1182 { 0|A(RELAXABLE)|A(FILL_SLOT)|A(COND_CTI)|A(ALIAS), { (1<<MACH_M32RX), PIPE_O } } 1183 }, 1184 /* bcl $disp24 */ 1185 { 1186 -1, "bcl24r", "bcl", 32, 1187 { 0|A(RELAX)|A(COND_CTI)|A(ALIAS), { (1<<MACH_M32RX), PIPE_NONE } } 1188 }, 1189 /* bnc $disp8 */ 1190 { 1191 -1, "bnc8r", "bnc", 16, 1192 { 0|A(RELAXABLE)|A(COND_CTI)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } } 1193 }, 1194 /* bnc $disp24 */ 1195 { 1196 -1, "bnc24r", "bnc", 32, 1197 { 0|A(RELAX)|A(COND_CTI)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } } 1198 }, 1199 /* bra $disp8 */ 1200 { 1201 -1, "bra8r", "bra", 16, 1202 { 0|A(RELAXABLE)|A(FILL_SLOT)|A(UNCOND_CTI)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } } 1203 }, 1204 /* bra $disp24 */ 1205 { 1206 -1, "bra24r", "bra", 32, 1207 { 0|A(RELAX)|A(UNCOND_CTI)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } } 1208 }, 1209 /* bncl $disp8 */ 1210 { 1211 -1, "bncl8r", "bncl", 16, 1212 { 0|A(RELAXABLE)|A(FILL_SLOT)|A(COND_CTI)|A(ALIAS), { (1<<MACH_M32RX), PIPE_O } } 1213 }, 1214 /* bncl $disp24 */ 1215 { 1216 -1, "bncl24r", "bncl", 32, 1217 { 0|A(RELAX)|A(COND_CTI)|A(ALIAS), { (1<<MACH_M32RX), PIPE_NONE } } 1218 }, 1219 /* ld $dr,@($sr) */ 1220 { 1221 -1, "ld-2", "ld", 16, 1222 { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } } 1223 }, 1224 /* ld $dr,@($sr,$slo16) */ 1225 { 1226 -1, "ld-d2", "ld", 32, 1227 { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } } 1228 }, 1229 /* ldb $dr,@($sr) */ 1230 { 1231 -1, "ldb-2", "ldb", 16, 1232 { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } } 1233 }, 1234 /* ldb $dr,@($sr,$slo16) */ 1235 { 1236 -1, "ldb-d2", "ldb", 32, 1237 { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } } 1238 }, 1239 /* ldh $dr,@($sr) */ 1240 { 1241 -1, "ldh-2", "ldh", 16, 1242 { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } } 1243 }, 1244 /* ldh $dr,@($sr,$slo16) */ 1245 { 1246 -1, "ldh-d2", "ldh", 32, 1247 { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } } 1248 }, 1249 /* ldub $dr,@($sr) */ 1250 { 1251 -1, "ldub-2", "ldub", 16, 1252 { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } } 1253 }, 1254 /* ldub $dr,@($sr,$slo16) */ 1255 { 1256 -1, "ldub-d2", "ldub", 32, 1257 { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } } 1258 }, 1259 /* lduh $dr,@($sr) */ 1260 { 1261 -1, "lduh-2", "lduh", 16, 1262 { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } } 1263 }, 1264 /* lduh $dr,@($sr,$slo16) */ 1265 { 1266 -1, "lduh-d2", "lduh", 32, 1267 { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } } 1268 }, 1269 /* pop $dr */ 1270 { 1271 -1, "pop", "pop", 16, 1272 { 0|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } } 1273 }, 1274 /* ldi $dr,$simm8 */ 1275 { 1276 -1, "ldi8a", "ldi", 16, 1277 { 0|A(ALIAS), { (1<<MACH_BASE), PIPE_OS } } 1278 }, 1279 /* ldi $dr,$hash$slo16 */ 1280 { 1281 -1, "ldi16a", "ldi", 32, 1282 { 0|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } } 1283 }, 1284 /* rac $accd */ 1285 { 1286 -1, "rac-d", "rac", 16, 1287 { 0|A(ALIAS), { (1<<MACH_M32RX), PIPE_S } } 1288 }, 1289 /* rac $accd,$accs */ 1290 { 1291 -1, "rac-ds", "rac", 16, 1292 { 0|A(ALIAS), { (1<<MACH_M32RX), PIPE_S } } 1293 }, 1294 /* rach $accd */ 1295 { 1296 -1, "rach-d", "rach", 16, 1297 { 0|A(ALIAS), { (1<<MACH_M32RX), PIPE_S } } 1298 }, 1299 /* rach $accd,$accs */ 1300 { 1301 -1, "rach-ds", "rach", 16, 1302 { 0|A(ALIAS), { (1<<MACH_M32RX), PIPE_S } } 1303 }, 1304 /* st $src1,@($src2) */ 1305 { 1306 -1, "st-2", "st", 16, 1307 { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } } 1308 }, 1309 /* st $src1,@($src2,$slo16) */ 1310 { 1311 -1, "st-d2", "st", 32, 1312 { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } } 1313 }, 1314 /* stb $src1,@($src2) */ 1315 { 1316 -1, "stb-2", "stb", 16, 1317 { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } } 1318 }, 1319 /* stb $src1,@($src2,$slo16) */ 1320 { 1321 -1, "stb-d2", "stb", 32, 1322 { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } } 1323 }, 1324 /* sth $src1,@($src2) */ 1325 { 1326 -1, "sth-2", "sth", 16, 1327 { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } } 1328 }, 1329 /* sth $src1,@($src2,$slo16) */ 1330 { 1331 -1, "sth-d2", "sth", 32, 1332 { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } } 1333 }, 1334 /* push $src1 */ 1335 { 1336 -1, "push", "push", 16, 1337 { 0|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } } 1338 }, 1339 }; 1340 1341 /* The macro instruction opcode table. */ 1342 1343 static const CGEN_OPCODE m32r_cgen_macro_insn_opcode_table[] = 1344 { 1345 /* bc $disp8 */ 1346 { 1347 { 0, 0, 0, 0 }, 1348 { { MNEM, ' ', OP (DISP8), 0 } }, 1349 & ifmt_bc8r, { 0x7c00 } 1350 }, 1351 /* bc $disp24 */ 1352 { 1353 { 0, 0, 0, 0 }, 1354 { { MNEM, ' ', OP (DISP24), 0 } }, 1355 & ifmt_bc24r, { 0xfc000000 } 1356 }, 1357 /* bl $disp8 */ 1358 { 1359 { 0, 0, 0, 0 }, 1360 { { MNEM, ' ', OP (DISP8), 0 } }, 1361 & ifmt_bl8r, { 0x7e00 } 1362 }, 1363 /* bl $disp24 */ 1364 { 1365 { 0, 0, 0, 0 }, 1366 { { MNEM, ' ', OP (DISP24), 0 } }, 1367 & ifmt_bl24r, { 0xfe000000 } 1368 }, 1369 /* bcl $disp8 */ 1370 { 1371 { 0, 0, 0, 0 }, 1372 { { MNEM, ' ', OP (DISP8), 0 } }, 1373 & ifmt_bcl8r, { 0x7800 } 1374 }, 1375 /* bcl $disp24 */ 1376 { 1377 { 0, 0, 0, 0 }, 1378 { { MNEM, ' ', OP (DISP24), 0 } }, 1379 & ifmt_bcl24r, { 0xf8000000 } 1380 }, 1381 /* bnc $disp8 */ 1382 { 1383 { 0, 0, 0, 0 }, 1384 { { MNEM, ' ', OP (DISP8), 0 } }, 1385 & ifmt_bnc8r, { 0x7d00 } 1386 }, 1387 /* bnc $disp24 */ 1388 { 1389 { 0, 0, 0, 0 }, 1390 { { MNEM, ' ', OP (DISP24), 0 } }, 1391 & ifmt_bnc24r, { 0xfd000000 } 1392 }, 1393 /* bra $disp8 */ 1394 { 1395 { 0, 0, 0, 0 }, 1396 { { MNEM, ' ', OP (DISP8), 0 } }, 1397 & ifmt_bra8r, { 0x7f00 } 1398 }, 1399 /* bra $disp24 */ 1400 { 1401 { 0, 0, 0, 0 }, 1402 { { MNEM, ' ', OP (DISP24), 0 } }, 1403 & ifmt_bra24r, { 0xff000000 } 1404 }, 1405 /* bncl $disp8 */ 1406 { 1407 { 0, 0, 0, 0 }, 1408 { { MNEM, ' ', OP (DISP8), 0 } }, 1409 & ifmt_bncl8r, { 0x7900 } 1410 }, 1411 /* bncl $disp24 */ 1412 { 1413 { 0, 0, 0, 0 }, 1414 { { MNEM, ' ', OP (DISP24), 0 } }, 1415 & ifmt_bncl24r, { 0xf9000000 } 1416 }, 1417 /* ld $dr,@($sr) */ 1418 { 1419 { 0, 0, 0, 0 }, 1420 { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ')', 0 } }, 1421 & ifmt_ld_2, { 0x20c0 } 1422 }, 1423 /* ld $dr,@($sr,$slo16) */ 1424 { 1425 { 0, 0, 0, 0 }, 1426 { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ',', OP (SLO16), ')', 0 } }, 1427 & ifmt_ld_d2, { 0xa0c00000 } 1428 }, 1429 /* ldb $dr,@($sr) */ 1430 { 1431 { 0, 0, 0, 0 }, 1432 { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ')', 0 } }, 1433 & ifmt_ldb_2, { 0x2080 } 1434 }, 1435 /* ldb $dr,@($sr,$slo16) */ 1436 { 1437 { 0, 0, 0, 0 }, 1438 { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ',', OP (SLO16), ')', 0 } }, 1439 & ifmt_ldb_d2, { 0xa0800000 } 1440 }, 1441 /* ldh $dr,@($sr) */ 1442 { 1443 { 0, 0, 0, 0 }, 1444 { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ')', 0 } }, 1445 & ifmt_ldh_2, { 0x20a0 } 1446 }, 1447 /* ldh $dr,@($sr,$slo16) */ 1448 { 1449 { 0, 0, 0, 0 }, 1450 { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ',', OP (SLO16), ')', 0 } }, 1451 & ifmt_ldh_d2, { 0xa0a00000 } 1452 }, 1453 /* ldub $dr,@($sr) */ 1454 { 1455 { 0, 0, 0, 0 }, 1456 { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ')', 0 } }, 1457 & ifmt_ldub_2, { 0x2090 } 1458 }, 1459 /* ldub $dr,@($sr,$slo16) */ 1460 { 1461 { 0, 0, 0, 0 }, 1462 { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ',', OP (SLO16), ')', 0 } }, 1463 & ifmt_ldub_d2, { 0xa0900000 } 1464 }, 1465 /* lduh $dr,@($sr) */ 1466 { 1467 { 0, 0, 0, 0 }, 1468 { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ')', 0 } }, 1469 & ifmt_lduh_2, { 0x20b0 } 1470 }, 1471 /* lduh $dr,@($sr,$slo16) */ 1472 { 1473 { 0, 0, 0, 0 }, 1474 { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ',', OP (SLO16), ')', 0 } }, 1475 & ifmt_lduh_d2, { 0xa0b00000 } 1476 }, 1477 /* pop $dr */ 1478 { 1479 { 0, 0, 0, 0 }, 1480 { { MNEM, ' ', OP (DR), 0 } }, 1481 & ifmt_pop, { 0x20ef } 1482 }, 1483 /* ldi $dr,$simm8 */ 1484 { 1485 { 0, 0, 0, 0 }, 1486 { { MNEM, ' ', OP (DR), ',', OP (SIMM8), 0 } }, 1487 & ifmt_ldi8a, { 0x6000 } 1488 }, 1489 /* ldi $dr,$hash$slo16 */ 1490 { 1491 { 0, 0, 0, 0 }, 1492 { { MNEM, ' ', OP (DR), ',', OP (HASH), OP (SLO16), 0 } }, 1493 & ifmt_ldi16a, { 0x90f00000 } 1494 }, 1495 /* rac $accd */ 1496 { 1497 { 0, 0, 0, 0 }, 1498 { { MNEM, ' ', OP (ACCD), 0 } }, 1499 & ifmt_rac_d, { 0x5090 } 1500 }, 1501 /* rac $accd,$accs */ 1502 { 1503 { 0, 0, 0, 0 }, 1504 { { MNEM, ' ', OP (ACCD), ',', OP (ACCS), 0 } }, 1505 & ifmt_rac_ds, { 0x5090 } 1506 }, 1507 /* rach $accd */ 1508 { 1509 { 0, 0, 0, 0 }, 1510 { { MNEM, ' ', OP (ACCD), 0 } }, 1511 & ifmt_rach_d, { 0x5080 } 1512 }, 1513 /* rach $accd,$accs */ 1514 { 1515 { 0, 0, 0, 0 }, 1516 { { MNEM, ' ', OP (ACCD), ',', OP (ACCS), 0 } }, 1517 & ifmt_rach_ds, { 0x5080 } 1518 }, 1519 /* st $src1,@($src2) */ 1520 { 1521 { 0, 0, 0, 0 }, 1522 { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ')', 0 } }, 1523 & ifmt_st_2, { 0x2040 } 1524 }, 1525 /* st $src1,@($src2,$slo16) */ 1526 { 1527 { 0, 0, 0, 0 }, 1528 { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ',', OP (SLO16), ')', 0 } }, 1529 & ifmt_st_d2, { 0xa0400000 } 1530 }, 1531 /* stb $src1,@($src2) */ 1532 { 1533 { 0, 0, 0, 0 }, 1534 { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ')', 0 } }, 1535 & ifmt_stb_2, { 0x2000 } 1536 }, 1537 /* stb $src1,@($src2,$slo16) */ 1538 { 1539 { 0, 0, 0, 0 }, 1540 { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ',', OP (SLO16), ')', 0 } }, 1541 & ifmt_stb_d2, { 0xa0000000 } 1542 }, 1543 /* sth $src1,@($src2) */ 1544 { 1545 { 0, 0, 0, 0 }, 1546 { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ')', 0 } }, 1547 & ifmt_sth_2, { 0x2020 } 1548 }, 1549 /* sth $src1,@($src2,$slo16) */ 1550 { 1551 { 0, 0, 0, 0 }, 1552 { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ',', OP (SLO16), ')', 0 } }, 1553 & ifmt_sth_d2, { 0xa0200000 } 1554 }, 1555 /* push $src1 */ 1556 { 1557 { 0, 0, 0, 0 }, 1558 { { MNEM, ' ', OP (SRC1), 0 } }, 1559 & ifmt_push, { 0x207f } 1560 }, 1561 }; 1562 1563 #undef A 1564 #undef MNEM 1565 #undef OPERAND 1566 #undef OP 1567 1568 #ifndef CGEN_ASM_HASH_P 1569 #define CGEN_ASM_HASH_P(insn) 1 1570 #endif 1571 1572 #ifndef CGEN_DIS_HASH_P 1573 #define CGEN_DIS_HASH_P(insn) 1 1574 #endif 1575 1576 /* Return non-zero if INSN is to be added to the hash table. 1577 Targets are free to override CGEN_{ASM,DIS}_HASH_P in the .opc file. */ 1578 1579 static int 1580 asm_hash_insn_p (insn) 1581 const CGEN_INSN *insn; 1582 { 1583 return CGEN_ASM_HASH_P (insn); 1584 } 1585 1586 static int 1587 dis_hash_insn_p (insn) 1588 const CGEN_INSN *insn; 1589 { 1590 /* If building the hash table and the NO-DIS attribute is present, 1591 ignore. */ 1592 if (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_NO_DIS)) 1593 return 0; 1594 return CGEN_DIS_HASH_P (insn); 1595 } 1596 1597 #ifndef CGEN_ASM_HASH 1598 #define CGEN_ASM_HASH_SIZE 127 1599 #ifdef CGEN_MNEMONIC_OPERANDS 1600 #define CGEN_ASM_HASH(mnem) (*(unsigned char *) (mnem) % CGEN_ASM_HASH_SIZE) 1601 #else 1602 #define CGEN_ASM_HASH(mnem) (*(unsigned char *) (mnem) % CGEN_ASM_HASH_SIZE) /*FIXME*/ 1603 #endif 1604 #endif 1605 1606 /* It doesn't make much sense to provide a default here, 1607 but while this is under development we do. 1608 BUFFER is a pointer to the bytes of the insn, target order. 1609 VALUE is the first base_insn_bitsize bits as an int in host order. */ 1610 1611 #ifndef CGEN_DIS_HASH 1612 #define CGEN_DIS_HASH_SIZE 256 1613 #define CGEN_DIS_HASH(buf, value) (*(unsigned char *) (buf)) 1614 #endif 1615 1616 /* The result is the hash value of the insn. 1617 Targets are free to override CGEN_{ASM,DIS}_HASH in the .opc file. */ 1618 1619 static unsigned int 1620 asm_hash_insn (mnem) 1621 const char * mnem; 1622 { 1623 return CGEN_ASM_HASH (mnem); 1624 } 1625 1626 /* BUF is a pointer to the bytes of the insn, target order. 1627 VALUE is the first base_insn_bitsize bits as an int in host order. */ 1628 1629 static unsigned int 1630 dis_hash_insn (buf, value) 1631 const char * buf; 1632 CGEN_INSN_INT value; 1633 { 1634 return CGEN_DIS_HASH (buf, value); 1635 } 1636 1637 /* Set the recorded length of the insn in the CGEN_FIELDS struct. */ 1638 1639 static void 1640 set_fields_bitsize (fields, size) 1641 CGEN_FIELDS *fields; 1642 int size; 1643 { 1644 CGEN_FIELDS_BITSIZE (fields) = size; 1645 } 1646 1647 /* Function to call before using the operand instance table. 1648 This plugs the opcode entries and macro instructions into the cpu table. */ 1649 1650 void 1651 m32r_cgen_init_opcode_table (cd) 1652 CGEN_CPU_DESC cd; 1653 { 1654 int i; 1655 int num_macros = (sizeof (m32r_cgen_macro_insn_table) / 1656 sizeof (m32r_cgen_macro_insn_table[0])); 1657 const CGEN_IBASE *ib = & m32r_cgen_macro_insn_table[0]; 1658 const CGEN_OPCODE *oc = & m32r_cgen_macro_insn_opcode_table[0]; 1659 CGEN_INSN *insns = (CGEN_INSN *) xmalloc (num_macros * sizeof (CGEN_INSN)); 1660 memset (insns, 0, num_macros * sizeof (CGEN_INSN)); 1661 for (i = 0; i < num_macros; ++i) 1662 { 1663 insns[i].base = &ib[i]; 1664 insns[i].opcode = &oc[i]; 1665 } 1666 cd->macro_insn_table.init_entries = insns; 1667 cd->macro_insn_table.entry_size = sizeof (CGEN_IBASE); 1668 cd->macro_insn_table.num_init_entries = num_macros; 1669 1670 oc = & m32r_cgen_insn_opcode_table[0]; 1671 insns = (CGEN_INSN *) cd->insn_table.init_entries; 1672 for (i = 0; i < MAX_INSNS; ++i) 1673 insns[i].opcode = &oc[i]; 1674 1675 cd->sizeof_fields = sizeof (CGEN_FIELDS); 1676 cd->set_fields_bitsize = set_fields_bitsize; 1677 1678 cd->asm_hash_p = asm_hash_insn_p; 1679 cd->asm_hash = asm_hash_insn; 1680 cd->asm_hash_size = CGEN_ASM_HASH_SIZE; 1681 1682 cd->dis_hash_p = dis_hash_insn_p; 1683 cd->dis_hash = dis_hash_insn; 1684 cd->dis_hash_size = CGEN_DIS_HASH_SIZE; 1685 } 1686