1 /* Instruction printing code for the ARM 2 Copyright (C) 1994, 95, 96, 97, 98, 99, 2000 Free Software Foundation, Inc. 3 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org) 4 Modification by James G. Smith (jsmith@cygnus.co.uk) 5 6 This file is part of libopcodes. 7 8 This program is free software; you can redistribute it and/or modify it under 9 the terms of the GNU General Public License as published by the Free 10 Software Foundation; either version 2 of the License, or (at your option) 11 any later version. 12 13 This program is distributed in the hope that it will be useful, but WITHOUT 14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 16 more details. 17 18 You should have received a copy of the GNU General Public License 19 along with this program; if not, write to the Free Software 20 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ 21 22 #include "sysdep.h" 23 #include "dis-asm.h" 24 #define DEFINE_TABLE 25 #include "arm-opc.h" 26 #include "coff/internal.h" 27 #include "libcoff.h" 28 #include "opintl.h" 29 30 /* FIXME: This shouldn't be done here */ 31 #include "elf-bfd.h" 32 #include "elf/internal.h" 33 #include "elf/arm.h" 34 35 #ifndef streq 36 #define streq(a,b) (strcmp ((a), (b)) == 0) 37 #endif 38 39 #ifndef strneq 40 #define strneq(a,b,n) (strncmp ((a), (b), (n)) == 0) 41 #endif 42 43 #ifndef NUM_ELEM 44 #define NUM_ELEM(a) (sizeof (a) / sizeof (a)[0]) 45 #endif 46 47 static char * arm_conditional[] = 48 {"eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc", 49 "hi", "ls", "ge", "lt", "gt", "le", "", "nv"}; 50 51 typedef struct 52 { 53 const char * name; 54 const char * description; 55 const char * reg_names[16]; 56 } 57 arm_regname; 58 59 static arm_regname regnames[] = 60 { 61 { "raw" , "Select raw register names", 62 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"}}, 63 { "std", "Select register names used in ARM's ISA documentation", 64 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc" }}, 65 { "apcs", "Select register names used in the APCS", 66 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "sl", "fp", "ip", "sp", "lr", "pc" }}, 67 { "atpcs", "Select register names used in the ATPCS", 68 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "IP", "SP", "LR", "PC" }}, 69 { "special-atpcs", "Select special register names used in the ATPCS", 70 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "WR", "v5", "SB", "SL", "FP", "IP", "SP", "LR", "PC" }} 71 }; 72 73 /* Default to standard register name set. */ 74 static unsigned int regname_selected = 1; 75 76 #define NUM_ARM_REGNAMES NUM_ELEM (regnames) 77 #define arm_regnames regnames[regname_selected].reg_names 78 79 static boolean force_thumb = false; 80 81 static char * arm_fp_const[] = 82 {"0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0"}; 83 84 static char * arm_shift[] = 85 {"lsl", "lsr", "asr", "ror"}; 86 87 /* Forward declarations. */ 88 static void arm_decode_shift PARAMS ((long, fprintf_ftype, void *)); 89 static int print_insn_arm PARAMS ((bfd_vma, struct disassemble_info *, long)); 90 static int print_insn_thumb PARAMS ((bfd_vma, struct disassemble_info *, long)); 91 static void parse_disassembler_options PARAMS ((char *)); 92 static int print_insn PARAMS ((bfd_vma, struct disassemble_info *, boolean)); 93 int get_arm_regname_num_options (void); 94 int set_arm_regname_option (int option); 95 int get_arm_regnames (int option, const char **setname, 96 const char **setdescription, 97 const char ***register_names); 98 99 /* Functions. */ 100 int 101 get_arm_regname_num_options (void) 102 { 103 return NUM_ARM_REGNAMES; 104 } 105 106 int 107 set_arm_regname_option (int option) 108 { 109 int old = regname_selected; 110 regname_selected = option; 111 return old; 112 } 113 114 int 115 get_arm_regnames (int option, const char **setname, 116 const char **setdescription, 117 const char ***register_names) 118 { 119 *setname = regnames[option].name; 120 *setdescription = regnames[option].description; 121 *register_names = regnames[option].reg_names; 122 return 16; 123 } 124 125 static void 126 arm_decode_shift (given, func, stream) 127 long given; 128 fprintf_ftype func; 129 void * stream; 130 { 131 func (stream, "%s", arm_regnames[given & 0xf]); 132 133 if ((given & 0xff0) != 0) 134 { 135 if ((given & 0x10) == 0) 136 { 137 int amount = (given & 0xf80) >> 7; 138 int shift = (given & 0x60) >> 5; 139 140 if (amount == 0) 141 { 142 if (shift == 3) 143 { 144 func (stream, ", rrx"); 145 return; 146 } 147 148 amount = 32; 149 } 150 151 func (stream, ", %s #%d", arm_shift[shift], amount); 152 } 153 else 154 func (stream, ", %s %s", arm_shift[(given & 0x60) >> 5], 155 arm_regnames[(given & 0xf00) >> 8]); 156 } 157 } 158 159 /* Print one instruction from PC on INFO->STREAM. 160 Return the size of the instruction (always 4 on ARM). */ 161 static int 162 print_insn_arm (pc, info, given) 163 bfd_vma pc; 164 struct disassemble_info * info; 165 long given; 166 { 167 struct arm_opcode * insn; 168 void * stream = info->stream; 169 fprintf_ftype func = info->fprintf_func; 170 171 for (insn = arm_opcodes; insn->assembler; insn++) 172 { 173 if ((given & insn->mask) == insn->value) 174 { 175 char * c; 176 177 for (c = insn->assembler; *c; c++) 178 { 179 if (*c == '%') 180 { 181 switch (*++c) 182 { 183 case '%': 184 func (stream, "%%"); 185 break; 186 187 case 'a': 188 if (((given & 0x000f0000) == 0x000f0000) 189 && ((given & 0x02000000) == 0)) 190 { 191 int offset = given & 0xfff; 192 193 func (stream, "[pc"); 194 195 if (given & 0x01000000) 196 { 197 if ((given & 0x00800000) == 0) 198 offset = - offset; 199 200 /* pre-indexed */ 201 func (stream, ", #%x]", offset); 202 203 offset += pc + 8; 204 205 /* Cope with the possibility of write-back 206 being used. Probably a very dangerous thing 207 for the programmer to do, but who are we to 208 argue ? */ 209 if (given & 0x00200000) 210 func (stream, "!"); 211 } 212 else 213 { 214 /* Post indexed. */ 215 func (stream, "], #%x", offset); 216 217 offset = pc + 8; /* ie ignore the offset. */ 218 } 219 220 func (stream, "\t; "); 221 info->print_address_func (offset, info); 222 } 223 else 224 { 225 func (stream, "[%s", 226 arm_regnames[(given >> 16) & 0xf]); 227 if ((given & 0x01000000) != 0) 228 { 229 if ((given & 0x02000000) == 0) 230 { 231 int offset = given & 0xfff; 232 if (offset) 233 func (stream, ", %s#%d", 234 (((given & 0x00800000) == 0) 235 ? "-" : ""), offset); 236 } 237 else 238 { 239 func (stream, ", %s", 240 (((given & 0x00800000) == 0) 241 ? "-" : "")); 242 arm_decode_shift (given, func, stream); 243 } 244 245 func (stream, "]%s", 246 ((given & 0x00200000) != 0) ? "!" : ""); 247 } 248 else 249 { 250 if ((given & 0x02000000) == 0) 251 { 252 int offset = given & 0xfff; 253 if (offset) 254 func (stream, "], %s#%d", 255 (((given & 0x00800000) == 0) 256 ? "-" : ""), offset); 257 else 258 func (stream, "]"); 259 } 260 else 261 { 262 func (stream, "], %s", 263 (((given & 0x00800000) == 0) 264 ? "-" : "")); 265 arm_decode_shift (given, func, stream); 266 } 267 } 268 } 269 break; 270 271 case 's': 272 if ((given & 0x004f0000) == 0x004f0000) 273 { 274 /* PC relative with immediate offset. */ 275 int offset = ((given & 0xf00) >> 4) | (given & 0xf); 276 277 if ((given & 0x00800000) == 0) 278 offset = -offset; 279 280 func (stream, "[pc, #%x]\t; ", offset); 281 282 (*info->print_address_func) 283 (offset + pc + 8, info); 284 } 285 else 286 { 287 func (stream, "[%s", 288 arm_regnames[(given >> 16) & 0xf]); 289 if ((given & 0x01000000) != 0) 290 { 291 /* Pre-indexed. */ 292 if ((given & 0x00400000) == 0x00400000) 293 { 294 /* Immediate. */ 295 int offset = ((given & 0xf00) >> 4) | (given & 0xf); 296 if (offset) 297 func (stream, ", %s#%d", 298 (((given & 0x00800000) == 0) 299 ? "-" : ""), offset); 300 } 301 else 302 { 303 /* Register. */ 304 func (stream, ", %s%s", 305 (((given & 0x00800000) == 0) 306 ? "-" : ""), 307 arm_regnames[given & 0xf]); 308 } 309 310 func (stream, "]%s", 311 ((given & 0x00200000) != 0) ? "!" : ""); 312 } 313 else 314 { 315 /* Post-indexed. */ 316 if ((given & 0x00400000) == 0x00400000) 317 { 318 /* Immediate. */ 319 int offset = ((given & 0xf00) >> 4) | (given & 0xf); 320 if (offset) 321 func (stream, "], %s#%d", 322 (((given & 0x00800000) == 0) 323 ? "-" : ""), offset); 324 else 325 func (stream, "]"); 326 } 327 else 328 { 329 /* Register. */ 330 func (stream, "], %s%s", 331 (((given & 0x00800000) == 0) 332 ? "-" : ""), 333 arm_regnames[given & 0xf]); 334 } 335 } 336 } 337 break; 338 339 case 'b': 340 (*info->print_address_func) 341 (BDISP (given) * 4 + pc + 8, info); 342 break; 343 344 case 'c': 345 func (stream, "%s", 346 arm_conditional [(given >> 28) & 0xf]); 347 break; 348 349 case 'm': 350 { 351 int started = 0; 352 int reg; 353 354 func (stream, "{"); 355 for (reg = 0; reg < 16; reg++) 356 if ((given & (1 << reg)) != 0) 357 { 358 if (started) 359 func (stream, ", "); 360 started = 1; 361 func (stream, "%s", arm_regnames[reg]); 362 } 363 func (stream, "}"); 364 } 365 break; 366 367 case 'o': 368 if ((given & 0x02000000) != 0) 369 { 370 int rotate = (given & 0xf00) >> 7; 371 int immed = (given & 0xff); 372 immed = (((immed << (32 - rotate)) 373 | (immed >> rotate)) & 0xffffffff); 374 func (stream, "#%d\t; 0x%x", immed, immed); 375 } 376 else 377 arm_decode_shift (given, func, stream); 378 break; 379 380 case 'p': 381 if ((given & 0x0000f000) == 0x0000f000) 382 func (stream, "p"); 383 break; 384 385 case 't': 386 if ((given & 0x01200000) == 0x00200000) 387 func (stream, "t"); 388 break; 389 390 case 'h': 391 if ((given & 0x00000020) == 0x00000020) 392 func (stream, "h"); 393 else 394 func (stream, "b"); 395 break; 396 397 case 'A': 398 func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]); 399 if ((given & 0x01000000) != 0) 400 { 401 int offset = given & 0xff; 402 if (offset) 403 func (stream, ", %s#%d]%s", 404 ((given & 0x00800000) == 0 ? "-" : ""), 405 offset * 4, 406 ((given & 0x00200000) != 0 ? "!" : "")); 407 else 408 func (stream, "]"); 409 } 410 else 411 { 412 int offset = given & 0xff; 413 if (offset) 414 func (stream, "], %s#%d", 415 ((given & 0x00800000) == 0 ? "-" : ""), 416 offset * 4); 417 else 418 func (stream, "]"); 419 } 420 break; 421 422 case 'C': 423 switch (given & 0x000f0000) 424 { 425 default: 426 func (stream, "_???"); 427 break; 428 case 0x90000: 429 func (stream, "_all"); 430 break; 431 case 0x10000: 432 func (stream, "_c"); 433 break; 434 case 0x20000: 435 func (stream, "_x"); 436 break; 437 case 0x40000: 438 func (stream, "_s"); 439 break; 440 case 0x80000: 441 func (stream, "_f"); 442 break; 443 } 444 break; 445 446 case 'F': 447 switch (given & 0x00408000) 448 { 449 case 0: 450 func (stream, "4"); 451 break; 452 case 0x8000: 453 func (stream, "1"); 454 break; 455 case 0x00400000: 456 func (stream, "2"); 457 break; 458 default: 459 func (stream, "3"); 460 } 461 break; 462 463 case 'P': 464 switch (given & 0x00080080) 465 { 466 case 0: 467 func (stream, "s"); 468 break; 469 case 0x80: 470 func (stream, "d"); 471 break; 472 case 0x00080000: 473 func (stream, "e"); 474 break; 475 default: 476 func (stream, _("<illegal precision>")); 477 break; 478 } 479 break; 480 case 'Q': 481 switch (given & 0x00408000) 482 { 483 case 0: 484 func (stream, "s"); 485 break; 486 case 0x8000: 487 func (stream, "d"); 488 break; 489 case 0x00400000: 490 func (stream, "e"); 491 break; 492 default: 493 func (stream, "p"); 494 break; 495 } 496 break; 497 case 'R': 498 switch (given & 0x60) 499 { 500 case 0: 501 break; 502 case 0x20: 503 func (stream, "p"); 504 break; 505 case 0x40: 506 func (stream, "m"); 507 break; 508 default: 509 func (stream, "z"); 510 break; 511 } 512 break; 513 514 case '0': case '1': case '2': case '3': case '4': 515 case '5': case '6': case '7': case '8': case '9': 516 { 517 int bitstart = *c++ - '0'; 518 int bitend = 0; 519 while (*c >= '0' && *c <= '9') 520 bitstart = (bitstart * 10) + *c++ - '0'; 521 522 switch (*c) 523 { 524 case '-': 525 c++; 526 527 while (*c >= '0' && *c <= '9') 528 bitend = (bitend * 10) + *c++ - '0'; 529 530 if (!bitend) 531 abort (); 532 533 switch (*c) 534 { 535 case 'r': 536 { 537 long reg; 538 539 reg = given >> bitstart; 540 reg &= (2 << (bitend - bitstart)) - 1; 541 542 func (stream, "%s", arm_regnames[reg]); 543 } 544 break; 545 case 'd': 546 { 547 long reg; 548 549 reg = given >> bitstart; 550 reg &= (2 << (bitend - bitstart)) - 1; 551 552 func (stream, "%d", reg); 553 } 554 break; 555 case 'x': 556 { 557 long reg; 558 559 reg = given >> bitstart; 560 reg &= (2 << (bitend - bitstart)) - 1; 561 562 func (stream, "0x%08x", reg); 563 564 /* Some SWI instructions have special 565 meanings. */ 566 if ((given & 0x0fffffff) == 0x0FF00000) 567 func (stream, "\t; IMB"); 568 else if ((given & 0x0fffffff) == 0x0FF00001) 569 func (stream, "\t; IMBRange"); 570 } 571 break; 572 case 'X': 573 { 574 long reg; 575 576 reg = given >> bitstart; 577 reg &= (2 << (bitend - bitstart)) - 1; 578 579 func (stream, "%01x", reg & 0xf); 580 } 581 break; 582 case 'f': 583 { 584 long reg; 585 586 reg = given >> bitstart; 587 reg &= (2 << (bitend - bitstart)) - 1; 588 589 if (reg > 7) 590 func (stream, "#%s", 591 arm_fp_const[reg & 7]); 592 else 593 func (stream, "f%d", reg); 594 } 595 break; 596 default: 597 abort (); 598 } 599 break; 600 601 case '`': 602 c++; 603 if ((given & (1 << bitstart)) == 0) 604 func (stream, "%c", *c); 605 break; 606 case '\'': 607 c++; 608 if ((given & (1 << bitstart)) != 0) 609 func (stream, "%c", *c); 610 break; 611 case '?': 612 ++c; 613 if ((given & (1 << bitstart)) != 0) 614 func (stream, "%c", *c++); 615 else 616 func (stream, "%c", *++c); 617 break; 618 default: 619 abort (); 620 } 621 break; 622 623 default: 624 abort (); 625 } 626 } 627 } 628 else 629 func (stream, "%c", *c); 630 } 631 return 4; 632 } 633 } 634 abort (); 635 } 636 637 /* Print one instruction from PC on INFO->STREAM. 638 Return the size of the instruction. */ 639 static int 640 print_insn_thumb (pc, info, given) 641 bfd_vma pc; 642 struct disassemble_info * info; 643 long given; 644 { 645 struct thumb_opcode * insn; 646 void * stream = info->stream; 647 fprintf_ftype func = info->fprintf_func; 648 649 for (insn = thumb_opcodes; insn->assembler; insn++) 650 { 651 if ((given & insn->mask) == insn->value) 652 { 653 char * c = insn->assembler; 654 655 /* Special processing for Thumb 2 instruction BL sequence: */ 656 if (!*c) /* Check for empty (not NULL) assembler string. */ 657 { 658 info->bytes_per_chunk = 4; 659 info->bytes_per_line = 4; 660 661 func (stream, "bl\t"); 662 663 info->print_address_func (BDISP23 (given) * 2 + pc + 4, info); 664 return 4; 665 } 666 else 667 { 668 info->bytes_per_chunk = 2; 669 info->bytes_per_line = 4; 670 671 given &= 0xffff; 672 673 for (; *c; c++) 674 { 675 if (*c == '%') 676 { 677 int domaskpc = 0; 678 int domasklr = 0; 679 680 switch (*++c) 681 { 682 case '%': 683 func (stream, "%%"); 684 break; 685 686 case 'S': 687 { 688 long reg; 689 690 reg = (given >> 3) & 0x7; 691 if (given & (1 << 6)) 692 reg += 8; 693 694 func (stream, "%s", arm_regnames[reg]); 695 } 696 break; 697 698 case 'D': 699 { 700 long reg; 701 702 reg = given & 0x7; 703 if (given & (1 << 7)) 704 reg += 8; 705 706 func (stream, "%s", arm_regnames[reg]); 707 } 708 break; 709 710 case 'T': 711 func (stream, "%s", 712 arm_conditional [(given >> 8) & 0xf]); 713 break; 714 715 case 'N': 716 if (given & (1 << 8)) 717 domasklr = 1; 718 /* Fall through. */ 719 case 'O': 720 if (*c == 'O' && (given & (1 << 8))) 721 domaskpc = 1; 722 /* Fall through. */ 723 case 'M': 724 { 725 int started = 0; 726 int reg; 727 728 func (stream, "{"); 729 730 /* It would be nice if we could spot 731 ranges, and generate the rS-rE format: */ 732 for (reg = 0; (reg < 8); reg++) 733 if ((given & (1 << reg)) != 0) 734 { 735 if (started) 736 func (stream, ", "); 737 started = 1; 738 func (stream, "%s", arm_regnames[reg]); 739 } 740 741 if (domasklr) 742 { 743 if (started) 744 func (stream, ", "); 745 started = 1; 746 func (stream, arm_regnames[14] /* "lr" */); 747 } 748 749 if (domaskpc) 750 { 751 if (started) 752 func (stream, ", "); 753 func (stream, arm_regnames[15] /* "pc" */); 754 } 755 756 func (stream, "}"); 757 } 758 break; 759 760 761 case '0': case '1': case '2': case '3': case '4': 762 case '5': case '6': case '7': case '8': case '9': 763 { 764 int bitstart = *c++ - '0'; 765 int bitend = 0; 766 767 while (*c >= '0' && *c <= '9') 768 bitstart = (bitstart * 10) + *c++ - '0'; 769 770 switch (*c) 771 { 772 case '-': 773 { 774 long reg; 775 776 c++; 777 while (*c >= '0' && *c <= '9') 778 bitend = (bitend * 10) + *c++ - '0'; 779 if (!bitend) 780 abort (); 781 reg = given >> bitstart; 782 reg &= (2 << (bitend - bitstart)) - 1; 783 switch (*c) 784 { 785 case 'r': 786 func (stream, "%s", arm_regnames[reg]); 787 break; 788 789 case 'd': 790 func (stream, "%d", reg); 791 break; 792 793 case 'H': 794 func (stream, "%d", reg << 1); 795 break; 796 797 case 'W': 798 func (stream, "%d", reg << 2); 799 break; 800 801 case 'a': 802 /* PC-relative address -- the bottom two 803 bits of the address are dropped 804 before the calculation. */ 805 info->print_address_func 806 (((pc + 4) & ~3) + (reg << 2), info); 807 break; 808 809 case 'x': 810 func (stream, "0x%04x", reg); 811 break; 812 813 case 'I': 814 reg = ((reg ^ (1 << bitend)) - (1 << bitend)); 815 func (stream, "%d", reg); 816 break; 817 818 case 'B': 819 reg = ((reg ^ (1 << bitend)) - (1 << bitend)); 820 (*info->print_address_func) 821 (reg * 2 + pc + 4, info); 822 break; 823 824 default: 825 abort (); 826 } 827 } 828 break; 829 830 case '\'': 831 c++; 832 if ((given & (1 << bitstart)) != 0) 833 func (stream, "%c", *c); 834 break; 835 836 case '?': 837 ++c; 838 if ((given & (1 << bitstart)) != 0) 839 func (stream, "%c", *c++); 840 else 841 func (stream, "%c", *++c); 842 break; 843 844 default: 845 abort (); 846 } 847 } 848 break; 849 850 default: 851 abort (); 852 } 853 } 854 else 855 func (stream, "%c", *c); 856 } 857 } 858 return 2; 859 } 860 } 861 862 /* No match. */ 863 abort (); 864 } 865 866 /* Parse an individual disassembler option. */ 867 void 868 parse_arm_disassembler_option (option) 869 char * option; 870 { 871 if (option == NULL) 872 return; 873 874 if (strneq (option, "reg-names-", 10)) 875 { 876 int i; 877 878 option += 10; 879 880 for (i = NUM_ARM_REGNAMES; i--;) 881 if (streq (option, regnames[i].name)) 882 { 883 regname_selected = i; 884 break; 885 } 886 887 if (i < 0) 888 fprintf (stderr, _("Unrecognised register name set: %s\n"), option); 889 } 890 else if (streq (option, "force-thumb")) 891 force_thumb = 1; 892 else if (streq (option, "no-force-thumb")) 893 force_thumb = 0; 894 else 895 fprintf (stderr, _("Unrecognised disassembler option: %s\n"), option); 896 897 return; 898 } 899 900 /* Parse the string of disassembler options, spliting it at whitespaces. */ 901 static void 902 parse_disassembler_options (options) 903 char * options; 904 { 905 char * space; 906 907 if (options == NULL) 908 return; 909 910 do 911 { 912 space = strchr (options, ' '); 913 914 if (space) 915 { 916 * space = '\0'; 917 parse_arm_disassembler_option (options); 918 * space = ' '; 919 options = space + 1; 920 } 921 else 922 parse_arm_disassembler_option (options); 923 } 924 while (space); 925 } 926 927 /* NOTE: There are no checks in these routines that 928 the relevant number of data bytes exist. */ 929 static int 930 print_insn (pc, info, little) 931 bfd_vma pc; 932 struct disassemble_info * info; 933 boolean little; 934 { 935 unsigned char b[4]; 936 long given; 937 int status; 938 int is_thumb; 939 940 if (info->disassembler_options) 941 { 942 parse_disassembler_options (info->disassembler_options); 943 944 /* To avoid repeated parsing of these options, we remove them here. */ 945 info->disassembler_options = NULL; 946 } 947 948 is_thumb = force_thumb; 949 950 if (!is_thumb && info->symbols != NULL) 951 { 952 if (bfd_asymbol_flavour (*info->symbols) == bfd_target_coff_flavour) 953 { 954 coff_symbol_type * cs; 955 956 cs = coffsymbol (*info->symbols); 957 is_thumb = ( cs->native->u.syment.n_sclass == C_THUMBEXT 958 || cs->native->u.syment.n_sclass == C_THUMBSTAT 959 || cs->native->u.syment.n_sclass == C_THUMBLABEL 960 || cs->native->u.syment.n_sclass == C_THUMBEXTFUNC 961 || cs->native->u.syment.n_sclass == C_THUMBSTATFUNC); 962 } 963 else if (bfd_asymbol_flavour (*info->symbols) == bfd_target_elf_flavour) 964 { 965 elf_symbol_type * es; 966 unsigned int type; 967 968 es = *(elf_symbol_type **)(info->symbols); 969 type = ELF_ST_TYPE (es->internal_elf_sym.st_info); 970 971 is_thumb = (type == STT_ARM_TFUNC) || (type == STT_ARM_16BIT); 972 } 973 } 974 975 info->bytes_per_chunk = 4; 976 info->display_endian = little ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG; 977 978 if (little) 979 { 980 status = info->read_memory_func (pc, (bfd_byte *) &b[0], 4, info); 981 if (status != 0 && is_thumb) 982 { 983 info->bytes_per_chunk = 2; 984 985 status = info->read_memory_func (pc, (bfd_byte *) b, 2, info); 986 b[3] = b[2] = 0; 987 } 988 989 if (status != 0) 990 { 991 info->memory_error_func (status, pc, info); 992 return -1; 993 } 994 995 given = (b[0]) | (b[1] << 8) | (b[2] << 16) | (b[3] << 24); 996 } 997 else 998 { 999 status = info->read_memory_func 1000 (pc & ~ 0x3, (bfd_byte *) &b[0], 4, info); 1001 if (status != 0) 1002 { 1003 info->memory_error_func (status, pc, info); 1004 return -1; 1005 } 1006 1007 if (is_thumb) 1008 { 1009 if (pc & 0x2) 1010 { 1011 given = (b[2] << 8) | b[3]; 1012 1013 status = info->read_memory_func 1014 ((pc + 4) & ~ 0x3, (bfd_byte *) b, 4, info); 1015 if (status != 0) 1016 { 1017 info->memory_error_func (status, pc + 4, info); 1018 return -1; 1019 } 1020 1021 given |= (b[0] << 24) | (b[1] << 16); 1022 } 1023 else 1024 given = (b[0] << 8) | b[1] | (b[2] << 24) | (b[3] << 16); 1025 } 1026 else 1027 given = (b[0] << 24) | (b[1] << 16) | (b[2] << 8) | (b[3]); 1028 } 1029 1030 if (is_thumb) 1031 status = print_insn_thumb (pc, info, given); 1032 else 1033 status = print_insn_arm (pc, info, given); 1034 1035 return status; 1036 } 1037 1038 int 1039 print_insn_big_arm (pc, info) 1040 bfd_vma pc; 1041 struct disassemble_info * info; 1042 { 1043 return print_insn (pc, info, false); 1044 } 1045 1046 int 1047 print_insn_little_arm (pc, info) 1048 bfd_vma pc; 1049 struct disassemble_info * info; 1050 { 1051 return print_insn (pc, info, true); 1052 } 1053 1054 void 1055 print_arm_disassembler_options (FILE * stream) 1056 { 1057 int i; 1058 1059 fprintf (stream, _("\n\ 1060 The following ARM specific disassembler options are supported for use with\n\ 1061 the -M switch:\n")); 1062 1063 for (i = NUM_ARM_REGNAMES; i--;) 1064 fprintf (stream, " reg-names-%s %*c%s\n", 1065 regnames[i].name, 1066 14 - strlen (regnames[i].name), ' ', 1067 regnames[i].description); 1068 1069 fprintf (stream, " force-thumb Assume all insns are Thumb insns\n"); 1070 fprintf (stream, " no-force-thumb Examine preceeding label to determine an insn's type\n\n"); 1071 } 1072