1 /* mips.h. Mips opcode list for GDB, the GNU debugger. 2 Copyright 1993, 94, 95, 96, 1997 Free Software Foundation, Inc. 3 Contributed by Ralph Campbell and OSF 4 Commented and modified by Ian Lance Taylor, Cygnus Support 5 6 This file is part of GDB, GAS, and the GNU binutils. 7 8 GDB, GAS, and the GNU binutils are free software; you can redistribute 9 them and/or modify them under the terms of the GNU General Public 10 License as published by the Free Software Foundation; either version 11 1, or (at your option) any later version. 12 13 GDB, GAS, and the GNU binutils are distributed in the hope that they 14 will be useful, but WITHOUT ANY WARRANTY; without even the implied 15 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See 16 the GNU General Public License for more details. 17 18 You should have received a copy of the GNU General Public License 19 along with this file; see the file COPYING. If not, write to the Free 20 Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ 21 22 #ifndef _MIPS_H_ 23 #define _MIPS_H_ 24 25 /* These are bit masks and shift counts to use to access the various 26 fields of an instruction. To retrieve the X field of an 27 instruction, use the expression 28 (i >> OP_SH_X) & OP_MASK_X 29 To set the same field (to j), use 30 i = (i &~ (OP_MASK_X << OP_SH_X)) | (j << OP_SH_X) 31 32 Make sure you use fields that are appropriate for the instruction, 33 of course. 34 35 The 'i' format uses OP, RS, RT and IMMEDIATE. 36 37 The 'j' format uses OP and TARGET. 38 39 The 'r' format uses OP, RS, RT, RD, SHAMT and FUNCT. 40 41 The 'b' format uses OP, RS, RT and DELTA. 42 43 The floating point 'i' format uses OP, RS, RT and IMMEDIATE. 44 45 The floating point 'r' format uses OP, FMT, FT, FS, FD and FUNCT. 46 47 A breakpoint instruction uses OP, CODE and SPEC (10 bits of the 48 breakpoint instruction are not defined; Kane says the breakpoint 49 code field in BREAK is 20 bits; yet MIPS assemblers and debuggers 50 only use ten bits). An optional two-operand form of break/sdbbp 51 allows the lower ten bits to be set too. 52 53 The syscall instruction uses SYSCALL. 54 55 The general coprocessor instructions use COPZ. */ 56 57 #define OP_MASK_OP 0x3f 58 #define OP_SH_OP 26 59 #define OP_MASK_RS 0x1f 60 #define OP_SH_RS 21 61 #define OP_MASK_FR 0x1f 62 #define OP_SH_FR 21 63 #define OP_MASK_FMT 0x1f 64 #define OP_SH_FMT 21 65 #define OP_MASK_BCC 0x7 66 #define OP_SH_BCC 18 67 #define OP_MASK_CODE 0x3ff 68 #define OP_SH_CODE 16 69 #define OP_MASK_CODE2 0x3ff 70 #define OP_SH_CODE2 6 71 #define OP_MASK_RT 0x1f 72 #define OP_SH_RT 16 73 #define OP_MASK_FT 0x1f 74 #define OP_SH_FT 16 75 #define OP_MASK_CACHE 0x1f 76 #define OP_SH_CACHE 16 77 #define OP_MASK_RD 0x1f 78 #define OP_SH_RD 11 79 #define OP_MASK_FS 0x1f 80 #define OP_SH_FS 11 81 #define OP_MASK_PREFX 0x1f 82 #define OP_SH_PREFX 11 83 #define OP_MASK_CCC 0x7 84 #define OP_SH_CCC 8 85 #define OP_MASK_SYSCALL 0xfffff 86 #define OP_SH_SYSCALL 6 87 #define OP_MASK_SHAMT 0x1f 88 #define OP_SH_SHAMT 6 89 #define OP_MASK_FD 0x1f 90 #define OP_SH_FD 6 91 #define OP_MASK_TARGET 0x3ffffff 92 #define OP_SH_TARGET 0 93 #define OP_MASK_COPZ 0x1ffffff 94 #define OP_SH_COPZ 0 95 #define OP_MASK_IMMEDIATE 0xffff 96 #define OP_SH_IMMEDIATE 0 97 #define OP_MASK_DELTA 0xffff 98 #define OP_SH_DELTA 0 99 #define OP_MASK_FUNCT 0x3f 100 #define OP_SH_FUNCT 0 101 #define OP_MASK_SPEC 0x3f 102 #define OP_SH_SPEC 0 103 #define OP_SH_LOCC 8 /* FP condition code */ 104 #define OP_SH_HICC 18 /* FP condition code */ 105 #define OP_MASK_CC 0x7 106 #define OP_SH_COP1NORM 25 /* Normal COP1 encoding */ 107 #define OP_MASK_COP1NORM 0x1 /* a single bit */ 108 #define OP_SH_COP1SPEC 21 /* COP1 encodings */ 109 #define OP_MASK_COP1SPEC 0xf 110 #define OP_MASK_COP1SCLR 0x4 111 #define OP_MASK_COP1CMP 0x3 112 #define OP_SH_COP1CMP 4 113 #define OP_SH_FORMAT 21 /* FP short format field */ 114 #define OP_MASK_FORMAT 0x7 115 #define OP_SH_TRUE 16 116 #define OP_MASK_TRUE 0x1 117 #define OP_SH_GE 17 118 #define OP_MASK_GE 0x01 119 #define OP_SH_UNSIGNED 16 120 #define OP_MASK_UNSIGNED 0x1 121 #define OP_SH_HINT 16 122 #define OP_MASK_HINT 0x1f 123 #define OP_SH_MMI 0 /* Multimedia (parallel) op */ 124 #define OP_MASK_MMI 0x3f 125 #define OP_SH_MMISUB 6 126 #define OP_MASK_MMISUB 0x1f 127 #define OP_MASK_PERFREG 0x1f /* Performance monitoring */ 128 #define OP_SH_PERFREG 1 129 130 /* This structure holds information for a particular instruction. */ 131 132 struct mips_opcode 133 { 134 /* The name of the instruction. */ 135 const char *name; 136 /* A string describing the arguments for this instruction. */ 137 const char *args; 138 /* The basic opcode for the instruction. When assembling, this 139 opcode is modified by the arguments to produce the actual opcode 140 that is used. If pinfo is INSN_MACRO, then this is 0. */ 141 unsigned long match; 142 /* If pinfo is not INSN_MACRO, then this is a bit mask for the 143 relevant portions of the opcode when disassembling. If the 144 actual opcode anded with the match field equals the opcode field, 145 then we have found the correct instruction. If pinfo is 146 INSN_MACRO, then this field is the macro identifier. */ 147 unsigned long mask; 148 /* For a macro, this is INSN_MACRO. Otherwise, it is a collection 149 of bits describing the instruction, notably any relevant hazard 150 information. */ 151 unsigned long pinfo; 152 /* A collection of bits describing the instruction sets of which this 153 instruction or macro is a member. */ 154 unsigned long membership; 155 }; 156 157 /* These are the characters which may appears in the args field of an 158 instruction. They appear in the order in which the fields appear 159 when the instruction is used. Commas and parentheses in the args 160 string are ignored when assembling, and written into the output 161 when disassembling. 162 163 Each of these characters corresponds to a mask field defined above. 164 165 "<" 5 bit shift amount (OP_*_SHAMT) 166 ">" shift amount between 32 and 63, stored after subtracting 32 (OP_*_SHAMT) 167 "a" 26 bit target address (OP_*_TARGET) 168 "b" 5 bit base register (OP_*_RS) 169 "c" 10 bit breakpoint code (OP_*_CODE) 170 "d" 5 bit destination register specifier (OP_*_RD) 171 "h" 5 bit prefx hint (OP_*_PREFX) 172 "i" 16 bit unsigned immediate (OP_*_IMMEDIATE) 173 "j" 16 bit signed immediate (OP_*_DELTA) 174 "k" 5 bit cache opcode in target register position (OP_*_CACHE) 175 "o" 16 bit signed offset (OP_*_DELTA) 176 "p" 16 bit PC relative branch target address (OP_*_DELTA) 177 "q" 10 bit extra breakpoint code (OP_*_CODE2) 178 "r" 5 bit same register used as both source and target (OP_*_RS) 179 "s" 5 bit source register specifier (OP_*_RS) 180 "t" 5 bit target register (OP_*_RT) 181 "u" 16 bit upper 16 bits of address (OP_*_IMMEDIATE) 182 "v" 5 bit same register used as both source and destination (OP_*_RS) 183 "w" 5 bit same register used as both target and destination (OP_*_RT) 184 "C" 25 bit coprocessor function code (OP_*_COPZ) 185 "B" 20 bit syscall function code (OP_*_SYSCALL) 186 "x" accept and ignore register name 187 "z" must be zero register 188 189 Floating point instructions: 190 "D" 5 bit destination register (OP_*_FD) 191 "M" 3 bit compare condition code (OP_*_CCC) (only used for mips4 and up) 192 "N" 3 bit branch condition code (OP_*_BCC) (only used for mips4 and up) 193 "S" 5 bit fs source 1 register (OP_*_FS) 194 "T" 5 bit ft source 2 register (OP_*_FT) 195 "R" 5 bit fr source 3 register (OP_*_FR) 196 "V" 5 bit same register used as floating source and destination (OP_*_FS) 197 "W" 5 bit same register used as floating target and destination (OP_*_FT) 198 199 Coprocessor instructions: 200 "E" 5 bit target register (OP_*_RT) 201 "G" 5 bit destination register (OP_*_RD) 202 "P" 5 bit performance-monitor register (OP_*_PERFREG) 203 204 Macro instructions: 205 "A" General 32 bit expression 206 "I" 32 bit immediate 207 "F" 64 bit floating point constant in .rdata 208 "L" 64 bit floating point constant in .lit8 209 "f" 32 bit floating point constant 210 "l" 32 bit floating point constant in .lit4 211 212 Other: 213 "()" parens surrounding optional value 214 "," separates operands 215 216 Characters used so far, for quick reference when adding more: 217 "<>()," 218 "ABCDEFGILMNSTRVW" 219 "abcdfhijklopqrstuvwxz" 220 */ 221 222 /* These are the bits which may be set in the pinfo field of an 223 instructions, if it is not equal to INSN_MACRO. */ 224 225 /* Modifies the general purpose register in OP_*_RD. */ 226 #define INSN_WRITE_GPR_D 0x00000001 227 /* Modifies the general purpose register in OP_*_RT. */ 228 #define INSN_WRITE_GPR_T 0x00000002 229 /* Modifies general purpose register 31. */ 230 #define INSN_WRITE_GPR_31 0x00000004 231 /* Modifies the floating point register in OP_*_FD. */ 232 #define INSN_WRITE_FPR_D 0x00000008 233 /* Modifies the floating point register in OP_*_FS. */ 234 #define INSN_WRITE_FPR_S 0x00000010 235 /* Modifies the floating point register in OP_*_FT. */ 236 #define INSN_WRITE_FPR_T 0x00000020 237 /* Reads the general purpose register in OP_*_RS. */ 238 #define INSN_READ_GPR_S 0x00000040 239 /* Reads the general purpose register in OP_*_RT. */ 240 #define INSN_READ_GPR_T 0x00000080 241 /* Reads the floating point register in OP_*_FS. */ 242 #define INSN_READ_FPR_S 0x00000100 243 /* Reads the floating point register in OP_*_FT. */ 244 #define INSN_READ_FPR_T 0x00000200 245 /* Reads the floating point register in OP_*_FR. */ 246 #define INSN_READ_FPR_R 0x00000400 247 /* Modifies coprocessor condition code. */ 248 #define INSN_WRITE_COND_CODE 0x00000800 249 /* Reads coprocessor condition code. */ 250 #define INSN_READ_COND_CODE 0x00001000 251 /* TLB operation. */ 252 #define INSN_TLB 0x00002000 253 /* Reads coprocessor register other than floating point register. */ 254 #define INSN_COP 0x00004000 255 /* Instruction loads value from memory, requiring delay. */ 256 #define INSN_LOAD_MEMORY_DELAY 0x00008000 257 /* Instruction loads value from coprocessor, requiring delay. */ 258 #define INSN_LOAD_COPROC_DELAY 0x00010000 259 /* Instruction has unconditional branch delay slot. */ 260 #define INSN_UNCOND_BRANCH_DELAY 0x00020000 261 /* Instruction has conditional branch delay slot. */ 262 #define INSN_COND_BRANCH_DELAY 0x00040000 263 /* Conditional branch likely: if branch not taken, insn nullified. */ 264 #define INSN_COND_BRANCH_LIKELY 0x00080000 265 /* Moves to coprocessor register, requiring delay. */ 266 #define INSN_COPROC_MOVE_DELAY 0x00100000 267 /* Loads coprocessor register from memory, requiring delay. */ 268 #define INSN_COPROC_MEMORY_DELAY 0x00200000 269 /* Reads the HI register. */ 270 #define INSN_READ_HI 0x00400000 271 /* Reads the LO register. */ 272 #define INSN_READ_LO 0x00800000 273 /* Modifies the HI register. */ 274 #define INSN_WRITE_HI 0x01000000 275 /* Modifies the LO register. */ 276 #define INSN_WRITE_LO 0x02000000 277 /* Takes a trap (easier to keep out of delay slot). */ 278 #define INSN_TRAP 0x04000000 279 /* Instruction stores value into memory. */ 280 #define INSN_STORE_MEMORY 0x08000000 281 /* Instruction uses single precision floating point. */ 282 #define FP_S 0x10000000 283 /* Instruction uses double precision floating point. */ 284 #define FP_D 0x20000000 285 /* Instruction is part of the tx39's integer multiply family. */ 286 #define INSN_MULT 0x40000000 287 /* Instruction synchronize shared memory. */ 288 #define INSN_SYNC 0x80000000 289 290 /* Instruction is actually a macro. It should be ignored by the 291 disassembler, and requires special treatment by the assembler. */ 292 #define INSN_MACRO 0xffffffff 293 294 295 296 297 298 /* MIPS ISA field--CPU level at which insn is supported. */ 299 #define INSN_ISA 0x0000000F 300 /* An instruction which is not part of any basic MIPS ISA. 301 (ie it is a chip specific instruction) */ 302 #define INSN_NO_ISA 0x00000000 303 /* MIPS ISA 1 instruction. */ 304 #define INSN_ISA1 0x00000001 305 /* MIPS ISA 2 instruction (R6000 or R4000). */ 306 #define INSN_ISA2 0x00000002 307 /* MIPS ISA 3 instruction (R4000). */ 308 #define INSN_ISA3 0x00000003 309 /* MIPS ISA 4 instruction (R8000). */ 310 #define INSN_ISA4 0x00000004 311 #define INSN_ISA5 0x00000005 312 313 /* Chip specific instructions. These are bitmasks. */ 314 /* MIPS R4650 instruction. */ 315 #define INSN_4650 0x00000010 316 /* LSI R4010 instruction. */ 317 #define INSN_4010 0x00000020 318 /* NEC VR4100 instruction. */ 319 #define INSN_4100 0x00000040 320 /* Toshiba R3900 instruction. */ 321 #define INSN_3900 0x00000080 322 323 /* 32-bit code running on a ISA3+ CPU. */ 324 #define INSN_GP32 0x00001000 325 326 /* Test for membership in an ISA including chip specific ISAs. 327 INSN is pointer to an element of the opcode table; ISA is the 328 specified ISA to test against; and CPU is the CPU specific ISA 329 to test, or zero if no CPU specific ISA test is desired. 330 The gp32 arg is set when you need to force 32-bit register usage on 331 a machine with 64-bit registers; see the documentation under -mgp32 332 in the MIPS gas docs. */ 333 334 #define OPCODE_IS_MEMBER(insn,isa,cpu,gp32) \ 335 ((((insn)->membership & INSN_ISA) != 0 \ 336 && ((insn)->membership & INSN_ISA) <= isa \ 337 && ((insn)->membership & INSN_GP32 ? gp32 : 1)) \ 338 || (cpu == 4650 \ 339 && ((insn)->membership & INSN_4650) != 0) \ 340 || (cpu == 4010 \ 341 && ((insn)->membership & INSN_4010) != 0) \ 342 || ((cpu == 4100 \ 343 || cpu == 4111 \ 344 ) \ 345 && ((insn)->membership & INSN_4100) != 0) \ 346 || (cpu == 3900 \ 347 && ((insn)->membership & INSN_3900) != 0)) 348 349 /* This is a list of macro expanded instructions. 350 * 351 * _I appended means immediate 352 * _A appended means address 353 * _AB appended means address with base register 354 * _D appended means 64 bit floating point constant 355 * _S appended means 32 bit floating point constant 356 */ 357 enum { 358 M_ABS, 359 M_ADD_I, 360 M_ADDU_I, 361 M_AND_I, 362 M_BEQ, 363 M_BEQ_I, 364 M_BEQL_I, 365 M_BGE, 366 M_BGEL, 367 M_BGE_I, 368 M_BGEL_I, 369 M_BGEU, 370 M_BGEUL, 371 M_BGEU_I, 372 M_BGEUL_I, 373 M_BGT, 374 M_BGTL, 375 M_BGT_I, 376 M_BGTL_I, 377 M_BGTU, 378 M_BGTUL, 379 M_BGTU_I, 380 M_BGTUL_I, 381 M_BLE, 382 M_BLEL, 383 M_BLE_I, 384 M_BLEL_I, 385 M_BLEU, 386 M_BLEUL, 387 M_BLEU_I, 388 M_BLEUL_I, 389 M_BLT, 390 M_BLTL, 391 M_BLT_I, 392 M_BLTL_I, 393 M_BLTU, 394 M_BLTUL, 395 M_BLTU_I, 396 M_BLTUL_I, 397 M_BNE, 398 M_BNE_I, 399 M_BNEL_I, 400 M_DABS, 401 M_DADD_I, 402 M_DADDU_I, 403 M_DDIV_3, 404 M_DDIV_3I, 405 M_DDIVU_3, 406 M_DDIVU_3I, 407 M_DIV_3, 408 M_DIV_3I, 409 M_DIVU_3, 410 M_DIVU_3I, 411 M_DLA_AB, 412 M_DLI, 413 M_DMUL, 414 M_DMUL_I, 415 M_DMULO, 416 M_DMULO_I, 417 M_DMULOU, 418 M_DMULOU_I, 419 M_DREM_3, 420 M_DREM_3I, 421 M_DREMU_3, 422 M_DREMU_3I, 423 M_DSUB_I, 424 M_DSUBU_I, 425 M_DSUBU_I_2, 426 M_J_A, 427 M_JAL_1, 428 M_JAL_2, 429 M_JAL_A, 430 M_L_DOB, 431 M_L_DAB, 432 M_LA_AB, 433 M_LB_A, 434 M_LB_AB, 435 M_LBU_A, 436 M_LBU_AB, 437 M_LD_A, 438 M_LD_OB, 439 M_LD_AB, 440 M_LDC1_AB, 441 M_LDC2_AB, 442 M_LDC3_AB, 443 M_LDL_AB, 444 M_LDR_AB, 445 M_LH_A, 446 M_LH_AB, 447 M_LHU_A, 448 M_LHU_AB, 449 M_LI, 450 M_LI_D, 451 M_LI_DD, 452 M_LI_S, 453 M_LI_SS, 454 M_LL_AB, 455 M_LLD_AB, 456 M_LS_A, 457 M_LW_A, 458 M_LW_AB, 459 M_LWC0_A, 460 M_LWC0_AB, 461 M_LWC1_A, 462 M_LWC1_AB, 463 M_LWC2_A, 464 M_LWC2_AB, 465 M_LWC3_A, 466 M_LWC3_AB, 467 M_LWL_A, 468 M_LWL_AB, 469 M_LWR_A, 470 M_LWR_AB, 471 M_LWU_AB, 472 M_MUL, 473 M_MUL_I, 474 M_MULO, 475 M_MULO_I, 476 M_MULOU, 477 M_MULOU_I, 478 M_NOR_I, 479 M_OR_I, 480 M_REM_3, 481 M_REM_3I, 482 M_REMU_3, 483 M_REMU_3I, 484 M_ROL, 485 M_ROL_I, 486 M_ROR, 487 M_ROR_I, 488 M_S_DA, 489 M_S_DOB, 490 M_S_DAB, 491 M_S_S, 492 M_SC_AB, 493 M_SCD_AB, 494 M_SD_A, 495 M_SD_OB, 496 M_SD_AB, 497 M_SDC1_AB, 498 M_SDC2_AB, 499 M_SDC3_AB, 500 M_SDL_AB, 501 M_SDR_AB, 502 M_SEQ, 503 M_SEQ_I, 504 M_SGE, 505 M_SGE_I, 506 M_SGEU, 507 M_SGEU_I, 508 M_SGT, 509 M_SGT_I, 510 M_SGTU, 511 M_SGTU_I, 512 M_SLE, 513 M_SLE_I, 514 M_SLEU, 515 M_SLEU_I, 516 M_SLT_I, 517 M_SLTU_I, 518 M_SNE, 519 M_SNE_I, 520 M_SB_A, 521 M_SB_AB, 522 M_SH_A, 523 M_SH_AB, 524 M_SW_A, 525 M_SW_AB, 526 M_SWC0_A, 527 M_SWC0_AB, 528 M_SWC1_A, 529 M_SWC1_AB, 530 M_SWC2_A, 531 M_SWC2_AB, 532 M_SWC3_A, 533 M_SWC3_AB, 534 M_SWL_A, 535 M_SWL_AB, 536 M_SWR_A, 537 M_SWR_AB, 538 M_SUB_I, 539 M_SUBU_I, 540 M_SUBU_I_2, 541 M_TEQ_I, 542 M_TGE_I, 543 M_TGEU_I, 544 M_TLT_I, 545 M_TLTU_I, 546 M_TNE_I, 547 M_TRUNCWD, 548 M_TRUNCWS, 549 M_ULD, 550 M_ULD_A, 551 M_ULH, 552 M_ULH_A, 553 M_ULHU, 554 M_ULHU_A, 555 M_ULW, 556 M_ULW_A, 557 M_USH, 558 M_USH_A, 559 M_USW, 560 M_USW_A, 561 M_USD, 562 M_USD_A, 563 M_XOR_I, 564 M_COP0, 565 M_COP1, 566 M_COP2, 567 M_COP3, 568 M_NUM_MACROS 569 }; 570 571 572 /* The order of overloaded instructions matters. Label arguments and 573 register arguments look the same. Instructions that can have either 574 for arguments must apear in the correct order in this table for the 575 assembler to pick the right one. In other words, entries with 576 immediate operands must apear after the same instruction with 577 registers. 578 579 Many instructions are short hand for other instructions (i.e., The 580 jal <register> instruction is short for jalr <register>). */ 581 582 extern const struct mips_opcode mips_builtin_opcodes[]; 583 extern const int bfd_mips_num_builtin_opcodes; 584 extern struct mips_opcode *mips_opcodes; 585 extern int bfd_mips_num_opcodes; 586 #define NUMOPCODES bfd_mips_num_opcodes 587 588 589 /* The rest of this file adds definitions for the mips16 TinyRISC 590 processor. */ 591 592 /* These are the bitmasks and shift counts used for the different 593 fields in the instruction formats. Other than OP, no masks are 594 provided for the fixed portions of an instruction, since they are 595 not needed. 596 597 The I format uses IMM11. 598 599 The RI format uses RX and IMM8. 600 601 The RR format uses RX, and RY. 602 603 The RRI format uses RX, RY, and IMM5. 604 605 The RRR format uses RX, RY, and RZ. 606 607 The RRI_A format uses RX, RY, and IMM4. 608 609 The SHIFT format uses RX, RY, and SHAMT. 610 611 The I8 format uses IMM8. 612 613 The I8_MOVR32 format uses RY and REGR32. 614 615 The IR_MOV32R format uses REG32R and MOV32Z. 616 617 The I64 format uses IMM8. 618 619 The RI64 format uses RY and IMM5. 620 */ 621 622 #define MIPS16OP_MASK_OP 0x1f 623 #define MIPS16OP_SH_OP 11 624 #define MIPS16OP_MASK_IMM11 0x7ff 625 #define MIPS16OP_SH_IMM11 0 626 #define MIPS16OP_MASK_RX 0x7 627 #define MIPS16OP_SH_RX 8 628 #define MIPS16OP_MASK_IMM8 0xff 629 #define MIPS16OP_SH_IMM8 0 630 #define MIPS16OP_MASK_RY 0x7 631 #define MIPS16OP_SH_RY 5 632 #define MIPS16OP_MASK_IMM5 0x1f 633 #define MIPS16OP_SH_IMM5 0 634 #define MIPS16OP_MASK_RZ 0x7 635 #define MIPS16OP_SH_RZ 2 636 #define MIPS16OP_MASK_IMM4 0xf 637 #define MIPS16OP_SH_IMM4 0 638 #define MIPS16OP_MASK_REGR32 0x1f 639 #define MIPS16OP_SH_REGR32 0 640 #define MIPS16OP_MASK_REG32R 0x1f 641 #define MIPS16OP_SH_REG32R 3 642 #define MIPS16OP_EXTRACT_REG32R(i) ((((i) >> 5) & 7) | ((i) & 0x18)) 643 #define MIPS16OP_MASK_MOVE32Z 0x7 644 #define MIPS16OP_SH_MOVE32Z 0 645 #define MIPS16OP_MASK_IMM6 0x3f 646 #define MIPS16OP_SH_IMM6 5 647 648 /* These are the characters which may appears in the args field of an 649 instruction. They appear in the order in which the fields appear 650 when the instruction is used. Commas and parentheses in the args 651 string are ignored when assembling, and written into the output 652 when disassembling. 653 654 "y" 3 bit register (MIPS16OP_*_RY) 655 "x" 3 bit register (MIPS16OP_*_RX) 656 "z" 3 bit register (MIPS16OP_*_RZ) 657 "Z" 3 bit register (MIPS16OP_*_MOVE32Z) 658 "v" 3 bit same register as source and destination (MIPS16OP_*_RX) 659 "w" 3 bit same register as source and destination (MIPS16OP_*_RY) 660 "0" zero register ($0) 661 "S" stack pointer ($sp or $29) 662 "P" program counter 663 "R" return address register ($ra or $31) 664 "X" 5 bit MIPS register (MIPS16OP_*_REGR32) 665 "Y" 5 bit MIPS register (MIPS16OP_*_REG32R) 666 "6" 6 bit unsigned break code (MIPS16OP_*_IMM6) 667 "a" 26 bit jump address 668 "e" 11 bit extension value 669 "l" register list for entry instruction 670 "L" register list for exit instruction 671 672 The remaining codes may be extended. Except as otherwise noted, 673 the full extended operand is a 16 bit signed value. 674 "<" 3 bit unsigned shift count * 0 (MIPS16OP_*_RZ) (full 5 bit unsigned) 675 ">" 3 bit unsigned shift count * 0 (MIPS16OP_*_RX) (full 5 bit unsigned) 676 "[" 3 bit unsigned shift count * 0 (MIPS16OP_*_RZ) (full 6 bit unsigned) 677 "]" 3 bit unsigned shift count * 0 (MIPS16OP_*_RX) (full 6 bit unsigned) 678 "4" 4 bit signed immediate * 0 (MIPS16OP_*_IMM4) (full 15 bit signed) 679 "5" 5 bit unsigned immediate * 0 (MIPS16OP_*_IMM5) 680 "H" 5 bit unsigned immediate * 2 (MIPS16OP_*_IMM5) 681 "W" 5 bit unsigned immediate * 4 (MIPS16OP_*_IMM5) 682 "D" 5 bit unsigned immediate * 8 (MIPS16OP_*_IMM5) 683 "j" 5 bit signed immediate * 0 (MIPS16OP_*_IMM5) 684 "8" 8 bit unsigned immediate * 0 (MIPS16OP_*_IMM8) 685 "V" 8 bit unsigned immediate * 4 (MIPS16OP_*_IMM8) 686 "C" 8 bit unsigned immediate * 8 (MIPS16OP_*_IMM8) 687 "U" 8 bit unsigned immediate * 0 (MIPS16OP_*_IMM8) (full 16 bit unsigned) 688 "k" 8 bit signed immediate * 0 (MIPS16OP_*_IMM8) 689 "K" 8 bit signed immediate * 8 (MIPS16OP_*_IMM8) 690 "p" 8 bit conditional branch address (MIPS16OP_*_IMM8) 691 "q" 11 bit branch address (MIPS16OP_*_IMM11) 692 "A" 8 bit PC relative address * 4 (MIPS16OP_*_IMM8) 693 "B" 5 bit PC relative address * 8 (MIPS16OP_*_IMM5) 694 "E" 5 bit PC relative address * 4 (MIPS16OP_*_IMM5) 695 */ 696 697 /* For the mips16, we use the same opcode table format and a few of 698 the same flags. However, most of the flags are different. */ 699 700 /* Modifies the register in MIPS16OP_*_RX. */ 701 #define MIPS16_INSN_WRITE_X 0x00000001 702 /* Modifies the register in MIPS16OP_*_RY. */ 703 #define MIPS16_INSN_WRITE_Y 0x00000002 704 /* Modifies the register in MIPS16OP_*_RZ. */ 705 #define MIPS16_INSN_WRITE_Z 0x00000004 706 /* Modifies the T ($24) register. */ 707 #define MIPS16_INSN_WRITE_T 0x00000008 708 /* Modifies the SP ($29) register. */ 709 #define MIPS16_INSN_WRITE_SP 0x00000010 710 /* Modifies the RA ($31) register. */ 711 #define MIPS16_INSN_WRITE_31 0x00000020 712 /* Modifies the general purpose register in MIPS16OP_*_REG32R. */ 713 #define MIPS16_INSN_WRITE_GPR_Y 0x00000040 714 /* Reads the register in MIPS16OP_*_RX. */ 715 #define MIPS16_INSN_READ_X 0x00000080 716 /* Reads the register in MIPS16OP_*_RY. */ 717 #define MIPS16_INSN_READ_Y 0x00000100 718 /* Reads the register in MIPS16OP_*_MOVE32Z. */ 719 #define MIPS16_INSN_READ_Z 0x00000200 720 /* Reads the T ($24) register. */ 721 #define MIPS16_INSN_READ_T 0x00000400 722 /* Reads the SP ($29) register. */ 723 #define MIPS16_INSN_READ_SP 0x00000800 724 /* Reads the RA ($31) register. */ 725 #define MIPS16_INSN_READ_31 0x00001000 726 /* Reads the program counter. */ 727 #define MIPS16_INSN_READ_PC 0x00002000 728 /* Reads the general purpose register in MIPS16OP_*_REGR32. */ 729 #define MIPS16_INSN_READ_GPR_X 0x00004000 730 /* Is a branch insn. */ 731 #define MIPS16_INSN_BRANCH 0x00010000 732 733 /* The following flags have the same value for the mips16 opcode 734 table: 735 INSN_UNCOND_BRANCH_DELAY 736 INSN_COND_BRANCH_DELAY 737 INSN_COND_BRANCH_LIKELY (never used) 738 INSN_READ_HI 739 INSN_READ_LO 740 INSN_WRITE_HI 741 INSN_WRITE_LO 742 INSN_TRAP 743 INSN_ISA3 744 */ 745 746 extern const struct mips_opcode mips16_opcodes[]; 747 extern const int bfd_mips16_num_opcodes; 748 749 #endif /* _MIPS_H_ */ 750