1*e93f7393Sniklas /* regPacket.h - register packet definitions for rdb */ 2*e93f7393Sniklas 3*e93f7393Sniklas /* Copyright 1992-1993 Wind River Systems, Inc. */ 4*e93f7393Sniklas 5*e93f7393Sniklas /* 6*e93f7393Sniklas modification history 7*e93f7393Sniklas -------------------- 8*e93f7393Sniklas 01d,30nov93,pad Added Am29K target definitions. 9*e93f7393Sniklas 01c,14jun93,maf additional definitions for documentation purposes. 10*e93f7393Sniklas fixed reversal of MIPS_R_LO and MIPS_R_HI. 11*e93f7393Sniklas 01b,08feb93,scy added SPARC target definitions. changed to WRS code convetion. 12*e93f7393Sniklas 01a,20feb92,j_w created. 13*e93f7393Sniklas */ 14*e93f7393Sniklas 15*e93f7393Sniklas #ifndef __INCregPacketh 16*e93f7393Sniklas #define __INCregPacketh 17*e93f7393Sniklas 18*e93f7393Sniklas 19*e93f7393Sniklas /* MC68K */ 20*e93f7393Sniklas 21*e93f7393Sniklas #define MC68K_GREG_SIZE 0x04 /* size of general-purpose reg */ 22*e93f7393Sniklas #define MC68K_GREG_PLEN 0x48 /* size of general-purpose reg block */ 23*e93f7393Sniklas 24*e93f7393Sniklas /* offsets into general-purpose register block */ 25*e93f7393Sniklas 26*e93f7393Sniklas #define MC68K_R_D0 0x00 /* d0; d1 - d7 follow in sequence */ 27*e93f7393Sniklas #define MC68K_R_A0 0x20 /* a0; a1 - a7 follow in sequence */ 28*e93f7393Sniklas #define MC68K_R_SR 0x40 /* sr (represented as a 4-byte val) */ 29*e93f7393Sniklas #define MC68K_R_PC 0x44 /* pc */ 30*e93f7393Sniklas 31*e93f7393Sniklas #define MC68K_FPREG_SIZE 0x0c /* size of floating-point data reg */ 32*e93f7393Sniklas #define MC68K_FPREG_PLEN 0x6c /* size of floating-point reg block */ 33*e93f7393Sniklas 34*e93f7393Sniklas /* offsets into floating-point register block */ 35*e93f7393Sniklas 36*e93f7393Sniklas #define MC68K_R_FP0 0x00 /* fp0; fp1 - fp7 follow in sequence */ 37*e93f7393Sniklas #define MC68K_R_FPCR 0x60 /* fpcr */ 38*e93f7393Sniklas #define MC68K_R_FPSR 0x64 /* fpsr */ 39*e93f7393Sniklas #define MC68K_R_FPIAR 0x68 /* fpiar */ 40*e93f7393Sniklas 41*e93f7393Sniklas 42*e93f7393Sniklas /* I960 */ 43*e93f7393Sniklas 44*e93f7393Sniklas #define I960_GREG_SIZE 0x04 /* size of general-purpose reg */ 45*e93f7393Sniklas #define I960_GREG_PLEN 0x8c /* size of general-purpose reg block */ 46*e93f7393Sniklas 47*e93f7393Sniklas /* offsets into general-purpose register block */ 48*e93f7393Sniklas 49*e93f7393Sniklas #define I960_R_R0 0x00 /* r0; r1 - r15 follow in sequence */ 50*e93f7393Sniklas #define I960_R_G0 0x40 /* g0; g1 - g15 follow in sequence */ 51*e93f7393Sniklas #define I960_R_PCW 0x80 /* pcw */ 52*e93f7393Sniklas #define I960_R_ACW 0x84 /* acw */ 53*e93f7393Sniklas #define I960_R_TCW 0x88 /* tcw */ 54*e93f7393Sniklas 55*e93f7393Sniklas #define I960_FPREG_SIZE 0x10 /* size of floating-point reg */ 56*e93f7393Sniklas #define I960_FPREG_PLEN 0x28 /* size of floating-point reg block */ 57*e93f7393Sniklas 58*e93f7393Sniklas /* offsets into floating-point register block */ 59*e93f7393Sniklas 60*e93f7393Sniklas #define I960_R_FP0 0x00 /* fp0; fp1 - fp3 follow in sequence */ 61*e93f7393Sniklas 62*e93f7393Sniklas 63*e93f7393Sniklas /* SPARC */ 64*e93f7393Sniklas 65*e93f7393Sniklas #define SPARC_GREG_SIZE 0x04 /* size of general-purpose reg */ 66*e93f7393Sniklas #define SPARC_GREG_PLEN 0x98 /* size of general-purpose reg block */ 67*e93f7393Sniklas 68*e93f7393Sniklas /* offsets into general-purpose register block */ 69*e93f7393Sniklas 70*e93f7393Sniklas #define SPARC_R_G0 0x00 /* g0; g1 - g7 follow in sequence */ 71*e93f7393Sniklas #define SPARC_R_O0 0x20 /* o0; o1 - o7 follow in sequence */ 72*e93f7393Sniklas #define SPARC_R_L0 0x40 /* l0; l1 - l7 follow in sequence */ 73*e93f7393Sniklas #define SPARC_R_I0 0x60 /* i0; i1 - i7 follow in sequence */ 74*e93f7393Sniklas #define SPARC_R_Y 0x80 /* y */ 75*e93f7393Sniklas #define SPARC_R_PSR 0x84 /* psr */ 76*e93f7393Sniklas #define SPARC_R_WIM 0x88 /* wim */ 77*e93f7393Sniklas #define SPARC_R_TBR 0x8c /* tbr */ 78*e93f7393Sniklas #define SPARC_R_PC 0x90 /* pc */ 79*e93f7393Sniklas #define SPARC_R_NPC 0x94 /* npc */ 80*e93f7393Sniklas 81*e93f7393Sniklas #define SPARC_FPREG_SIZE 0x04 /* size of floating-point reg */ 82*e93f7393Sniklas #define SPARC_FPREG_PLEN 0x84 /* size of floating-point reg block */ 83*e93f7393Sniklas 84*e93f7393Sniklas /* offsets into floating-point register block */ 85*e93f7393Sniklas 86*e93f7393Sniklas #define SPARC_R_FP0 0x00 /* f0; f1 - f31 follow in sequence */ 87*e93f7393Sniklas #define SPARC_R_FSR 0x80 /* fsr */ 88*e93f7393Sniklas 89*e93f7393Sniklas 90*e93f7393Sniklas /* MIPS */ 91*e93f7393Sniklas 92*e93f7393Sniklas #define MIPS_GREG_SIZE 0x04 /* size of general-purpose reg */ 93*e93f7393Sniklas #define MIPS_GREG_PLEN 0x90 /* size of general-purpose reg block */ 94*e93f7393Sniklas 95*e93f7393Sniklas /* offsets into general-purpose register block */ 96*e93f7393Sniklas 97*e93f7393Sniklas #define MIPS_R_GP0 0x00 /* gp0 (zero) */ 98*e93f7393Sniklas #define MIPS_R_AT 0x04 /* at */ 99*e93f7393Sniklas #define MIPS_R_V0 0x08 /* v0 */ 100*e93f7393Sniklas #define MIPS_R_V1 0x0c /* v1 */ 101*e93f7393Sniklas #define MIPS_R_A0 0x10 /* a0 */ 102*e93f7393Sniklas #define MIPS_R_A1 0x14 /* a1 */ 103*e93f7393Sniklas #define MIPS_R_A2 0x18 /* a2 */ 104*e93f7393Sniklas #define MIPS_R_A3 0x1c /* a3 */ 105*e93f7393Sniklas #define MIPS_R_T0 0x20 /* t0 */ 106*e93f7393Sniklas #define MIPS_R_T1 0x24 /* t1 */ 107*e93f7393Sniklas #define MIPS_R_T2 0x28 /* t2 */ 108*e93f7393Sniklas #define MIPS_R_T3 0x2c /* t3 */ 109*e93f7393Sniklas #define MIPS_R_T4 0x30 /* t4 */ 110*e93f7393Sniklas #define MIPS_R_T5 0x34 /* t5 */ 111*e93f7393Sniklas #define MIPS_R_T6 0x38 /* t6 */ 112*e93f7393Sniklas #define MIPS_R_T7 0x3c /* t7 */ 113*e93f7393Sniklas #define MIPS_R_S0 0x40 /* s0 */ 114*e93f7393Sniklas #define MIPS_R_S1 0x44 /* s1 */ 115*e93f7393Sniklas #define MIPS_R_S2 0x48 /* s2 */ 116*e93f7393Sniklas #define MIPS_R_S3 0x4c /* s3 */ 117*e93f7393Sniklas #define MIPS_R_S4 0x50 /* s4 */ 118*e93f7393Sniklas #define MIPS_R_S5 0x54 /* s5 */ 119*e93f7393Sniklas #define MIPS_R_S6 0x58 /* s6 */ 120*e93f7393Sniklas #define MIPS_R_S7 0x5c /* s7 */ 121*e93f7393Sniklas #define MIPS_R_T8 0x60 /* t8 */ 122*e93f7393Sniklas #define MIPS_R_T9 0x64 /* t9 */ 123*e93f7393Sniklas #define MIPS_R_K0 0x68 /* k0 */ 124*e93f7393Sniklas #define MIPS_R_K1 0x6c /* k1 */ 125*e93f7393Sniklas #define MIPS_R_GP 0x70 /* gp */ 126*e93f7393Sniklas #define MIPS_R_SP 0x74 /* sp */ 127*e93f7393Sniklas #define MIPS_R_S8 0x78 /* s8 */ 128*e93f7393Sniklas #define MIPS_R_LO 0x80 /* lo */ 129*e93f7393Sniklas #define MIPS_R_HI 0x84 /* hi */ 130*e93f7393Sniklas #define MIPS_R_SR 0x88 /* sr */ 131*e93f7393Sniklas #define MIPS_R_PC 0x8c /* pc */ 132*e93f7393Sniklas 133*e93f7393Sniklas #define MIPS_FPREG_SIZE 0x04 /* size of floating-point data reg */ 134*e93f7393Sniklas #define MIPS_FPREG_PLEN 0x84 /* size of floating-point reg block */ 135*e93f7393Sniklas 136*e93f7393Sniklas /* offsets into floating-point register block */ 137*e93f7393Sniklas 138*e93f7393Sniklas #define MIPS_R_FP0 0x00 /* f0; f1 - f31 follow in sequence */ 139*e93f7393Sniklas #define MIPS_R_FPCSR 0x80 /* offset of fpcsr in reg block */ 140*e93f7393Sniklas 141*e93f7393Sniklas 142*e93f7393Sniklas /* General registers for the Am29k */ 143*e93f7393Sniklas 144*e93f7393Sniklas #define AM29K_GREG_SIZE 0x04 145*e93f7393Sniklas #define AM29K_GREG_PLEN 0x2d4 146*e93f7393Sniklas 147*e93f7393Sniklas #define AM29K_R_GR96 0x0 148*e93f7393Sniklas #define AM29K_R_VAB 0x280 149*e93f7393Sniklas #define AM29K_R_INTE 0x2bc 150*e93f7393Sniklas #define AM29K_R_RSP 0x2c0 151*e93f7393Sniklas 152*e93f7393Sniklas /* Floating Point registers for the Am29k */ 153*e93f7393Sniklas 154*e93f7393Sniklas #define AM29K_FPREG_SIZE 0x04 155*e93f7393Sniklas #define AM29K_FPREG_PLEN 0x8 156*e93f7393Sniklas 157*e93f7393Sniklas #define AM29K_R_FPE 0x0 158*e93f7393Sniklas #define AM29K_R_FPS 0x4 159*e93f7393Sniklas 160*e93f7393Sniklas #endif /* __INCregPacketh */ 161