1*11efff7fSkettenis /* Helper file for i386 platform. Runtime check for MMX/SSE/SSE2 support.
2*11efff7fSkettenis
3*11efff7fSkettenis Copyright 2004 Free Software Foundation, Inc.
4*11efff7fSkettenis
5*11efff7fSkettenis This file is part of GDB.
6*11efff7fSkettenis
7*11efff7fSkettenis This program is free software; you can redistribute it and/or modify
8*11efff7fSkettenis it under the terms of the GNU General Public License as published by
9*11efff7fSkettenis the Free Software Foundation; either version 2 of the License, or
10*11efff7fSkettenis (at your option) any later version.
11*11efff7fSkettenis
12*11efff7fSkettenis This program is distributed in the hope that it will be useful,
13*11efff7fSkettenis but WITHOUT ANY WARRANTY; without even the implied warranty of
14*11efff7fSkettenis MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15*11efff7fSkettenis GNU General Public License for more details.
16*11efff7fSkettenis
17*11efff7fSkettenis You should have received a copy of the GNU General Public License
18*11efff7fSkettenis along with this program; if not, write to the Free Software
19*11efff7fSkettenis Foundation, Inc., 59 Temple Place - Suite 330,
20*11efff7fSkettenis Boston, MA 02111-1307, USA. */
21*11efff7fSkettenis
22*11efff7fSkettenis /* Used by 20020523-2.c and i386-sse-6.c, and possibly others. */
23*11efff7fSkettenis /* Plagarized from 20020523-2.c. */
24*11efff7fSkettenis /* Plagarized from gcc. */
25*11efff7fSkettenis
26*11efff7fSkettenis #define bit_CMOV (1 << 15)
27*11efff7fSkettenis #define bit_MMX (1 << 23)
28*11efff7fSkettenis #define bit_SSE (1 << 25)
29*11efff7fSkettenis #define bit_SSE2 (1 << 26)
30*11efff7fSkettenis
31*11efff7fSkettenis #ifndef NOINLINE
32*11efff7fSkettenis #define NOINLINE __attribute__ ((noinline))
33*11efff7fSkettenis #endif
34*11efff7fSkettenis
35*11efff7fSkettenis unsigned int i386_cpuid (void) NOINLINE;
36*11efff7fSkettenis
37*11efff7fSkettenis unsigned int NOINLINE
i386_cpuid(void)38*11efff7fSkettenis i386_cpuid (void)
39*11efff7fSkettenis {
40*11efff7fSkettenis int fl1, fl2;
41*11efff7fSkettenis
42*11efff7fSkettenis #ifndef __x86_64__
43*11efff7fSkettenis /* See if we can use cpuid. On AMD64 we always can. */
44*11efff7fSkettenis __asm__ ("pushfl; pushfl; popl %0; movl %0,%1; xorl %2,%0;"
45*11efff7fSkettenis "pushl %0; popfl; pushfl; popl %0; popfl"
46*11efff7fSkettenis : "=&r" (fl1), "=&r" (fl2)
47*11efff7fSkettenis : "i" (0x00200000));
48*11efff7fSkettenis if (((fl1 ^ fl2) & 0x00200000) == 0)
49*11efff7fSkettenis return (0);
50*11efff7fSkettenis #endif
51*11efff7fSkettenis
52*11efff7fSkettenis /* Host supports cpuid. See if cpuid gives capabilities, try
53*11efff7fSkettenis CPUID(0). Preserve %ebx and %ecx; cpuid insn clobbers these, we
54*11efff7fSkettenis don't need their CPUID values here, and %ebx may be the PIC
55*11efff7fSkettenis register. */
56*11efff7fSkettenis #ifdef __x86_64__
57*11efff7fSkettenis __asm__ ("pushq %%rcx; pushq %%rbx; cpuid; popq %%rbx; popq %%rcx"
58*11efff7fSkettenis : "=a" (fl1) : "0" (0) : "rdx", "cc");
59*11efff7fSkettenis #else
60*11efff7fSkettenis __asm__ ("pushl %%ecx; pushl %%ebx; cpuid; popl %%ebx; popl %%ecx"
61*11efff7fSkettenis : "=a" (fl1) : "0" (0) : "edx", "cc");
62*11efff7fSkettenis #endif
63*11efff7fSkettenis if (fl1 == 0)
64*11efff7fSkettenis return (0);
65*11efff7fSkettenis
66*11efff7fSkettenis /* Invoke CPUID(1), return %edx; caller can examine bits to
67*11efff7fSkettenis determine what's supported. */
68*11efff7fSkettenis #ifdef __x86_64__
69*11efff7fSkettenis __asm__ ("pushq %%rcx; pushq %%rbx; cpuid; popq %%rbx; popq %%rcx"
70*11efff7fSkettenis : "=d" (fl2), "=a" (fl1) : "1" (1) : "cc");
71*11efff7fSkettenis #else
72*11efff7fSkettenis __asm__ ("pushl %%ecx; pushl %%ebx; cpuid; popl %%ebx; popl %%ecx"
73*11efff7fSkettenis : "=d" (fl2), "=a" (fl1) : "1" (1) : "cc");
74*11efff7fSkettenis #endif
75*11efff7fSkettenis
76*11efff7fSkettenis return fl2;
77*11efff7fSkettenis }
78