1 /* Target-dependent code for the SPARC for GDB, the GNU debugger. 2 Copyright 1986, 1987, 1989, 1991, 1992, 1993, 1994, 1995, 1996 3 Free Software Foundation, Inc. 4 5 This file is part of GDB. 6 7 This program is free software; you can redistribute it and/or modify 8 it under the terms of the GNU General Public License as published by 9 the Free Software Foundation; either version 2 of the License, or 10 (at your option) any later version. 11 12 This program is distributed in the hope that it will be useful, 13 but WITHOUT ANY WARRANTY; without even the implied warranty of 14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 GNU General Public License for more details. 16 17 You should have received a copy of the GNU General Public License 18 along with this program; if not, write to the Free Software 19 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ 20 21 /* ??? Support for calling functions from gdb in sparc64 is unfinished. */ 22 23 #include "defs.h" 24 #include "frame.h" 25 #include "inferior.h" 26 #include "obstack.h" 27 #include "target.h" 28 #include "value.h" 29 #include "bfd.h" 30 #include "gdb_string.h" 31 32 #ifdef USE_PROC_FS 33 #include <sys/procfs.h> 34 #endif 35 36 #include "gdbcore.h" 37 38 #ifdef GDB_TARGET_IS_SPARC64 39 #define FP_REGISTER_BYTES (64 * 4) 40 #else 41 #define FP_REGISTER_BYTES (32 * 4) 42 #endif 43 44 /* If not defined, assume 32 bit sparc. */ 45 #ifndef FP_MAX_REGNUM 46 #define FP_MAX_REGNUM (FP0_REGNUM + 32) 47 #endif 48 49 #define SPARC_INTREG_SIZE (REGISTER_RAW_SIZE (G0_REGNUM)) 50 51 /* From infrun.c */ 52 extern int stop_after_trap; 53 54 /* We don't store all registers immediately when requested, since they 55 get sent over in large chunks anyway. Instead, we accumulate most 56 of the changes and send them over once. "deferred_stores" keeps 57 track of which sets of registers we have locally-changed copies of, 58 so we only need send the groups that have changed. */ 59 60 int deferred_stores = 0; /* Cumulates stores we want to do eventually. */ 61 62 /* Branches with prediction are treated like their non-predicting cousins. */ 63 /* FIXME: What about floating point branches? */ 64 65 /* Macros to extract fields from sparc instructions. */ 66 #define X_OP(i) (((i) >> 30) & 0x3) 67 #define X_RD(i) (((i) >> 25) & 0x1f) 68 #define X_A(i) (((i) >> 29) & 1) 69 #define X_COND(i) (((i) >> 25) & 0xf) 70 #define X_OP2(i) (((i) >> 22) & 0x7) 71 #define X_IMM22(i) ((i) & 0x3fffff) 72 #define X_OP3(i) (((i) >> 19) & 0x3f) 73 #define X_RS1(i) (((i) >> 14) & 0x1f) 74 #define X_I(i) (((i) >> 13) & 1) 75 #define X_IMM13(i) ((i) & 0x1fff) 76 /* Sign extension macros. */ 77 #define X_SIMM13(i) ((X_IMM13 (i) ^ 0x1000) - 0x1000) 78 #define X_DISP22(i) ((X_IMM22 (i) ^ 0x200000) - 0x200000) 79 #ifdef GDB_TARGET_IS_SPARC64 80 #define X_CC(i) (((i) >> 20) & 3) 81 #define X_P(i) (((i) >> 19) & 1) 82 #define X_DISP19(i) ((((i) & 0x7ffff) ^ 0x40000) - 0x40000) 83 #define X_RCOND(i) (((i) >> 25) & 7) 84 #define X_DISP16(i) ((((((i) >> 6) && 0xc000) | ((i) & 0x3fff)) ^ 0x8000) - 0x8000) 85 #define X_FCN(i) (((i) >> 25) & 31) 86 #endif 87 88 typedef enum 89 { 90 Error, not_branch, bicc, bicca, ba, baa, ticc, ta, 91 #ifdef GDB_TARGET_IS_SPARC64 92 done_retry 93 #endif 94 } branch_type; 95 96 /* Simulate single-step ptrace call for sun4. Code written by Gary 97 Beihl (beihl@mcc.com). */ 98 99 /* npc4 and next_pc describe the situation at the time that the 100 step-breakpoint was set, not necessary the current value of NPC_REGNUM. */ 101 static CORE_ADDR next_pc, npc4, target; 102 static int brknpc4, brktrg; 103 typedef char binsn_quantum[BREAKPOINT_MAX]; 104 static binsn_quantum break_mem[3]; 105 106 /* Non-zero if we just simulated a single-step ptrace call. This is 107 needed because we cannot remove the breakpoints in the inferior 108 process until after the `wait' in `wait_for_inferior'. Used for 109 sun4. */ 110 111 int one_stepped; 112 113 static branch_type isbranch PARAMS ((long, CORE_ADDR, CORE_ADDR *)); 114 115 /* single_step() is called just before we want to resume the inferior, 116 if we want to single-step it but there is no hardware or kernel single-step 117 support (as on all SPARCs). We find all the possible targets of the 118 coming instruction and breakpoint them. 119 120 single_step is also called just after the inferior stops. If we had 121 set up a simulated single-step, we undo our damage. */ 122 123 void 124 single_step (ignore) 125 enum target_signal ignore; /* pid, but we don't need it */ 126 { 127 branch_type br; 128 CORE_ADDR pc; 129 long pc_instruction; 130 131 if (!one_stepped) 132 { 133 /* Always set breakpoint for NPC. */ 134 next_pc = read_register (NPC_REGNUM); 135 npc4 = next_pc + 4; /* branch not taken */ 136 137 target_insert_breakpoint (next_pc, break_mem[0]); 138 /* printf_unfiltered ("set break at %x\n",next_pc); */ 139 140 pc = read_register (PC_REGNUM); 141 pc_instruction = read_memory_integer (pc, 4); 142 br = isbranch (pc_instruction, pc, &target); 143 brknpc4 = brktrg = 0; 144 145 if (br == bicca) 146 { 147 /* Conditional annulled branch will either end up at 148 npc (if taken) or at npc+4 (if not taken). 149 Trap npc+4. */ 150 brknpc4 = 1; 151 target_insert_breakpoint (npc4, break_mem[1]); 152 } 153 else if (br == baa && target != next_pc) 154 { 155 /* Unconditional annulled branch will always end up at 156 the target. */ 157 brktrg = 1; 158 target_insert_breakpoint (target, break_mem[2]); 159 } 160 #ifdef GDB_TARGET_IS_SPARC64 161 else if (br == done_retry) 162 { 163 brktrg = 1; 164 target_insert_breakpoint (target, break_mem[2]); 165 } 166 #endif 167 168 /* We are ready to let it go */ 169 one_stepped = 1; 170 return; 171 } 172 else 173 { 174 /* Remove breakpoints */ 175 target_remove_breakpoint (next_pc, break_mem[0]); 176 177 if (brknpc4) 178 target_remove_breakpoint (npc4, break_mem[1]); 179 180 if (brktrg) 181 target_remove_breakpoint (target, break_mem[2]); 182 183 one_stepped = 0; 184 } 185 } 186 187 /* Call this for each newly created frame. For SPARC, we need to calculate 188 the bottom of the frame, and do some extra work if the prologue 189 has been generated via the -mflat option to GCC. In particular, 190 we need to know where the previous fp and the pc have been stashed, 191 since their exact position within the frame may vary. */ 192 193 void 194 sparc_init_extra_frame_info (fromleaf, fi) 195 int fromleaf; 196 struct frame_info *fi; 197 { 198 char *name; 199 CORE_ADDR addr; 200 int insn; 201 202 fi->bottom = 203 (fi->next ? 204 (fi->frame == fi->next->frame ? fi->next->bottom : fi->next->frame) : 205 read_sp ()); 206 207 /* If fi->next is NULL, then we already set ->frame by passing read_fp() 208 to create_new_frame. */ 209 if (fi->next) 210 { 211 char buf[MAX_REGISTER_RAW_SIZE]; 212 int err; 213 214 /* Compute ->frame as if not flat. If it is flat, we'll change 215 it later. */ 216 /* FIXME: If error reading memory, should just stop backtracing, rather 217 than error(). */ 218 get_saved_register (buf, 0, 0, fi, FP_REGNUM, 0); 219 fi->frame = extract_address (buf, REGISTER_RAW_SIZE (FP_REGNUM)); 220 221 #ifdef GDB_TARGET_IS_SPARC64 222 if (fi->frame & 1) 223 fi->frame += 2047; 224 #endif 225 } 226 227 /* Decide whether this is a function with a ``flat register window'' 228 frame. For such functions, the frame pointer is actually in %i7. */ 229 fi->flat = 0; 230 if (find_pc_partial_function (fi->pc, &name, &addr, NULL)) 231 { 232 /* See if the function starts with an add (which will be of a 233 negative number if a flat frame) to the sp. FIXME: Does not 234 handle large frames which will need more than one instruction 235 to adjust the sp. */ 236 insn = read_memory_integer (addr, 4); 237 if (X_OP (insn) == 2 && X_RD (insn) == 14 && X_OP3 (insn) == 0 238 && X_I (insn) && X_SIMM13 (insn) < 0) 239 { 240 int offset = X_SIMM13 (insn); 241 242 /* Then look for a save of %i7 into the frame. */ 243 insn = read_memory_integer (addr + 4, 4); 244 if (X_OP (insn) == 3 245 && X_RD (insn) == 31 246 && X_OP3 (insn) == 4 247 && X_RS1 (insn) == 14) 248 { 249 char buf[MAX_REGISTER_RAW_SIZE]; 250 251 /* We definitely have a flat frame now. */ 252 fi->flat = 1; 253 254 fi->sp_offset = offset; 255 256 /* Overwrite the frame's address with the value in %i7. */ 257 get_saved_register (buf, 0, 0, fi, I7_REGNUM, 0); 258 fi->frame = extract_address (buf, REGISTER_RAW_SIZE (I7_REGNUM)); 259 260 #ifdef GDB_TARGET_IS_SPARC64 261 if (fi->frame & 1) 262 fi->frame += 2047; 263 #endif 264 265 /* Record where the fp got saved. */ 266 fi->fp_addr = fi->frame + fi->sp_offset + X_SIMM13 (insn); 267 268 /* Also try to collect where the pc got saved to. */ 269 fi->pc_addr = 0; 270 insn = read_memory_integer (addr + 12, 4); 271 if (X_OP (insn) == 3 272 && X_RD (insn) == 15 273 && X_OP3 (insn) == 4 274 && X_RS1 (insn) == 14) 275 fi->pc_addr = fi->frame + fi->sp_offset + X_SIMM13 (insn); 276 } 277 } 278 } 279 if (fi->next && fi->frame == 0) 280 { 281 /* Kludge to cause init_prev_frame_info to destroy the new frame. */ 282 fi->frame = fi->next->frame; 283 fi->pc = fi->next->pc; 284 } 285 } 286 287 CORE_ADDR 288 sparc_frame_chain (frame) 289 struct frame_info *frame; 290 { 291 /* Value that will cause FRAME_CHAIN_VALID to not worry about the chain 292 value. If it realy is zero, we detect it later in 293 sparc_init_prev_frame. */ 294 return (CORE_ADDR)1; 295 } 296 297 CORE_ADDR 298 sparc_extract_struct_value_address (regbuf) 299 char regbuf[REGISTER_BYTES]; 300 { 301 #ifdef GDB_TARGET_IS_SPARC64 302 return extract_address (regbuf + REGISTER_BYTE (O0_REGNUM), 303 REGISTER_RAW_SIZE (O0_REGNUM)); 304 #else 305 return read_memory_integer (((int *)(regbuf)) [SP_REGNUM] + (16 * SPARC_INTREG_SIZE), 306 TARGET_PTR_BIT / TARGET_CHAR_BIT); 307 #endif 308 } 309 310 /* Find the pc saved in frame FRAME. */ 311 312 CORE_ADDR 313 sparc_frame_saved_pc (frame) 314 struct frame_info *frame; 315 { 316 char buf[MAX_REGISTER_RAW_SIZE]; 317 CORE_ADDR addr; 318 319 if (frame->signal_handler_caller) 320 { 321 /* This is the signal trampoline frame. 322 Get the saved PC from the sigcontext structure. */ 323 324 #ifndef SIGCONTEXT_PC_OFFSET 325 #define SIGCONTEXT_PC_OFFSET 12 326 #endif 327 328 CORE_ADDR sigcontext_addr; 329 char scbuf[TARGET_PTR_BIT / HOST_CHAR_BIT]; 330 int saved_pc_offset = SIGCONTEXT_PC_OFFSET; 331 char *name = NULL; 332 333 /* Solaris2 ucbsigvechandler passes a pointer to a sigcontext 334 as the third parameter. The offset to the saved pc is 12. */ 335 find_pc_partial_function (frame->pc, &name, 336 (CORE_ADDR *)NULL,(CORE_ADDR *)NULL); 337 if (name && STREQ (name, "ucbsigvechandler")) 338 saved_pc_offset = 12; 339 340 /* The sigcontext address is contained in register O2. */ 341 get_saved_register (buf, (int *)NULL, (CORE_ADDR *)NULL, 342 frame, O0_REGNUM + 2, (enum lval_type *)NULL); 343 sigcontext_addr = extract_address (buf, REGISTER_RAW_SIZE (O0_REGNUM + 2)); 344 345 /* Don't cause a memory_error when accessing sigcontext in case the 346 stack layout has changed or the stack is corrupt. */ 347 target_read_memory (sigcontext_addr + saved_pc_offset, 348 scbuf, sizeof (scbuf)); 349 return extract_address (scbuf, sizeof (scbuf)); 350 } 351 if (frame->flat) 352 addr = frame->pc_addr; 353 else 354 addr = frame->bottom + FRAME_SAVED_I0 + 355 SPARC_INTREG_SIZE * (I7_REGNUM - I0_REGNUM); 356 357 if (addr == 0) 358 /* A flat frame leaf function might not save the PC anywhere, 359 just leave it in %o7. */ 360 return PC_ADJUST (read_register (O7_REGNUM)); 361 362 read_memory (addr, buf, SPARC_INTREG_SIZE); 363 return PC_ADJUST (extract_address (buf, SPARC_INTREG_SIZE)); 364 } 365 366 /* Since an individual frame in the frame cache is defined by two 367 arguments (a frame pointer and a stack pointer), we need two 368 arguments to get info for an arbitrary stack frame. This routine 369 takes two arguments and makes the cached frames look as if these 370 two arguments defined a frame on the cache. This allows the rest 371 of info frame to extract the important arguments without 372 difficulty. */ 373 374 struct frame_info * 375 setup_arbitrary_frame (argc, argv) 376 int argc; 377 CORE_ADDR *argv; 378 { 379 struct frame_info *frame; 380 381 if (argc != 2) 382 error ("Sparc frame specifications require two arguments: fp and sp"); 383 384 frame = create_new_frame (argv[0], 0); 385 386 if (!frame) 387 fatal ("internal: create_new_frame returned invalid frame"); 388 389 frame->bottom = argv[1]; 390 frame->pc = FRAME_SAVED_PC (frame); 391 return frame; 392 } 393 394 /* Given a pc value, skip it forward past the function prologue by 395 disassembling instructions that appear to be a prologue. 396 397 If FRAMELESS_P is set, we are only testing to see if the function 398 is frameless. This allows a quicker answer. 399 400 This routine should be more specific in its actions; making sure 401 that it uses the same register in the initial prologue section. */ 402 403 static CORE_ADDR examine_prologue PARAMS ((CORE_ADDR, int, struct frame_info *, 404 struct frame_saved_regs *)); 405 406 static CORE_ADDR 407 examine_prologue (start_pc, frameless_p, fi, saved_regs) 408 CORE_ADDR start_pc; 409 int frameless_p; 410 struct frame_info *fi; 411 struct frame_saved_regs *saved_regs; 412 { 413 int insn; 414 int dest = -1; 415 CORE_ADDR pc = start_pc; 416 int is_flat = 0; 417 418 insn = read_memory_integer (pc, 4); 419 420 /* Recognize the `sethi' insn and record its destination. */ 421 if (X_OP (insn) == 0 && X_OP2 (insn) == 4) 422 { 423 dest = X_RD (insn); 424 pc += 4; 425 insn = read_memory_integer (pc, 4); 426 } 427 428 /* Recognize an add immediate value to register to either %g1 or 429 the destination register recorded above. Actually, this might 430 well recognize several different arithmetic operations. 431 It doesn't check that rs1 == rd because in theory "sub %g0, 5, %g1" 432 followed by "save %sp, %g1, %sp" is a valid prologue (Not that 433 I imagine any compiler really does that, however). */ 434 if (X_OP (insn) == 2 435 && X_I (insn) 436 && (X_RD (insn) == 1 || X_RD (insn) == dest)) 437 { 438 pc += 4; 439 insn = read_memory_integer (pc, 4); 440 } 441 442 /* Recognize any SAVE insn. */ 443 if (X_OP (insn) == 2 && X_OP3 (insn) == 60) 444 { 445 pc += 4; 446 if (frameless_p) /* If the save is all we care about, */ 447 return pc; /* return before doing more work */ 448 insn = read_memory_integer (pc, 4); 449 } 450 /* Recognize add to %sp. */ 451 else if (X_OP (insn) == 2 && X_RD (insn) == 14 && X_OP3 (insn) == 0) 452 { 453 pc += 4; 454 if (frameless_p) /* If the add is all we care about, */ 455 return pc; /* return before doing more work */ 456 is_flat = 1; 457 insn = read_memory_integer (pc, 4); 458 /* Recognize store of frame pointer (i7). */ 459 if (X_OP (insn) == 3 460 && X_RD (insn) == 31 461 && X_OP3 (insn) == 4 462 && X_RS1 (insn) == 14) 463 { 464 pc += 4; 465 insn = read_memory_integer (pc, 4); 466 467 /* Recognize sub %sp, <anything>, %i7. */ 468 if (X_OP (insn) == 2 469 && X_OP3 (insn) == 4 470 && X_RS1 (insn) == 14 471 && X_RD (insn) == 31) 472 { 473 pc += 4; 474 insn = read_memory_integer (pc, 4); 475 } 476 else 477 return pc; 478 } 479 else 480 return pc; 481 } 482 else 483 /* Without a save or add instruction, it's not a prologue. */ 484 return start_pc; 485 486 while (1) 487 { 488 /* Recognize stores into the frame from the input registers. 489 This recognizes all non alternate stores of input register, 490 into a location offset from the frame pointer. */ 491 if ((X_OP (insn) == 3 492 && (X_OP3 (insn) & 0x3c) == 4 /* Store, non-alternate. */ 493 && (X_RD (insn) & 0x18) == 0x18 /* Input register. */ 494 && X_I (insn) /* Immediate mode. */ 495 && X_RS1 (insn) == 30 /* Off of frame pointer. */ 496 /* Into reserved stack space. */ 497 && X_SIMM13 (insn) >= 0x44 498 && X_SIMM13 (insn) < 0x5b)) 499 ; 500 else if (is_flat 501 && X_OP (insn) == 3 502 && X_OP3 (insn) == 4 503 && X_RS1 (insn) == 14 504 ) 505 { 506 if (saved_regs && X_I (insn)) 507 saved_regs->regs[X_RD (insn)] = 508 fi->frame + fi->sp_offset + X_SIMM13 (insn); 509 } 510 else 511 break; 512 pc += 4; 513 insn = read_memory_integer (pc, 4); 514 } 515 516 return pc; 517 } 518 519 CORE_ADDR 520 skip_prologue (start_pc, frameless_p) 521 CORE_ADDR start_pc; 522 int frameless_p; 523 { 524 return examine_prologue (start_pc, frameless_p, NULL, NULL); 525 } 526 527 /* Check instruction at ADDR to see if it is a branch. 528 All non-annulled instructions will go to NPC or will trap. 529 Set *TARGET if we find a candidate branch; set to zero if not. 530 531 This isn't static as it's used by remote-sa.sparc.c. */ 532 533 static branch_type 534 isbranch (instruction, addr, target) 535 long instruction; 536 CORE_ADDR addr, *target; 537 { 538 branch_type val = not_branch; 539 long int offset; /* Must be signed for sign-extend. */ 540 541 *target = 0; 542 543 if (X_OP (instruction) == 0 544 && (X_OP2 (instruction) == 2 545 || X_OP2 (instruction) == 6 546 #ifdef GDB_TARGET_IS_SPARC64 547 || X_OP2 (instruction) == 1 548 || X_OP2 (instruction) == 3 549 || X_OP2 (instruction) == 5 550 #else 551 || X_OP2 (instruction) == 7 552 #endif 553 )) 554 { 555 if (X_COND (instruction) == 8) 556 val = X_A (instruction) ? baa : ba; 557 else 558 val = X_A (instruction) ? bicca : bicc; 559 switch (X_OP2 (instruction)) 560 { 561 case 2: 562 case 6: 563 #ifndef GDB_TARGET_IS_SPARC64 564 case 7: 565 #endif 566 offset = 4 * X_DISP22 (instruction); 567 break; 568 #ifdef GDB_TARGET_IS_SPARC64 569 case 1: 570 case 5: 571 offset = 4 * X_DISP19 (instruction); 572 break; 573 case 3: 574 offset = 4 * X_DISP16 (instruction); 575 break; 576 #endif 577 } 578 *target = addr + offset; 579 } 580 #ifdef GDB_TARGET_IS_SPARC64 581 else if (X_OP (instruction) == 2 582 && X_OP3 (instruction) == 62) 583 { 584 if (X_FCN (instruction) == 0) 585 { 586 /* done */ 587 *target = read_register (TNPC_REGNUM); 588 val = done_retry; 589 } 590 else if (X_FCN (instruction) == 1) 591 { 592 /* retry */ 593 *target = read_register (TPC_REGNUM); 594 val = done_retry; 595 } 596 } 597 #endif 598 599 return val; 600 } 601 602 /* Find register number REGNUM relative to FRAME and put its 603 (raw) contents in *RAW_BUFFER. Set *OPTIMIZED if the variable 604 was optimized out (and thus can't be fetched). If the variable 605 was fetched from memory, set *ADDRP to where it was fetched from, 606 otherwise it was fetched from a register. 607 608 The argument RAW_BUFFER must point to aligned memory. */ 609 610 void 611 get_saved_register (raw_buffer, optimized, addrp, frame, regnum, lval) 612 char *raw_buffer; 613 int *optimized; 614 CORE_ADDR *addrp; 615 struct frame_info *frame; 616 int regnum; 617 enum lval_type *lval; 618 { 619 struct frame_info *frame1; 620 CORE_ADDR addr; 621 622 if (!target_has_registers) 623 error ("No registers."); 624 625 if (optimized) 626 *optimized = 0; 627 628 addr = 0; 629 630 /* FIXME This code extracted from infcmd.c; should put elsewhere! */ 631 if (frame == NULL) 632 { 633 /* error ("No selected frame."); */ 634 if (!target_has_registers) 635 error ("The program has no registers now."); 636 if (selected_frame == NULL) 637 error ("No selected frame."); 638 /* Try to use selected frame */ 639 frame = get_prev_frame (selected_frame); 640 if (frame == 0) 641 error ("Cmd not meaningful in the outermost frame."); 642 } 643 644 645 frame1 = frame->next; 646 647 /* Get saved PC from the frame info if not in innermost frame. */ 648 if (regnum == PC_REGNUM && frame1 != NULL) 649 { 650 if (lval != NULL) 651 *lval = not_lval; 652 if (raw_buffer != NULL) 653 { 654 /* Put it back in target format. */ 655 store_address (raw_buffer, REGISTER_RAW_SIZE (regnum), frame->pc); 656 } 657 if (addrp != NULL) 658 *addrp = 0; 659 return; 660 } 661 662 while (frame1 != NULL) 663 { 664 if (frame1->pc >= (frame1->bottom ? frame1->bottom : 665 read_sp ()) 666 && frame1->pc <= FRAME_FP (frame1)) 667 { 668 /* Dummy frame. All but the window regs are in there somewhere. 669 The window registers are saved on the stack, just like in a 670 normal frame. */ 671 if (regnum >= G1_REGNUM && regnum < G1_REGNUM + 7) 672 addr = frame1->frame + (regnum - G0_REGNUM) * SPARC_INTREG_SIZE 673 - (FP_REGISTER_BYTES + 8 * SPARC_INTREG_SIZE); 674 else if (regnum >= I0_REGNUM && regnum < I0_REGNUM + 8) 675 addr = (frame1->prev->bottom 676 + (regnum - I0_REGNUM) * SPARC_INTREG_SIZE 677 + FRAME_SAVED_I0); 678 else if (regnum >= L0_REGNUM && regnum < L0_REGNUM + 8) 679 addr = (frame1->prev->bottom 680 + (regnum - L0_REGNUM) * SPARC_INTREG_SIZE 681 + FRAME_SAVED_L0); 682 else if (regnum >= O0_REGNUM && regnum < O0_REGNUM + 8) 683 addr = frame1->frame + (regnum - O0_REGNUM) * SPARC_INTREG_SIZE 684 - (FP_REGISTER_BYTES + 16 * SPARC_INTREG_SIZE); 685 #ifdef FP0_REGNUM 686 else if (regnum >= FP0_REGNUM && regnum < FP0_REGNUM + 32) 687 addr = frame1->frame + (regnum - FP0_REGNUM) * 4 688 - (FP_REGISTER_BYTES); 689 #ifdef GDB_TARGET_IS_SPARC64 690 else if (regnum >= FP0_REGNUM + 32 && regnum < FP_MAX_REGNUM) 691 addr = frame1->frame + 32 * 4 + (regnum - FP0_REGNUM - 32) * 8 692 - (FP_REGISTER_BYTES); 693 #endif 694 #endif /* FP0_REGNUM */ 695 else if (regnum >= Y_REGNUM && regnum < NUM_REGS) 696 addr = frame1->frame + (regnum - Y_REGNUM) * SPARC_INTREG_SIZE 697 - (FP_REGISTER_BYTES + 24 * SPARC_INTREG_SIZE); 698 } 699 else if (frame1->flat) 700 { 701 702 if (regnum == RP_REGNUM) 703 addr = frame1->pc_addr; 704 else if (regnum == I7_REGNUM) 705 addr = frame1->fp_addr; 706 else 707 { 708 CORE_ADDR func_start; 709 struct frame_saved_regs regs; 710 memset (®s, 0, sizeof (regs)); 711 712 find_pc_partial_function (frame1->pc, NULL, &func_start, NULL); 713 examine_prologue (func_start, 0, frame1, ®s); 714 addr = regs.regs[regnum]; 715 } 716 } 717 else 718 { 719 /* Normal frame. Local and In registers are saved on stack. */ 720 if (regnum >= I0_REGNUM && regnum < I0_REGNUM + 8) 721 addr = (frame1->prev->bottom 722 + (regnum - I0_REGNUM) * SPARC_INTREG_SIZE 723 + FRAME_SAVED_I0); 724 else if (regnum >= L0_REGNUM && regnum < L0_REGNUM + 8) 725 addr = (frame1->prev->bottom 726 + (regnum - L0_REGNUM) * SPARC_INTREG_SIZE 727 + FRAME_SAVED_L0); 728 else if (regnum >= O0_REGNUM && regnum < O0_REGNUM + 8) 729 { 730 /* Outs become ins. */ 731 get_saved_register (raw_buffer, optimized, addrp, frame1, 732 (regnum - O0_REGNUM + I0_REGNUM), lval); 733 return; 734 } 735 } 736 if (addr != 0) 737 break; 738 frame1 = frame1->next; 739 } 740 if (addr != 0) 741 { 742 if (lval != NULL) 743 *lval = lval_memory; 744 if (regnum == SP_REGNUM) 745 { 746 if (raw_buffer != NULL) 747 { 748 /* Put it back in target format. */ 749 store_address (raw_buffer, REGISTER_RAW_SIZE (regnum), addr); 750 } 751 if (addrp != NULL) 752 *addrp = 0; 753 return; 754 } 755 if (raw_buffer != NULL) 756 read_memory (addr, raw_buffer, REGISTER_RAW_SIZE (regnum)); 757 } 758 else 759 { 760 if (lval != NULL) 761 *lval = lval_register; 762 addr = REGISTER_BYTE (regnum); 763 if (raw_buffer != NULL) 764 read_register_gen (regnum, raw_buffer); 765 } 766 if (addrp != NULL) 767 *addrp = addr; 768 } 769 770 /* Push an empty stack frame, and record in it the current PC, regs, etc. 771 772 We save the non-windowed registers and the ins. The locals and outs 773 are new; they don't need to be saved. The i's and l's of 774 the last frame were already saved on the stack. */ 775 776 /* Definitely see tm-sparc.h for more doc of the frame format here. */ 777 778 #ifdef GDB_TARGET_IS_SPARC64 779 #define DUMMY_REG_SAVE_OFFSET (128 + 16) 780 #else 781 #define DUMMY_REG_SAVE_OFFSET 0x60 782 #endif 783 784 /* See tm-sparc.h for how this is calculated. */ 785 #ifdef FP0_REGNUM 786 #define DUMMY_STACK_REG_BUF_SIZE \ 787 (((8+8+8) * SPARC_INTREG_SIZE) + (32 * REGISTER_RAW_SIZE (FP0_REGNUM))) 788 #else 789 #define DUMMY_STACK_REG_BUF_SIZE \ 790 (((8+8+8) * SPARC_INTREG_SIZE) ) 791 #endif /* FP0_REGNUM */ 792 #define DUMMY_STACK_SIZE (DUMMY_STACK_REG_BUF_SIZE + DUMMY_REG_SAVE_OFFSET) 793 794 void 795 sparc_push_dummy_frame () 796 { 797 CORE_ADDR sp, old_sp; 798 char register_temp[DUMMY_STACK_SIZE]; 799 800 old_sp = sp = read_sp (); 801 802 #ifdef GDB_TARGET_IS_SPARC64 803 /* PC, NPC, CCR, FSR, FPRS, Y, ASI */ 804 read_register_bytes (REGISTER_BYTE (PC_REGNUM), ®ister_temp[0], 805 REGISTER_RAW_SIZE (PC_REGNUM) * 7); 806 read_register_bytes (REGISTER_BYTE (PSTATE_REGNUM), 807 ®ister_temp[7 * SPARC_INTREG_SIZE], 808 REGISTER_RAW_SIZE (PSTATE_REGNUM)); 809 /* FIXME: not sure what needs to be saved here. */ 810 #else 811 /* Y, PS, WIM, TBR, PC, NPC, FPS, CPS regs */ 812 read_register_bytes (REGISTER_BYTE (Y_REGNUM), ®ister_temp[0], 813 REGISTER_RAW_SIZE (Y_REGNUM) * 8); 814 #endif 815 816 read_register_bytes (REGISTER_BYTE (O0_REGNUM), 817 ®ister_temp[8 * SPARC_INTREG_SIZE], 818 SPARC_INTREG_SIZE * 8); 819 820 read_register_bytes (REGISTER_BYTE (G0_REGNUM), 821 ®ister_temp[16 * SPARC_INTREG_SIZE], 822 SPARC_INTREG_SIZE * 8); 823 824 #ifdef FP0_REGNUM 825 read_register_bytes (REGISTER_BYTE (FP0_REGNUM), 826 ®ister_temp[24 * SPARC_INTREG_SIZE], 827 FP_REGISTER_BYTES); 828 #endif /* FP0_REGNUM */ 829 830 sp -= DUMMY_STACK_SIZE; 831 832 write_sp (sp); 833 834 write_memory (sp + DUMMY_REG_SAVE_OFFSET, ®ister_temp[0], 835 DUMMY_STACK_REG_BUF_SIZE); 836 837 write_fp (old_sp); 838 839 /* Set return address register for the call dummy to the current PC. */ 840 write_register (I7_REGNUM, read_pc() - 8); 841 } 842 843 /* sparc_frame_find_saved_regs (). This function is here only because 844 pop_frame uses it. Note there is an interesting corner case which 845 I think few ports of GDB get right--if you are popping a frame 846 which does not save some register that *is* saved by a more inner 847 frame (such a frame will never be a dummy frame because dummy 848 frames save all registers). Rewriting pop_frame to use 849 get_saved_register would solve this problem and also get rid of the 850 ugly duplication between sparc_frame_find_saved_regs and 851 get_saved_register. 852 853 Stores, into a struct frame_saved_regs, 854 the addresses of the saved registers of frame described by FRAME_INFO. 855 This includes special registers such as pc and fp saved in special 856 ways in the stack frame. sp is even more special: 857 the address we return for it IS the sp for the next frame. 858 859 Note that on register window machines, we are currently making the 860 assumption that window registers are being saved somewhere in the 861 frame in which they are being used. If they are stored in an 862 inferior frame, find_saved_register will break. 863 864 On the Sun 4, the only time all registers are saved is when 865 a dummy frame is involved. Otherwise, the only saved registers 866 are the LOCAL and IN registers which are saved as a result 867 of the "save/restore" opcodes. This condition is determined 868 by address rather than by value. 869 870 The "pc" is not stored in a frame on the SPARC. (What is stored 871 is a return address minus 8.) sparc_pop_frame knows how to 872 deal with that. Other routines might or might not. 873 874 See tm-sparc.h (PUSH_FRAME and friends) for CRITICAL information 875 about how this works. */ 876 877 static void sparc_frame_find_saved_regs PARAMS ((struct frame_info *, 878 struct frame_saved_regs *)); 879 880 static void 881 sparc_frame_find_saved_regs (fi, saved_regs_addr) 882 struct frame_info *fi; 883 struct frame_saved_regs *saved_regs_addr; 884 { 885 register int regnum; 886 CORE_ADDR frame_addr = FRAME_FP (fi); 887 888 if (!fi) 889 fatal ("Bad frame info struct in FRAME_FIND_SAVED_REGS"); 890 891 memset (saved_regs_addr, 0, sizeof (*saved_regs_addr)); 892 893 if (fi->pc >= (fi->bottom ? fi->bottom : 894 read_sp ()) 895 && fi->pc <= FRAME_FP(fi)) 896 { 897 /* Dummy frame. All but the window regs are in there somewhere. */ 898 for (regnum = G1_REGNUM; regnum < G1_REGNUM+7; regnum++) 899 saved_regs_addr->regs[regnum] = 900 frame_addr + (regnum - G0_REGNUM) * SPARC_INTREG_SIZE 901 - (FP_REGISTER_BYTES + 8 * SPARC_INTREG_SIZE); 902 for (regnum = I0_REGNUM; regnum < I0_REGNUM+8; regnum++) 903 saved_regs_addr->regs[regnum] = 904 frame_addr + (regnum - I0_REGNUM) * SPARC_INTREG_SIZE 905 - (FP_REGISTER_BYTES + 16 * SPARC_INTREG_SIZE); 906 #ifdef FP0_REGNUM 907 for (regnum = FP0_REGNUM; regnum < FP0_REGNUM + 32; regnum++) 908 saved_regs_addr->regs[regnum] = 909 frame_addr + (regnum - FP0_REGNUM) * 4 910 - (FP_REGISTER_BYTES); 911 #ifdef GDB_TARGET_IS_SPARC64 912 for (regnum = FP0_REGNUM + 32; regnum < FP_MAX_REGNUM; regnum++) 913 saved_regs_addr->regs[regnum] = 914 frame_addr + 32 * 4 + (regnum - FP0_REGNUM - 32) * 8 915 - (FP_REGISTER_BYTES); 916 #endif 917 #endif /* FP0_REGNUM */ 918 for (regnum = Y_REGNUM; regnum < NUM_REGS; regnum++) 919 saved_regs_addr->regs[regnum] = 920 frame_addr + (regnum - Y_REGNUM) * SPARC_INTREG_SIZE - 0xe0; 921 - (FP_REGISTER_BYTES + 24 * SPARC_INTREG_SIZE); 922 frame_addr = fi->bottom ? 923 fi->bottom : read_sp (); 924 } 925 else if (fi->flat) 926 { 927 CORE_ADDR func_start; 928 find_pc_partial_function (fi->pc, NULL, &func_start, NULL); 929 examine_prologue (func_start, 0, fi, saved_regs_addr); 930 931 /* Flat register window frame. */ 932 saved_regs_addr->regs[RP_REGNUM] = fi->pc_addr; 933 saved_regs_addr->regs[I7_REGNUM] = fi->fp_addr; 934 } 935 else 936 { 937 /* Normal frame. Just Local and In registers */ 938 frame_addr = fi->bottom ? 939 fi->bottom : read_sp (); 940 for (regnum = L0_REGNUM; regnum < L0_REGNUM+8; regnum++) 941 saved_regs_addr->regs[regnum] = 942 (frame_addr + (regnum - L0_REGNUM) * SPARC_INTREG_SIZE 943 + FRAME_SAVED_L0); 944 for (regnum = I0_REGNUM; regnum < I0_REGNUM+8; regnum++) 945 saved_regs_addr->regs[regnum] = 946 (frame_addr + (regnum - I0_REGNUM) * SPARC_INTREG_SIZE 947 + FRAME_SAVED_I0); 948 } 949 if (fi->next) 950 { 951 if (fi->flat) 952 { 953 saved_regs_addr->regs[O7_REGNUM] = fi->pc_addr; 954 } 955 else 956 { 957 /* Pull off either the next frame pointer or the stack pointer */ 958 CORE_ADDR next_next_frame_addr = 959 (fi->next->bottom ? 960 fi->next->bottom : 961 read_sp ()); 962 for (regnum = O0_REGNUM; regnum < O0_REGNUM+8; regnum++) 963 saved_regs_addr->regs[regnum] = 964 (next_next_frame_addr 965 + (regnum - O0_REGNUM) * SPARC_INTREG_SIZE 966 + FRAME_SAVED_I0); 967 } 968 } 969 /* Otherwise, whatever we would get from ptrace(GETREGS) is accurate */ 970 saved_regs_addr->regs[SP_REGNUM] = FRAME_FP (fi); 971 } 972 973 /* Discard from the stack the innermost frame, restoring all saved registers. 974 975 Note that the values stored in fsr by get_frame_saved_regs are *in 976 the context of the called frame*. What this means is that the i 977 regs of fsr must be restored into the o regs of the (calling) frame that 978 we pop into. We don't care about the output regs of the calling frame, 979 since unless it's a dummy frame, it won't have any output regs in it. 980 981 We never have to bother with %l (local) regs, since the called routine's 982 locals get tossed, and the calling routine's locals are already saved 983 on its stack. */ 984 985 /* Definitely see tm-sparc.h for more doc of the frame format here. */ 986 987 void 988 sparc_pop_frame () 989 { 990 register struct frame_info *frame = get_current_frame (); 991 register CORE_ADDR pc; 992 struct frame_saved_regs fsr; 993 char raw_buffer[REGISTER_BYTES]; 994 int regnum; 995 996 sparc_frame_find_saved_regs (frame, &fsr); 997 #ifdef FP0_REGNUM 998 if (fsr.regs[FP0_REGNUM]) 999 { 1000 read_memory (fsr.regs[FP0_REGNUM], raw_buffer, FP_REGISTER_BYTES); 1001 write_register_bytes (REGISTER_BYTE (FP0_REGNUM), 1002 raw_buffer, FP_REGISTER_BYTES); 1003 } 1004 #ifndef GDB_TARGET_IS_SPARC64 1005 if (fsr.regs[FPS_REGNUM]) 1006 { 1007 read_memory (fsr.regs[FPS_REGNUM], raw_buffer, 4); 1008 write_register_bytes (REGISTER_BYTE (FPS_REGNUM), raw_buffer, 4); 1009 } 1010 if (fsr.regs[CPS_REGNUM]) 1011 { 1012 read_memory (fsr.regs[CPS_REGNUM], raw_buffer, 4); 1013 write_register_bytes (REGISTER_BYTE (CPS_REGNUM), raw_buffer, 4); 1014 } 1015 #endif 1016 #endif /* FP0_REGNUM */ 1017 if (fsr.regs[G1_REGNUM]) 1018 { 1019 read_memory (fsr.regs[G1_REGNUM], raw_buffer, 7 * SPARC_INTREG_SIZE); 1020 write_register_bytes (REGISTER_BYTE (G1_REGNUM), raw_buffer, 1021 7 * SPARC_INTREG_SIZE); 1022 } 1023 1024 if (frame->flat) 1025 { 1026 /* Each register might or might not have been saved, need to test 1027 individually. */ 1028 for (regnum = L0_REGNUM; regnum < L0_REGNUM + 8; ++regnum) 1029 if (fsr.regs[regnum]) 1030 write_register (regnum, read_memory_integer (fsr.regs[regnum], 1031 SPARC_INTREG_SIZE)); 1032 for (regnum = I0_REGNUM; regnum < I0_REGNUM + 8; ++regnum) 1033 if (fsr.regs[regnum]) 1034 write_register (regnum, read_memory_integer (fsr.regs[regnum], 1035 SPARC_INTREG_SIZE)); 1036 1037 /* Handle all outs except stack pointer (o0-o5; o7). */ 1038 for (regnum = O0_REGNUM; regnum < O0_REGNUM + 6; ++regnum) 1039 if (fsr.regs[regnum]) 1040 write_register (regnum, read_memory_integer (fsr.regs[regnum], 1041 SPARC_INTREG_SIZE)); 1042 if (fsr.regs[O0_REGNUM + 7]) 1043 write_register (O0_REGNUM + 7, 1044 read_memory_integer (fsr.regs[O0_REGNUM + 7], 1045 SPARC_INTREG_SIZE)); 1046 1047 write_sp (frame->frame); 1048 } 1049 else if (fsr.regs[I0_REGNUM]) 1050 { 1051 CORE_ADDR sp; 1052 1053 char reg_temp[REGISTER_BYTES]; 1054 1055 read_memory (fsr.regs[I0_REGNUM], raw_buffer, 8 * SPARC_INTREG_SIZE); 1056 1057 /* Get the ins and locals which we are about to restore. Just 1058 moving the stack pointer is all that is really needed, except 1059 store_inferior_registers is then going to write the ins and 1060 locals from the registers array, so we need to muck with the 1061 registers array. */ 1062 sp = fsr.regs[SP_REGNUM]; 1063 1064 #ifdef GDB_TARGET_IS_SPARC64 1065 if (sp & 1) 1066 sp += 2047; 1067 #endif 1068 1069 read_memory (sp, reg_temp, SPARC_INTREG_SIZE * 16); 1070 1071 /* Restore the out registers. 1072 Among other things this writes the new stack pointer. */ 1073 write_register_bytes (REGISTER_BYTE (O0_REGNUM), raw_buffer, 1074 SPARC_INTREG_SIZE * 8); 1075 1076 write_register_bytes (REGISTER_BYTE (L0_REGNUM), reg_temp, 1077 SPARC_INTREG_SIZE * 16); 1078 } 1079 #ifndef GDB_TARGET_IS_SPARC64 1080 if (fsr.regs[PS_REGNUM]) 1081 write_register (PS_REGNUM, read_memory_integer (fsr.regs[PS_REGNUM], 4)); 1082 #endif 1083 if (fsr.regs[Y_REGNUM]) 1084 write_register (Y_REGNUM, read_memory_integer (fsr.regs[Y_REGNUM], REGISTER_RAW_SIZE (Y_REGNUM))); 1085 if (fsr.regs[PC_REGNUM]) 1086 { 1087 /* Explicitly specified PC (and maybe NPC) -- just restore them. */ 1088 write_register (PC_REGNUM, read_memory_integer (fsr.regs[PC_REGNUM], 1089 REGISTER_RAW_SIZE (PC_REGNUM))); 1090 if (fsr.regs[NPC_REGNUM]) 1091 write_register (NPC_REGNUM, 1092 read_memory_integer (fsr.regs[NPC_REGNUM], 1093 REGISTER_RAW_SIZE (NPC_REGNUM))); 1094 } 1095 else if (frame->flat) 1096 { 1097 if (frame->pc_addr) 1098 pc = PC_ADJUST ((CORE_ADDR) 1099 read_memory_integer (frame->pc_addr, 1100 REGISTER_RAW_SIZE (PC_REGNUM))); 1101 else 1102 { 1103 /* I think this happens only in the innermost frame, if so then 1104 it is a complicated way of saying 1105 "pc = read_register (O7_REGNUM);". */ 1106 char buf[MAX_REGISTER_RAW_SIZE]; 1107 get_saved_register (buf, 0, 0, frame, O7_REGNUM, 0); 1108 pc = PC_ADJUST (extract_address 1109 (buf, REGISTER_RAW_SIZE (O7_REGNUM))); 1110 } 1111 1112 write_register (PC_REGNUM, pc); 1113 write_register (NPC_REGNUM, pc + 4); 1114 } 1115 else if (fsr.regs[I7_REGNUM]) 1116 { 1117 /* Return address in %i7 -- adjust it, then restore PC and NPC from it */ 1118 pc = PC_ADJUST ((CORE_ADDR) read_memory_integer (fsr.regs[I7_REGNUM], 1119 SPARC_INTREG_SIZE)); 1120 write_register (PC_REGNUM, pc); 1121 write_register (NPC_REGNUM, pc + 4); 1122 } 1123 flush_cached_frames (); 1124 } 1125 1126 /* On the Sun 4 under SunOS, the compile will leave a fake insn which 1127 encodes the structure size being returned. If we detect such 1128 a fake insn, step past it. */ 1129 1130 CORE_ADDR 1131 sparc_pc_adjust(pc) 1132 CORE_ADDR pc; 1133 { 1134 unsigned long insn; 1135 char buf[4]; 1136 int err; 1137 1138 err = target_read_memory (pc + 8, buf, sizeof(long)); 1139 insn = extract_unsigned_integer (buf, 4); 1140 if ((err == 0) && (insn & 0xffc00000) == 0) 1141 return pc+12; 1142 else 1143 return pc+8; 1144 } 1145 1146 /* If pc is in a shared library trampoline, return its target. 1147 The SunOs 4.x linker rewrites the jump table entries for PIC 1148 compiled modules in the main executable to bypass the dynamic linker 1149 with jumps of the form 1150 sethi %hi(addr),%g1 1151 jmp %g1+%lo(addr) 1152 and removes the corresponding jump table relocation entry in the 1153 dynamic relocations. 1154 find_solib_trampoline_target relies on the presence of the jump 1155 table relocation entry, so we have to detect these jump instructions 1156 by hand. */ 1157 1158 CORE_ADDR 1159 sunos4_skip_trampoline_code (pc) 1160 CORE_ADDR pc; 1161 { 1162 unsigned long insn1; 1163 char buf[4]; 1164 int err; 1165 1166 err = target_read_memory (pc, buf, 4); 1167 insn1 = extract_unsigned_integer (buf, 4); 1168 if (err == 0 && (insn1 & 0xffc00000) == 0x03000000) 1169 { 1170 unsigned long insn2; 1171 1172 err = target_read_memory (pc + 4, buf, 4); 1173 insn2 = extract_unsigned_integer (buf, 4); 1174 if (err == 0 && (insn2 & 0xffffe000) == 0x81c06000) 1175 { 1176 CORE_ADDR target_pc = (insn1 & 0x3fffff) << 10; 1177 int delta = insn2 & 0x1fff; 1178 1179 /* Sign extend the displacement. */ 1180 if (delta & 0x1000) 1181 delta |= ~0x1fff; 1182 return target_pc + delta; 1183 } 1184 } 1185 return find_solib_trampoline_target (pc); 1186 } 1187 1188 #ifdef USE_PROC_FS /* Target dependent support for /proc */ 1189 1190 /* The /proc interface divides the target machine's register set up into 1191 two different sets, the general register set (gregset) and the floating 1192 point register set (fpregset). For each set, there is an ioctl to get 1193 the current register set and another ioctl to set the current values. 1194 1195 The actual structure passed through the ioctl interface is, of course, 1196 naturally machine dependent, and is different for each set of registers. 1197 For the sparc for example, the general register set is typically defined 1198 by: 1199 1200 typedef int gregset_t[38]; 1201 1202 #define R_G0 0 1203 ... 1204 #define R_TBR 37 1205 1206 and the floating point set by: 1207 1208 typedef struct prfpregset { 1209 union { 1210 u_long pr_regs[32]; 1211 double pr_dregs[16]; 1212 } pr_fr; 1213 void * pr_filler; 1214 u_long pr_fsr; 1215 u_char pr_qcnt; 1216 u_char pr_q_entrysize; 1217 u_char pr_en; 1218 u_long pr_q[64]; 1219 } prfpregset_t; 1220 1221 These routines provide the packing and unpacking of gregset_t and 1222 fpregset_t formatted data. 1223 1224 */ 1225 1226 /* Given a pointer to a general register set in /proc format (gregset_t *), 1227 unpack the register contents and supply them as gdb's idea of the current 1228 register values. */ 1229 1230 void 1231 supply_gregset (gregsetp) 1232 prgregset_t *gregsetp; 1233 { 1234 register int regi; 1235 register prgreg_t *regp = (prgreg_t *) gregsetp; 1236 static char zerobuf[MAX_REGISTER_RAW_SIZE] = {0}; 1237 1238 /* GDB register numbers for Gn, On, Ln, In all match /proc reg numbers. */ 1239 for (regi = G0_REGNUM ; regi <= I7_REGNUM ; regi++) 1240 { 1241 supply_register (regi, (char *) (regp + regi)); 1242 } 1243 1244 /* These require a bit more care. */ 1245 supply_register (PS_REGNUM, (char *) (regp + R_PS)); 1246 supply_register (PC_REGNUM, (char *) (regp + R_PC)); 1247 supply_register (NPC_REGNUM,(char *) (regp + R_nPC)); 1248 supply_register (Y_REGNUM, (char *) (regp + R_Y)); 1249 1250 /* Fill inaccessible registers with zero. */ 1251 supply_register (WIM_REGNUM, zerobuf); 1252 supply_register (TBR_REGNUM, zerobuf); 1253 supply_register (CPS_REGNUM, zerobuf); 1254 } 1255 1256 void 1257 fill_gregset (gregsetp, regno) 1258 prgregset_t *gregsetp; 1259 int regno; 1260 { 1261 int regi; 1262 register prgreg_t *regp = (prgreg_t *) gregsetp; 1263 1264 for (regi = 0 ; regi <= R_I7 ; regi++) 1265 { 1266 if ((regno == -1) || (regno == regi)) 1267 { 1268 *(regp + regi) = *(int *) ®isters[REGISTER_BYTE (regi)]; 1269 } 1270 } 1271 if ((regno == -1) || (regno == PS_REGNUM)) 1272 { 1273 *(regp + R_PS) = *(int *) ®isters[REGISTER_BYTE (PS_REGNUM)]; 1274 } 1275 if ((regno == -1) || (regno == PC_REGNUM)) 1276 { 1277 *(regp + R_PC) = *(int *) ®isters[REGISTER_BYTE (PC_REGNUM)]; 1278 } 1279 if ((regno == -1) || (regno == NPC_REGNUM)) 1280 { 1281 *(regp + R_nPC) = *(int *) ®isters[REGISTER_BYTE (NPC_REGNUM)]; 1282 } 1283 if ((regno == -1) || (regno == Y_REGNUM)) 1284 { 1285 *(regp + R_Y) = *(int *) ®isters[REGISTER_BYTE (Y_REGNUM)]; 1286 } 1287 } 1288 1289 #if defined (FP0_REGNUM) 1290 1291 /* Given a pointer to a floating point register set in /proc format 1292 (fpregset_t *), unpack the register contents and supply them as gdb's 1293 idea of the current floating point register values. */ 1294 1295 void 1296 supply_fpregset (fpregsetp) 1297 prfpregset_t *fpregsetp; 1298 { 1299 register int regi; 1300 char *from; 1301 1302 for (regi = FP0_REGNUM ; regi < FP_MAX_REGNUM ; regi++) 1303 { 1304 from = (char *) &fpregsetp->pr_fr.pr_regs[regi-FP0_REGNUM]; 1305 supply_register (regi, from); 1306 } 1307 supply_register (FPS_REGNUM, (char *) &(fpregsetp->pr_fsr)); 1308 } 1309 1310 /* Given a pointer to a floating point register set in /proc format 1311 (fpregset_t *), update the register specified by REGNO from gdb's idea 1312 of the current floating point register set. If REGNO is -1, update 1313 them all. */ 1314 /* ??? This will probably need some changes for sparc64. */ 1315 1316 void 1317 fill_fpregset (fpregsetp, regno) 1318 prfpregset_t *fpregsetp; 1319 int regno; 1320 { 1321 int regi; 1322 char *to; 1323 char *from; 1324 1325 for (regi = FP0_REGNUM ; regi < FP_MAX_REGNUM ; regi++) 1326 { 1327 if ((regno == -1) || (regno == regi)) 1328 { 1329 from = (char *) ®isters[REGISTER_BYTE (regi)]; 1330 to = (char *) &fpregsetp->pr_fr.pr_regs[regi-FP0_REGNUM]; 1331 memcpy (to, from, REGISTER_RAW_SIZE (regi)); 1332 } 1333 } 1334 if ((regno == -1) || (regno == FPS_REGNUM)) 1335 { 1336 fpregsetp->pr_fsr = *(int *) ®isters[REGISTER_BYTE (FPS_REGNUM)]; 1337 } 1338 } 1339 1340 #endif /* defined (FP0_REGNUM) */ 1341 1342 #endif /* USE_PROC_FS */ 1343 1344 1345 #ifdef GET_LONGJMP_TARGET 1346 1347 /* Figure out where the longjmp will land. We expect that we have just entered 1348 longjmp and haven't yet setup the stack frame, so the args are still in the 1349 output regs. %o0 (O0_REGNUM) points at the jmp_buf structure from which we 1350 extract the pc (JB_PC) that we will land at. The pc is copied into ADDR. 1351 This routine returns true on success */ 1352 1353 int 1354 get_longjmp_target (pc) 1355 CORE_ADDR *pc; 1356 { 1357 CORE_ADDR jb_addr; 1358 #define LONGJMP_TARGET_SIZE 4 1359 char buf[LONGJMP_TARGET_SIZE]; 1360 1361 jb_addr = read_register (O0_REGNUM); 1362 1363 if (target_read_memory (jb_addr + JB_PC * JB_ELEMENT_SIZE, buf, 1364 LONGJMP_TARGET_SIZE)) 1365 return 0; 1366 1367 *pc = extract_address (buf, LONGJMP_TARGET_SIZE); 1368 1369 return 1; 1370 } 1371 #endif /* GET_LONGJMP_TARGET */ 1372 1373 #ifdef STATIC_TRANSFORM_NAME 1374 /* SunPRO (3.0 at least), encodes the static variables. This is not 1375 related to C++ mangling, it is done for C too. */ 1376 1377 char * 1378 sunpro_static_transform_name (name) 1379 char *name; 1380 { 1381 char *p; 1382 if (name[0] == '$') 1383 { 1384 /* For file-local statics there will be a dollar sign, a bunch 1385 of junk (the contents of which match a string given in the 1386 N_OPT), a period and the name. For function-local statics 1387 there will be a bunch of junk (which seems to change the 1388 second character from 'A' to 'B'), a period, the name of the 1389 function, and the name. So just skip everything before the 1390 last period. */ 1391 p = strrchr (name, '.'); 1392 if (p != NULL) 1393 name = p + 1; 1394 } 1395 return name; 1396 } 1397 #endif /* STATIC_TRANSFORM_NAME */ 1398 1399 #ifdef GDB_TARGET_IS_SPARC64 1400 1401 /* Utilities for printing registers. 1402 Page numbers refer to the SPARC Architecture Manual. */ 1403 1404 static void dump_ccreg PARAMS ((char *, int)); 1405 1406 static void 1407 dump_ccreg (reg, val) 1408 char *reg; 1409 int val; 1410 { 1411 /* page 41 */ 1412 printf_unfiltered ("%s:%s,%s,%s,%s", reg, 1413 val & 8 ? "N" : "NN", 1414 val & 4 ? "Z" : "NZ", 1415 val & 2 ? "O" : "NO", 1416 val & 1 ? "C" : "NC" 1417 ); 1418 } 1419 1420 static char * 1421 decode_asi (val) 1422 int val; 1423 { 1424 /* page 72 */ 1425 switch (val) 1426 { 1427 case 4 : return "ASI_NUCLEUS"; 1428 case 0x0c : return "ASI_NUCLEUS_LITTLE"; 1429 case 0x10 : return "ASI_AS_IF_USER_PRIMARY"; 1430 case 0x11 : return "ASI_AS_IF_USER_SECONDARY"; 1431 case 0x18 : return "ASI_AS_IF_USER_PRIMARY_LITTLE"; 1432 case 0x19 : return "ASI_AS_IF_USER_SECONDARY_LITTLE"; 1433 case 0x80 : return "ASI_PRIMARY"; 1434 case 0x81 : return "ASI_SECONDARY"; 1435 case 0x82 : return "ASI_PRIMARY_NOFAULT"; 1436 case 0x83 : return "ASI_SECONDARY_NOFAULT"; 1437 case 0x88 : return "ASI_PRIMARY_LITTLE"; 1438 case 0x89 : return "ASI_SECONDARY_LITTLE"; 1439 case 0x8a : return "ASI_PRIMARY_NOFAULT_LITTLE"; 1440 case 0x8b : return "ASI_SECONDARY_NOFAULT_LITTLE"; 1441 default : return NULL; 1442 } 1443 } 1444 1445 /* PRINT_REGISTER_HOOK routine. 1446 Pretty print various registers. */ 1447 /* FIXME: Would be nice if this did some fancy things for 32 bit sparc. */ 1448 1449 void 1450 sparc_print_register_hook (regno) 1451 int regno; 1452 { 1453 unsigned LONGEST val; 1454 1455 /* Handle double/quad versions of lower 32 fp regs. */ 1456 if (regno >= FP0_REGNUM && regno < FP0_REGNUM + 32 1457 && (regno & 1) == 0) 1458 { 1459 char value[16]; 1460 1461 if (!read_relative_register_raw_bytes (regno, value) 1462 && !read_relative_register_raw_bytes (regno + 1, value + 4)) 1463 { 1464 printf_unfiltered ("\t"); 1465 print_floating (value, builtin_type_double, gdb_stdout); 1466 } 1467 #if 0 /* FIXME: gdb doesn't handle long doubles */ 1468 if ((regno & 3) == 0) 1469 { 1470 if (!read_relative_register_raw_bytes (regno + 2, value + 8) 1471 && !read_relative_register_raw_bytes (regno + 3, value + 12)) 1472 { 1473 printf_unfiltered ("\t"); 1474 print_floating (value, builtin_type_long_double, gdb_stdout); 1475 } 1476 } 1477 #endif 1478 return; 1479 } 1480 1481 #if 0 /* FIXME: gdb doesn't handle long doubles */ 1482 /* Print upper fp regs as long double if appropriate. */ 1483 if (regno >= FP0_REGNUM + 32 && regno < FP_MAX_REGNUM 1484 /* We test for even numbered regs and not a multiple of 4 because 1485 the upper fp regs are recorded as doubles. */ 1486 && (regno & 1) == 0) 1487 { 1488 char value[16]; 1489 1490 if (!read_relative_register_raw_bytes (regno, value) 1491 && !read_relative_register_raw_bytes (regno + 1, value + 8)) 1492 { 1493 printf_unfiltered ("\t"); 1494 print_floating (value, builtin_type_long_double, gdb_stdout); 1495 } 1496 return; 1497 } 1498 #endif 1499 1500 /* FIXME: Some of these are priviledged registers. 1501 Not sure how they should be handled. */ 1502 1503 #define BITS(n, mask) ((int) (((val) >> (n)) & (mask))) 1504 1505 val = read_register (regno); 1506 1507 /* pages 40 - 60 */ 1508 switch (regno) 1509 { 1510 case CCR_REGNUM : 1511 printf_unfiltered("\t"); 1512 dump_ccreg ("xcc", val >> 4); 1513 printf_unfiltered(", "); 1514 dump_ccreg ("icc", val & 15); 1515 break; 1516 case FPRS_REGNUM : 1517 printf ("\tfef:%d, du:%d, dl:%d", 1518 BITS (2, 1), BITS (1, 1), BITS (0, 1)); 1519 break; 1520 case FSR_REGNUM : 1521 { 1522 static char *fcc[4] = { "=", "<", ">", "?" }; 1523 static char *rd[4] = { "N", "0", "+", "-" }; 1524 /* Long, yes, but I'd rather leave it as is and use a wide screen. */ 1525 printf ("\t0:%s, 1:%s, 2:%s, 3:%s, rd:%s, tem:%d, ns:%d, ver:%d, ftt:%d, qne:%d, aexc:%d, cexc:%d", 1526 fcc[BITS (10, 3)], fcc[BITS (32, 3)], 1527 fcc[BITS (34, 3)], fcc[BITS (36, 3)], 1528 rd[BITS (30, 3)], BITS (23, 31), BITS (22, 1), BITS (17, 7), 1529 BITS (14, 7), BITS (13, 1), BITS (5, 31), BITS (0, 31)); 1530 break; 1531 } 1532 case ASI_REGNUM : 1533 { 1534 char *asi = decode_asi (val); 1535 if (asi != NULL) 1536 printf ("\t%s", asi); 1537 break; 1538 } 1539 case VER_REGNUM : 1540 printf ("\tmanuf:%d, impl:%d, mask:%d, maxtl:%d, maxwin:%d", 1541 BITS (48, 0xffff), BITS (32, 0xffff), 1542 BITS (24, 0xff), BITS (8, 0xff), BITS (0, 31)); 1543 break; 1544 case PSTATE_REGNUM : 1545 { 1546 static char *mm[4] = { "tso", "pso", "rso", "?" }; 1547 printf ("\tcle:%d, tle:%d, mm:%s, red:%d, pef:%d, am:%d, priv:%d, ie:%d, ag:%d", 1548 BITS (9, 1), BITS (8, 1), mm[BITS (6, 3)], BITS (5, 1), 1549 BITS (4, 1), BITS (3, 1), BITS (2, 1), BITS (1, 1), 1550 BITS (0, 1)); 1551 break; 1552 } 1553 case TSTATE_REGNUM : 1554 /* FIXME: print all 4? */ 1555 break; 1556 case TT_REGNUM : 1557 /* FIXME: print all 4? */ 1558 break; 1559 case TPC_REGNUM : 1560 /* FIXME: print all 4? */ 1561 break; 1562 case TNPC_REGNUM : 1563 /* FIXME: print all 4? */ 1564 break; 1565 case WSTATE_REGNUM : 1566 printf ("\tother:%d, normal:%d", BITS (3, 7), BITS (0, 7)); 1567 break; 1568 case CWP_REGNUM : 1569 printf ("\t%d", BITS (0, 31)); 1570 break; 1571 case CANSAVE_REGNUM : 1572 printf ("\t%-2d before spill", BITS (0, 31)); 1573 break; 1574 case CANRESTORE_REGNUM : 1575 printf ("\t%-2d before fill", BITS (0, 31)); 1576 break; 1577 case CLEANWIN_REGNUM : 1578 printf ("\t%-2d before clean", BITS (0, 31)); 1579 break; 1580 case OTHERWIN_REGNUM : 1581 printf ("\t%d", BITS (0, 31)); 1582 break; 1583 } 1584 1585 #undef BITS 1586 } 1587 1588 #endif 1589 1590 void 1591 _initialize_sparc_tdep () 1592 { 1593 tm_print_insn = print_insn_sparc; 1594 tm_print_insn_info.mach = TM_PRINT_INSN_MACH; /* Selects sparc/sparclite */ 1595 } 1596 1597 #ifdef GDB_TARGET_IS_SPARC64 1598 1599 /* Compensate for stack bias. Note that we currently don't handle 1600 mixed 32/64 bit code. */ 1601 1602 CORE_ADDR 1603 sparc64_read_sp (void) 1604 { 1605 CORE_ADDR sp = read_register (SP_REGNUM); 1606 1607 if (sp & 1) 1608 sp += 2047; 1609 return sp; 1610 } 1611 1612 CORE_ADDR 1613 sparc64_read_fp (void) 1614 { 1615 CORE_ADDR fp = read_register (FP_REGNUM); 1616 1617 if (fp & 1) 1618 fp += 2047; 1619 return fp; 1620 } 1621 1622 void 1623 sparc64_write_sp (CORE_ADDR val) 1624 { 1625 CORE_ADDR oldsp = read_register (SP_REGNUM); 1626 if (oldsp & 1) 1627 write_register (SP_REGNUM, val - 2047); 1628 else 1629 write_register (SP_REGNUM, val); 1630 } 1631 1632 void 1633 sparc64_write_fp (CORE_ADDR val) 1634 { 1635 CORE_ADDR oldfp = read_register (FP_REGNUM); 1636 if (oldfp & 1) 1637 write_register (FP_REGNUM, val - 2047); 1638 else 1639 write_register (FP_REGNUM, val); 1640 } 1641 1642 #endif 1643