1 /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger. 2 Copyright 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995 3 Free Software Foundation, Inc. 4 Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU 5 and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin. 6 7 This file is part of GDB. 8 9 This program is free software; you can redistribute it and/or modify 10 it under the terms of the GNU General Public License as published by 11 the Free Software Foundation; either version 2 of the License, or 12 (at your option) any later version. 13 14 This program is distributed in the hope that it will be useful, 15 but WITHOUT ANY WARRANTY; without even the implied warranty of 16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 GNU General Public License for more details. 18 19 You should have received a copy of the GNU General Public License 20 along with this program; if not, write to the Free Software 21 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ 22 23 #include "defs.h" 24 #include "gdb_string.h" 25 #include "frame.h" 26 #include "inferior.h" 27 #include "symtab.h" 28 #include "value.h" 29 #include "gdbcmd.h" 30 #include "language.h" 31 #include "gdbcore.h" 32 #include "symfile.h" 33 #include "objfiles.h" 34 #include "gdbtypes.h" 35 #include "target.h" 36 37 #include "opcode/mips.h" 38 39 #define VM_MIN_ADDRESS (CORE_ADDR)0x400000 40 41 /* FIXME: Put this declaration in frame.h. */ 42 extern struct obstack frame_cache_obstack; 43 44 /* FIXME! this code assumes 4-byte instructions. */ 45 #define MIPS_INSTLEN 4 46 #define MIPS_NUMREGS 32 /* FIXME! how many on 64-bit mips? */ 47 typedef unsigned long t_inst; 48 49 50 #if 0 51 static int mips_in_lenient_prologue PARAMS ((CORE_ADDR, CORE_ADDR)); 52 #endif 53 54 static int gdb_print_insn_mips PARAMS ((bfd_vma, disassemble_info *)); 55 56 static void mips_print_register PARAMS ((int, int)); 57 58 static mips_extra_func_info_t 59 heuristic_proc_desc PARAMS ((CORE_ADDR, CORE_ADDR, struct frame_info *)); 60 61 static CORE_ADDR heuristic_proc_start PARAMS ((CORE_ADDR)); 62 63 static CORE_ADDR read_next_frame_reg PARAMS ((struct frame_info *, int)); 64 65 static void mips_set_fpu_command PARAMS ((char *, int, 66 struct cmd_list_element *)); 67 68 static void mips_show_fpu_command PARAMS ((char *, int, 69 struct cmd_list_element *)); 70 71 void mips_set_processor_type_command PARAMS ((char *, int)); 72 73 int mips_set_processor_type PARAMS ((char *)); 74 75 static void mips_show_processor_type_command PARAMS ((char *, int)); 76 77 static void reinit_frame_cache_sfunc PARAMS ((char *, int, 78 struct cmd_list_element *)); 79 80 static mips_extra_func_info_t 81 find_proc_desc PARAMS ((CORE_ADDR pc, struct frame_info *next_frame)); 82 83 static CORE_ADDR after_prologue PARAMS ((CORE_ADDR pc, 84 mips_extra_func_info_t proc_desc)); 85 86 /* This value is the model of MIPS in use. It is derived from the value 87 of the PrID register. */ 88 89 char *mips_processor_type; 90 91 char *tmp_mips_processor_type; 92 93 /* Some MIPS boards don't support floating point, so we permit the 94 user to turn it off. */ 95 96 enum mips_fpu_type mips_fpu; 97 98 static char *mips_fpu_string; 99 100 /* A set of original names, to be used when restoring back to generic 101 registers from a specific set. */ 102 103 char *mips_generic_reg_names[] = REGISTER_NAMES; 104 105 /* Names of IDT R3041 registers. */ 106 107 char *mips_r3041_reg_names[] = { 108 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", 109 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", 110 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 111 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", 112 "sr", "lo", "hi", "bad", "cause","pc", 113 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", 114 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", 115 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", 116 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", 117 "fsr", "fir", "fp", "", 118 "", "", "bus", "ccfg", "", "", "", "", 119 "", "", "port", "cmp", "", "", "epc", "prid", 120 }; 121 122 /* Names of IDT R3051 registers. */ 123 124 char *mips_r3051_reg_names[] = { 125 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", 126 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", 127 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 128 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", 129 "sr", "lo", "hi", "bad", "cause","pc", 130 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", 131 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", 132 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", 133 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", 134 "fsr", "fir", "fp", "", 135 "inx", "rand", "elo", "", "ctxt", "", "", "", 136 "", "", "ehi", "", "", "", "epc", "prid", 137 }; 138 139 /* Names of IDT R3081 registers. */ 140 141 char *mips_r3081_reg_names[] = { 142 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", 143 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", 144 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 145 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", 146 "sr", "lo", "hi", "bad", "cause","pc", 147 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", 148 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", 149 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", 150 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", 151 "fsr", "fir", "fp", "", 152 "inx", "rand", "elo", "cfg", "ctxt", "", "", "", 153 "", "", "ehi", "", "", "", "epc", "prid", 154 }; 155 156 /* Names of LSI 33k registers. */ 157 158 char *mips_lsi33k_reg_names[] = { 159 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", 160 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", 161 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 162 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", 163 "epc", "hi", "lo", "sr", "cause","badvaddr", 164 "dcic", "bpc", "bda", "", "", "", "", "", 165 "", "", "", "", "", "", "", "", 166 "", "", "", "", "", "", "", "", 167 "", "", "", "", "", "", "", "", 168 "", "", "", "", 169 "", "", "", "", "", "", "", "", 170 "", "", "", "", "", "", "", "", 171 }; 172 173 struct { 174 char *name; 175 char **regnames; 176 } mips_processor_type_table[] = { 177 { "generic", mips_generic_reg_names }, 178 { "r3041", mips_r3041_reg_names }, 179 { "r3051", mips_r3051_reg_names }, 180 { "r3071", mips_r3081_reg_names }, 181 { "r3081", mips_r3081_reg_names }, 182 { "lsi33k", mips_lsi33k_reg_names }, 183 { NULL, NULL } 184 }; 185 186 /* Heuristic_proc_start may hunt through the text section for a long 187 time across a 2400 baud serial line. Allows the user to limit this 188 search. */ 189 190 static unsigned int heuristic_fence_post = 0; 191 192 #define PROC_LOW_ADDR(proc) ((proc)->pdr.adr) /* least address */ 193 #define PROC_HIGH_ADDR(proc) ((proc)->high_addr) /* upper address bound */ 194 #define PROC_FRAME_OFFSET(proc) ((proc)->pdr.frameoffset) 195 #define PROC_FRAME_REG(proc) ((proc)->pdr.framereg) 196 #define PROC_REG_MASK(proc) ((proc)->pdr.regmask) 197 #define PROC_FREG_MASK(proc) ((proc)->pdr.fregmask) 198 #define PROC_REG_OFFSET(proc) ((proc)->pdr.regoffset) 199 #define PROC_FREG_OFFSET(proc) ((proc)->pdr.fregoffset) 200 #define PROC_PC_REG(proc) ((proc)->pdr.pcreg) 201 #define PROC_SYMBOL(proc) (*(struct symbol**)&(proc)->pdr.isym) 202 #define _PROC_MAGIC_ 0x0F0F0F0F 203 #define PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym == _PROC_MAGIC_) 204 #define SET_PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym = _PROC_MAGIC_) 205 206 struct linked_proc_info 207 { 208 struct mips_extra_func_info info; 209 struct linked_proc_info *next; 210 } *linked_proc_desc_table = NULL; 211 212 213 214 /* This returns the PC of the first inst after the prologue. If we can't 215 find the prologue, then return 0. */ 216 217 static CORE_ADDR 218 after_prologue (pc, proc_desc) 219 CORE_ADDR pc; 220 mips_extra_func_info_t proc_desc; 221 { 222 struct symtab_and_line sal; 223 CORE_ADDR func_addr, func_end; 224 225 if (!proc_desc) 226 proc_desc = find_proc_desc (pc, NULL); 227 228 if (proc_desc) 229 { 230 /* If function is frameless, then we need to do it the hard way. I 231 strongly suspect that frameless always means prologueless... */ 232 if (PROC_FRAME_REG (proc_desc) == SP_REGNUM 233 && PROC_FRAME_OFFSET (proc_desc) == 0) 234 return 0; 235 } 236 237 if (!find_pc_partial_function (pc, NULL, &func_addr, &func_end)) 238 return 0; /* Unknown */ 239 240 sal = find_pc_line (func_addr, 0); 241 242 if (sal.end < func_end) 243 return sal.end; 244 245 /* The line after the prologue is after the end of the function. In this 246 case, tell the caller to find the prologue the hard way. */ 247 248 return 0; 249 } 250 251 /* Guaranteed to set fci->saved_regs to some values (it never leaves it 252 NULL). */ 253 254 void 255 mips_find_saved_regs (fci) 256 struct frame_info *fci; 257 { 258 int ireg; 259 CORE_ADDR reg_position; 260 /* r0 bit means kernel trap */ 261 int kernel_trap; 262 /* What registers have been saved? Bitmasks. */ 263 unsigned long gen_mask, float_mask; 264 mips_extra_func_info_t proc_desc; 265 266 fci->saved_regs = (struct frame_saved_regs *) 267 obstack_alloc (&frame_cache_obstack, sizeof(struct frame_saved_regs)); 268 memset (fci->saved_regs, 0, sizeof (struct frame_saved_regs)); 269 270 /* If it is the frame for sigtramp, the saved registers are located 271 in a sigcontext structure somewhere on the stack. 272 If the stack layout for sigtramp changes we might have to change these 273 constants and the companion fixup_sigtramp in mdebugread.c */ 274 #ifndef SIGFRAME_BASE 275 /* To satisfy alignment restrictions, sigcontext is located 4 bytes 276 above the sigtramp frame. */ 277 #define SIGFRAME_BASE MIPS_REGSIZE 278 /* FIXME! Are these correct?? */ 279 #define SIGFRAME_PC_OFF (SIGFRAME_BASE + 2 * MIPS_REGSIZE) 280 #define SIGFRAME_REGSAVE_OFF (SIGFRAME_BASE + 3 * MIPS_REGSIZE) 281 #define SIGFRAME_FPREGSAVE_OFF \ 282 (SIGFRAME_REGSAVE_OFF + MIPS_NUMREGS * MIPS_REGSIZE + 3 * MIPS_REGSIZE) 283 #endif 284 #ifndef SIGFRAME_REG_SIZE 285 /* FIXME! Is this correct?? */ 286 #define SIGFRAME_REG_SIZE MIPS_REGSIZE 287 #endif 288 if (fci->signal_handler_caller) 289 { 290 for (ireg = 0; ireg < MIPS_NUMREGS; ireg++) 291 { 292 reg_position = fci->frame + SIGFRAME_REGSAVE_OFF 293 + ireg * SIGFRAME_REG_SIZE; 294 fci->saved_regs->regs[ireg] = reg_position; 295 } 296 for (ireg = 0; ireg < MIPS_NUMREGS; ireg++) 297 { 298 reg_position = fci->frame + SIGFRAME_FPREGSAVE_OFF 299 + ireg * SIGFRAME_REG_SIZE; 300 fci->saved_regs->regs[FP0_REGNUM + ireg] = reg_position; 301 } 302 fci->saved_regs->regs[PC_REGNUM] = fci->frame + SIGFRAME_PC_OFF; 303 return; 304 } 305 306 proc_desc = fci->proc_desc; 307 if (proc_desc == NULL) 308 /* I'm not sure how/whether this can happen. Normally when we can't 309 find a proc_desc, we "synthesize" one using heuristic_proc_desc 310 and set the saved_regs right away. */ 311 return; 312 313 kernel_trap = PROC_REG_MASK(proc_desc) & 1; 314 gen_mask = kernel_trap ? 0xFFFFFFFF : PROC_REG_MASK(proc_desc); 315 float_mask = kernel_trap ? 0xFFFFFFFF : PROC_FREG_MASK(proc_desc); 316 317 if (/* In any frame other than the innermost, we assume that all 318 registers have been saved. This assumes that all register 319 saves in a function happen before the first function 320 call. */ 321 fci->next == NULL 322 323 /* In a dummy frame we know exactly where things are saved. */ 324 && !PROC_DESC_IS_DUMMY (proc_desc) 325 326 /* Don't bother unless we are inside a function prologue. Outside the 327 prologue, we know where everything is. */ 328 329 && in_prologue (fci->pc, PROC_LOW_ADDR (proc_desc)) 330 331 /* Not sure exactly what kernel_trap means, but if it means 332 the kernel saves the registers without a prologue doing it, 333 we better not examine the prologue to see whether registers 334 have been saved yet. */ 335 && !kernel_trap) 336 { 337 /* We need to figure out whether the registers that the proc_desc 338 claims are saved have been saved yet. */ 339 340 CORE_ADDR addr; 341 int status; 342 char buf[MIPS_INSTLEN]; 343 t_inst inst; 344 345 /* Bitmasks; set if we have found a save for the register. */ 346 unsigned long gen_save_found = 0; 347 unsigned long float_save_found = 0; 348 349 for (addr = PROC_LOW_ADDR (proc_desc); 350 addr < fci->pc /*&& (gen_mask != gen_save_found 351 || float_mask != float_save_found)*/; 352 addr += MIPS_INSTLEN) 353 { 354 status = read_memory_nobpt (addr, buf, MIPS_INSTLEN); 355 if (status) 356 memory_error (status, addr); 357 inst = extract_unsigned_integer (buf, MIPS_INSTLEN); 358 if (/* sw reg,n($sp) */ 359 (inst & 0xffe00000) == 0xafa00000 360 361 /* sw reg,n($r30) */ 362 || (inst & 0xffe00000) == 0xafc00000 363 364 /* sd reg,n($sp) */ 365 || (inst & 0xffe00000) == 0xffa00000) 366 { 367 /* It might be possible to use the instruction to 368 find the offset, rather than the code below which 369 is based on things being in a certain order in the 370 frame, but figuring out what the instruction's offset 371 is relative to might be a little tricky. */ 372 int reg = (inst & 0x001f0000) >> 16; 373 gen_save_found |= (1 << reg); 374 } 375 else if (/* swc1 freg,n($sp) */ 376 (inst & 0xffe00000) == 0xe7a00000 377 378 /* swc1 freg,n($r30) */ 379 || (inst & 0xffe00000) == 0xe7c00000 380 381 /* sdc1 freg,n($sp) */ 382 || (inst & 0xffe00000) == 0xf7a00000) 383 384 { 385 int reg = ((inst & 0x001f0000) >> 16); 386 float_save_found |= (1 << reg); 387 } 388 } 389 gen_mask = gen_save_found; 390 float_mask = float_save_found; 391 } 392 393 /* Fill in the offsets for the registers which gen_mask says 394 were saved. */ 395 reg_position = fci->frame + PROC_REG_OFFSET (proc_desc); 396 for (ireg= MIPS_NUMREGS-1; gen_mask; --ireg, gen_mask <<= 1) 397 if (gen_mask & 0x80000000) 398 { 399 fci->saved_regs->regs[ireg] = reg_position; 400 reg_position -= MIPS_REGSIZE; 401 } 402 /* Fill in the offsets for the registers which float_mask says 403 were saved. */ 404 reg_position = fci->frame + PROC_FREG_OFFSET (proc_desc); 405 406 /* The freg_offset points to where the first *double* register 407 is saved. So skip to the high-order word. */ 408 if (! GDB_TARGET_IS_MIPS64) 409 reg_position += 4; 410 411 /* FIXME! this code looks scary... 412 * Looks like it's trying to do stuff with a register, 413 * but .... ??? 414 */ 415 for (ireg = MIPS_NUMREGS-1; float_mask; --ireg, float_mask <<= 1) 416 if (float_mask & 0x80000000) 417 { 418 fci->saved_regs->regs[FP0_REGNUM+ireg] = reg_position; 419 reg_position -= MIPS_REGSIZE; 420 } 421 422 fci->saved_regs->regs[PC_REGNUM] = fci->saved_regs->regs[RA_REGNUM]; 423 } 424 425 static CORE_ADDR 426 read_next_frame_reg(fi, regno) 427 struct frame_info *fi; 428 int regno; 429 { 430 for (; fi; fi = fi->next) 431 { 432 /* We have to get the saved sp from the sigcontext 433 if it is a signal handler frame. */ 434 if (regno == SP_REGNUM && !fi->signal_handler_caller) 435 return fi->frame; 436 else 437 { 438 if (fi->saved_regs == NULL) 439 mips_find_saved_regs (fi); 440 if (fi->saved_regs->regs[regno]) 441 return read_memory_integer(fi->saved_regs->regs[regno], MIPS_REGSIZE); 442 } 443 } 444 return read_register (regno); 445 } 446 447 static CORE_ADDR 448 fix_sign_extension (addr) 449 CORE_ADDR addr; 450 { 451 if (GDB_TARGET_IS_MIPS64 452 && (addr >> 32 == (CORE_ADDR)0xffffffff) 453 && (strcmp(target_shortname,"pmon")==0 454 || strcmp(target_shortname,"ddb")==0)) 455 { 456 /* This hack is a work-around for PMON. 457 * The PMON version in the Vr4300 board has been 458 * compiled without the 64bit register access commands. 459 * Thus, the upper word of the PC or SP may be sign extended to all 1s. 460 * If so, change it to zero. */ 461 addr &= (CORE_ADDR)0xffffffff; 462 } 463 464 return addr; 465 } 466 467 CORE_ADDR 468 mips_frame_saved_pc(frame) 469 struct frame_info *frame; 470 { 471 CORE_ADDR saved_pc; 472 mips_extra_func_info_t proc_desc = frame->proc_desc; 473 /* We have to get the saved pc from the sigcontext 474 if it is a signal handler frame. */ 475 int pcreg = frame->signal_handler_caller ? PC_REGNUM 476 : (proc_desc ? PROC_PC_REG(proc_desc) : RA_REGNUM); 477 478 if (proc_desc && PROC_DESC_IS_DUMMY(proc_desc)) 479 saved_pc = read_memory_integer(frame->frame - MIPS_REGSIZE, MIPS_REGSIZE); 480 else 481 saved_pc = read_next_frame_reg(frame, pcreg); 482 483 return fix_sign_extension (saved_pc); 484 } 485 486 static struct mips_extra_func_info temp_proc_desc; 487 static struct frame_saved_regs temp_saved_regs; 488 489 /* This fencepost looks highly suspicious to me. Removing it also 490 seems suspicious as it could affect remote debugging across serial 491 lines. */ 492 493 static CORE_ADDR 494 heuristic_proc_start(pc) 495 CORE_ADDR pc; 496 { 497 CORE_ADDR start_pc = pc; 498 CORE_ADDR fence = start_pc - heuristic_fence_post; 499 500 if (start_pc == 0) return 0; 501 502 if (heuristic_fence_post == UINT_MAX 503 || fence < VM_MIN_ADDRESS) 504 fence = VM_MIN_ADDRESS; 505 506 /* search back for previous return */ 507 for (start_pc -= MIPS_INSTLEN; ; start_pc -= MIPS_INSTLEN) /* FIXME!! */ 508 if (start_pc < fence) 509 { 510 /* It's not clear to me why we reach this point when 511 stop_soon_quietly, but with this test, at least we 512 don't print out warnings for every child forked (eg, on 513 decstation). 22apr93 rich@cygnus.com. */ 514 if (!stop_soon_quietly) 515 { 516 static int blurb_printed = 0; 517 518 if (fence == VM_MIN_ADDRESS) 519 warning("Hit beginning of text section without finding"); 520 else 521 warning("Hit heuristic-fence-post without finding"); 522 523 warning("enclosing function for address 0x%x", pc); 524 if (!blurb_printed) 525 { 526 printf_filtered ("\ 527 This warning occurs if you are debugging a function without any symbols\n\ 528 (for example, in a stripped executable). In that case, you may wish to\n\ 529 increase the size of the search with the `set heuristic-fence-post' command.\n\ 530 \n\ 531 Otherwise, you told GDB there was a function where there isn't one, or\n\ 532 (more likely) you have encountered a bug in GDB.\n"); 533 blurb_printed = 1; 534 } 535 } 536 537 return 0; 538 } 539 else if (ABOUT_TO_RETURN(start_pc)) 540 break; 541 542 start_pc += 8; /* skip return, and its delay slot */ /* FIXME!! */ 543 #if 0 544 /* skip nops (usually 1) 0 - is this */ 545 while (start_pc < pc && read_memory_integer (start_pc, MIPS_INSTLEN) == 0) 546 start_pc += MIPS_INSTLEN; 547 #endif 548 return start_pc; 549 } 550 551 static mips_extra_func_info_t 552 heuristic_proc_desc(start_pc, limit_pc, next_frame) 553 CORE_ADDR start_pc, limit_pc; 554 struct frame_info *next_frame; 555 { 556 CORE_ADDR sp = read_next_frame_reg (next_frame, SP_REGNUM); 557 CORE_ADDR cur_pc; 558 unsigned long frame_size; 559 int has_frame_reg = 0; 560 CORE_ADDR reg30 = 0; /* Value of $r30. Used by gcc for frame-pointer */ 561 unsigned long reg_mask = 0; 562 563 if (start_pc == 0) return NULL; 564 memset (&temp_proc_desc, '\0', sizeof(temp_proc_desc)); 565 memset (&temp_saved_regs, '\0', sizeof(struct frame_saved_regs)); 566 PROC_LOW_ADDR (&temp_proc_desc) = start_pc; 567 568 if (start_pc + 200 < limit_pc) 569 limit_pc = start_pc + 200; 570 restart: 571 frame_size = 0; 572 for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += MIPS_INSTLEN) { 573 char buf[MIPS_INSTLEN]; 574 unsigned long word; 575 int status; 576 577 status = (unsigned long) read_memory_nobpt (cur_pc, buf, MIPS_INSTLEN); /* FIXME!! */ 578 if (status) memory_error (status, cur_pc); 579 word = (unsigned long) extract_unsigned_integer (buf, MIPS_INSTLEN); /* FIXME!! */ 580 581 if ((word & 0xFFFF0000) == 0x27bd0000) /* addiu $sp,$sp,-i */ 582 frame_size += (-word) & 0xFFFF; 583 else if ((word & 0xFFFF0000) == 0x23bd0000) /* addu $sp,$sp,-i */ 584 frame_size += (-word) & 0xFFFF; 585 else if ((word & 0xFFE00000) == 0xafa00000) { /* sw reg,offset($sp) */ 586 int reg = (word & 0x001F0000) >> 16; 587 reg_mask |= 1 << reg; 588 temp_saved_regs.regs[reg] = sp + (word & 0xffff); 589 } 590 else if ((word & 0xFFFF0000) == 0x27be0000) { /* addiu $30,$sp,size */ 591 if ((word & 0xffff) != frame_size) 592 reg30 = sp + (word & 0xffff); 593 else if (!has_frame_reg) { 594 unsigned alloca_adjust; 595 has_frame_reg = 1; 596 reg30 = read_next_frame_reg(next_frame, 30); 597 alloca_adjust = (unsigned)(reg30 - (sp + (word & 0xffff))); 598 if (alloca_adjust > 0) { 599 /* FP > SP + frame_size. This may be because 600 * of an alloca or somethings similar. 601 * Fix sp to "pre-alloca" value, and try again. 602 */ 603 sp += alloca_adjust; 604 goto restart; 605 } 606 } 607 } 608 else if ((word & 0xFFE00000) == 0xafc00000) { /* sw reg,offset($30) */ 609 int reg = (word & 0x001F0000) >> 16; 610 reg_mask |= 1 << reg; 611 temp_saved_regs.regs[reg] = reg30 + (word & 0xffff); 612 } 613 } 614 if (has_frame_reg) { 615 PROC_FRAME_REG(&temp_proc_desc) = 30; 616 PROC_FRAME_OFFSET(&temp_proc_desc) = 0; 617 } 618 else { 619 PROC_FRAME_REG(&temp_proc_desc) = SP_REGNUM; 620 PROC_FRAME_OFFSET(&temp_proc_desc) = frame_size; 621 } 622 PROC_REG_MASK(&temp_proc_desc) = reg_mask; 623 PROC_PC_REG(&temp_proc_desc) = RA_REGNUM; 624 return &temp_proc_desc; 625 } 626 627 static mips_extra_func_info_t 628 find_proc_desc (pc, next_frame) 629 CORE_ADDR pc; 630 struct frame_info *next_frame; 631 { 632 mips_extra_func_info_t proc_desc; 633 struct block *b = block_for_pc(pc); 634 struct symbol *sym; 635 CORE_ADDR startaddr; 636 637 find_pc_partial_function (pc, NULL, &startaddr, NULL); 638 if (b == NULL) 639 sym = NULL; 640 else 641 { 642 if (startaddr > BLOCK_START (b)) 643 /* This is the "pathological" case referred to in a comment in 644 print_frame_info. It might be better to move this check into 645 symbol reading. */ 646 sym = NULL; 647 else 648 sym = lookup_symbol (MIPS_EFI_SYMBOL_NAME, b, LABEL_NAMESPACE, 649 0, NULL); 650 } 651 652 /* If we never found a PDR for this function in symbol reading, then 653 examine prologues to find the information. */ 654 if (sym && ((mips_extra_func_info_t) SYMBOL_VALUE (sym))->pdr.framereg == -1) 655 sym = NULL; 656 657 if (sym) 658 { 659 /* IF this is the topmost frame AND 660 * (this proc does not have debugging information OR 661 * the PC is in the procedure prologue) 662 * THEN create a "heuristic" proc_desc (by analyzing 663 * the actual code) to replace the "official" proc_desc. 664 */ 665 proc_desc = (mips_extra_func_info_t) SYMBOL_VALUE (sym); 666 if (next_frame == NULL) { 667 struct symtab_and_line val; 668 struct symbol *proc_symbol = 669 PROC_DESC_IS_DUMMY(proc_desc) ? 0 : PROC_SYMBOL(proc_desc); 670 671 if (proc_symbol) { 672 val = find_pc_line (BLOCK_START 673 (SYMBOL_BLOCK_VALUE(proc_symbol)), 674 0); 675 val.pc = val.end ? val.end : pc; 676 } 677 if (!proc_symbol || pc < val.pc) { 678 mips_extra_func_info_t found_heuristic = 679 heuristic_proc_desc (PROC_LOW_ADDR (proc_desc), 680 pc, next_frame); 681 if (found_heuristic) 682 proc_desc = found_heuristic; 683 } 684 } 685 } 686 else 687 { 688 /* Is linked_proc_desc_table really necessary? It only seems to be used 689 by procedure call dummys. However, the procedures being called ought 690 to have their own proc_descs, and even if they don't, 691 heuristic_proc_desc knows how to create them! */ 692 693 register struct linked_proc_info *link; 694 695 for (link = linked_proc_desc_table; link; link = link->next) 696 if (PROC_LOW_ADDR(&link->info) <= pc 697 && PROC_HIGH_ADDR(&link->info) > pc) 698 return &link->info; 699 700 if (startaddr == 0) 701 startaddr = heuristic_proc_start (pc); 702 703 proc_desc = 704 heuristic_proc_desc (startaddr, pc, next_frame); 705 } 706 return proc_desc; 707 } 708 709 static CORE_ADDR 710 get_frame_pointer(frame, proc_desc) 711 struct frame_info *frame; 712 mips_extra_func_info_t proc_desc; 713 { 714 return fix_sign_extension (read_next_frame_reg (frame, 715 PROC_FRAME_REG(proc_desc)) + PROC_FRAME_OFFSET(proc_desc)); 716 } 717 718 mips_extra_func_info_t cached_proc_desc; 719 720 CORE_ADDR 721 mips_frame_chain(frame) 722 struct frame_info *frame; 723 { 724 mips_extra_func_info_t proc_desc; 725 CORE_ADDR saved_pc = FRAME_SAVED_PC(frame); 726 727 if (saved_pc == 0 || inside_entry_file (saved_pc)) 728 return 0; 729 730 proc_desc = find_proc_desc(saved_pc, frame); 731 if (!proc_desc) 732 return 0; 733 734 cached_proc_desc = proc_desc; 735 736 /* If no frame pointer and frame size is zero, we must be at end 737 of stack (or otherwise hosed). If we don't check frame size, 738 we loop forever if we see a zero size frame. */ 739 if (PROC_FRAME_REG (proc_desc) == SP_REGNUM 740 && PROC_FRAME_OFFSET (proc_desc) == 0 741 /* The previous frame from a sigtramp frame might be frameless 742 and have frame size zero. */ 743 && !frame->signal_handler_caller) 744 return 0; 745 else 746 return get_frame_pointer (frame, proc_desc); 747 } 748 749 void 750 init_extra_frame_info(fci) 751 struct frame_info *fci; 752 { 753 /* Use proc_desc calculated in frame_chain */ 754 mips_extra_func_info_t proc_desc = 755 fci->next ? cached_proc_desc : find_proc_desc(fci->pc, fci->next); 756 757 fci->saved_regs = NULL; 758 fci->proc_desc = 759 proc_desc == &temp_proc_desc ? 0 : proc_desc; 760 if (proc_desc) 761 { 762 /* Fixup frame-pointer - only needed for top frame */ 763 /* This may not be quite right, if proc has a real frame register. 764 Get the value of the frame relative sp, procedure might have been 765 interrupted by a signal at it's very start. */ 766 if (fci->pc == PROC_LOW_ADDR (proc_desc) 767 && !PROC_DESC_IS_DUMMY (proc_desc)) 768 fci->frame = read_next_frame_reg (fci->next, SP_REGNUM); 769 else 770 fci->frame = get_frame_pointer (fci->next, proc_desc); 771 772 if (proc_desc == &temp_proc_desc) 773 { 774 char *name; 775 776 /* Do not set the saved registers for a sigtramp frame, 777 mips_find_saved_registers will do that for us. 778 We can't use fci->signal_handler_caller, it is not yet set. */ 779 find_pc_partial_function (fci->pc, &name, 780 (CORE_ADDR *)NULL,(CORE_ADDR *)NULL); 781 if (!IN_SIGTRAMP (fci->pc, name)) 782 { 783 fci->saved_regs = (struct frame_saved_regs*) 784 obstack_alloc (&frame_cache_obstack, 785 sizeof (struct frame_saved_regs)); 786 *fci->saved_regs = temp_saved_regs; 787 fci->saved_regs->regs[PC_REGNUM] 788 = fci->saved_regs->regs[RA_REGNUM]; 789 } 790 } 791 792 /* hack: if argument regs are saved, guess these contain args */ 793 if ((PROC_REG_MASK(proc_desc) & 0xF0) == 0) fci->num_args = -1; 794 /* FIXME! Increase this for MIPS EABI */ 795 else if ((PROC_REG_MASK(proc_desc) & 0x80) == 0) fci->num_args = 4; 796 else if ((PROC_REG_MASK(proc_desc) & 0x40) == 0) fci->num_args = 3; 797 else if ((PROC_REG_MASK(proc_desc) & 0x20) == 0) fci->num_args = 2; 798 else if ((PROC_REG_MASK(proc_desc) & 0x10) == 0) fci->num_args = 1; 799 } 800 } 801 802 /* MIPS stack frames are almost impenetrable. When execution stops, 803 we basically have to look at symbol information for the function 804 that we stopped in, which tells us *which* register (if any) is 805 the base of the frame pointer, and what offset from that register 806 the frame itself is at. 807 808 This presents a problem when trying to examine a stack in memory 809 (that isn't executing at the moment), using the "frame" command. We 810 don't have a PC, nor do we have any registers except SP. 811 812 This routine takes two arguments, SP and PC, and tries to make the 813 cached frames look as if these two arguments defined a frame on the 814 cache. This allows the rest of info frame to extract the important 815 arguments without difficulty. */ 816 817 struct frame_info * 818 setup_arbitrary_frame (argc, argv) 819 int argc; 820 CORE_ADDR *argv; 821 { 822 if (argc != 2) 823 error ("MIPS frame specifications require two arguments: sp and pc"); 824 825 return create_new_frame (argv[0], argv[1]); 826 } 827 828 829 CORE_ADDR 830 mips_push_arguments(nargs, args, sp, struct_return, struct_addr) 831 int nargs; 832 value_ptr *args; 833 CORE_ADDR sp; 834 int struct_return; 835 CORE_ADDR struct_addr; 836 { 837 register i; 838 int accumulate_size; 839 struct mips_arg { char *contents; int len; int offset; }; 840 struct mips_arg *mips_args; 841 register struct mips_arg *m_arg; 842 int fake_args = 0; 843 int len; 844 845 /* Macro to round n up to the next a boundary (a must be a power of two) */ 846 #define ALIGN(n,a) (((n)+(a)-1) & ~((a)-1)) 847 848 /* First ensure that the stack and structure return address (if any) 849 are properly aligned. */ 850 851 sp = ALIGN (sp, MIPS_REGSIZE); 852 struct_addr = ALIGN (struct_addr, MIPS_REGSIZE); 853 854 accumulate_size = struct_return ? MIPS_REGSIZE : 0; 855 856 /* Allocate descriptors for each argument, plus some extras for the 857 dummies we will create to zero-fill the holes left when we align 858 arguments passed in registers that are smaller than a register. */ 859 mips_args = /* FIXME! Should this 4 be increased for MIPS64? */ 860 (struct mips_arg*) alloca ((nargs + 4) * sizeof (struct mips_arg)); 861 862 /* Build up the list of argument descriptors. */ 863 for (i = 0, m_arg = mips_args; i < nargs; i++, m_arg++) { 864 value_ptr arg = args[i]; 865 len = m_arg->len = TYPE_LENGTH (VALUE_TYPE (arg)); 866 /* This entire mips-specific routine is because doubles must be aligned 867 * on 8-byte boundaries. It still isn't quite right, because MIPS decided 868 * to align 'struct {int a, b}' on 4-byte boundaries (even though this 869 * breaks their varargs implementation...). A correct solution 870 * requires an simulation of gcc's 'alignof' (and use of 'alignof' 871 * in stdarg.h/varargs.h). 872 * On the 64 bit r4000 we always pass the first four arguments 873 * using eight bytes each, so that we can load them up correctly 874 * in CALL_DUMMY. 875 */ 876 if (len > 4) /* FIXME? */ 877 accumulate_size = ALIGN (accumulate_size, 8); 878 m_arg->offset = accumulate_size; 879 m_arg->contents = VALUE_CONTENTS(arg); 880 if (! GDB_TARGET_IS_MIPS64) 881 /* For 32-bit targets, align the next argument on a 32-bit boundary. */ 882 accumulate_size = ALIGN (accumulate_size + len, 4); 883 else 884 { 885 /* If the argument is being passed on the stack, not a register, 886 adjust the size of the argument upward to account for stack 887 alignment. The EABI allows 8 arguments to be passed in 888 registers; the old ABI allows only four. This code seems 889 bogus to me: shouldn't we be right-aligning small arguments 890 as we do below for the args-in-registers case? FIXME!! */ 891 #if MIPS_EABI 892 if (accumulate_size >= 8 * MIPS_REGSIZE) /* Ignores FP. FIXME!! */ 893 accumulate_size = ALIGN (accumulate_size + len, 8); 894 #else 895 if (accumulate_size >= 4 * MIPS_REGSIZE) 896 accumulate_size = ALIGN (accumulate_size + len, 4); 897 #endif 898 else 899 { 900 if (len < MIPS_REGSIZE) 901 { 902 /* The argument is being passed in a register, but is smaller 903 than a register. So it it must be right-aligned in the 904 register image being placed in the stack, and the rest 905 of the register image must be zero-filled. */ 906 static char zeroes[MIPS_REGSIZE] = { 0 }; 907 908 /* Align the arg in the rightmost part of the 64-bit word. */ 909 if (TARGET_BYTE_ORDER == BIG_ENDIAN) 910 m_arg->offset += MIPS_REGSIZE - len; 911 912 /* Create a fake argument to zero-fill the unsused part 913 of the 64-bit word. */ 914 ++m_arg; 915 m_arg->len = MIPS_REGSIZE - len; 916 m_arg->contents = zeroes; 917 if (TARGET_BYTE_ORDER == BIG_ENDIAN) 918 m_arg->offset = accumulate_size; 919 else 920 m_arg->offset = accumulate_size + len; 921 ++fake_args; 922 } 923 accumulate_size = ALIGN (accumulate_size + len, MIPS_REGSIZE); 924 } 925 } 926 } 927 accumulate_size = ALIGN (accumulate_size, 8); 928 if (accumulate_size < 4 * MIPS_REGSIZE) 929 accumulate_size = 4 * MIPS_REGSIZE; 930 sp -= accumulate_size; 931 for (i = nargs + fake_args; m_arg--, --i >= 0; ) 932 write_memory(sp + m_arg->offset, m_arg->contents, m_arg->len); 933 if (struct_return) 934 { 935 char buf[TARGET_PTR_BIT / HOST_CHAR_BIT]; 936 937 store_address (buf, sizeof buf, struct_addr); 938 write_memory (sp, buf, sizeof buf); 939 } 940 return sp; 941 } 942 943 void 944 mips_push_register(CORE_ADDR *sp, int regno) 945 { 946 char buffer[MAX_REGISTER_RAW_SIZE]; 947 int regsize = REGISTER_RAW_SIZE (regno); 948 949 *sp -= regsize; 950 read_register_gen (regno, buffer); 951 write_memory (*sp, buffer, regsize); 952 } 953 954 /* MASK(i,j) == (1<<i) + (1<<(i+1)) + ... + (1<<j)). Assume i<=j<(MIPS_NUMREGS-1). */ 955 #define MASK(i,j) (((1 << ((j)+1))-1) ^ ((1 << (i))-1)) 956 957 void 958 mips_push_dummy_frame() 959 { 960 int ireg; 961 struct linked_proc_info *link = (struct linked_proc_info*) 962 xmalloc(sizeof(struct linked_proc_info)); 963 mips_extra_func_info_t proc_desc = &link->info; 964 CORE_ADDR sp = read_register (SP_REGNUM); 965 CORE_ADDR old_sp = sp; 966 link->next = linked_proc_desc_table; 967 linked_proc_desc_table = link; 968 969 /* FIXME! are these correct ? */ 970 #define PUSH_FP_REGNUM 16 /* must be a register preserved across calls */ 971 #define GEN_REG_SAVE_MASK MASK(1,16)|MASK(24,28)|(1<<(MIPS_NUMREGS-1)) 972 #define GEN_REG_SAVE_COUNT 22 973 #define FLOAT_REG_SAVE_MASK MASK(0,19) 974 #define FLOAT_REG_SAVE_COUNT 20 975 #define FLOAT_SINGLE_REG_SAVE_MASK \ 976 ((1<<18)|(1<<16)|(1<<14)|(1<<12)|(1<<10)|(1<<8)|(1<<6)|(1<<4)|(1<<2)|(1<<0)) 977 #define FLOAT_SINGLE_REG_SAVE_COUNT 10 978 #define SPECIAL_REG_SAVE_COUNT 4 979 /* 980 * The registers we must save are all those not preserved across 981 * procedure calls. Dest_Reg (see tm-mips.h) must also be saved. 982 * In addition, we must save the PC, PUSH_FP_REGNUM, MMLO/-HI 983 * and FP Control/Status registers. 984 * 985 * 986 * Dummy frame layout: 987 * (high memory) 988 * Saved PC 989 * Saved MMHI, MMLO, FPC_CSR 990 * Saved R31 991 * Saved R28 992 * ... 993 * Saved R1 994 * Saved D18 (i.e. F19, F18) 995 * ... 996 * Saved D0 (i.e. F1, F0) 997 * CALL_DUMMY (subroutine stub; see tm-mips.h) 998 * Parameter build area (not yet implemented) 999 * (low memory) 1000 */ 1001 1002 /* Save special registers (PC, MMHI, MMLO, FPC_CSR) */ 1003 write_register (PUSH_FP_REGNUM, sp); 1004 PROC_FRAME_REG(proc_desc) = PUSH_FP_REGNUM; 1005 PROC_FRAME_OFFSET(proc_desc) = 0; 1006 mips_push_register (&sp, PC_REGNUM); 1007 mips_push_register (&sp, HI_REGNUM); 1008 mips_push_register (&sp, LO_REGNUM); 1009 mips_push_register (&sp, mips_fpu == MIPS_FPU_NONE ? 0 : FCRCS_REGNUM); 1010 1011 /* Save general CPU registers */ 1012 PROC_REG_MASK(proc_desc) = GEN_REG_SAVE_MASK; 1013 PROC_REG_OFFSET(proc_desc) = sp - old_sp; /* offset of (Saved R31) from FP */ 1014 for (ireg = 32; --ireg >= 0; ) 1015 if (PROC_REG_MASK(proc_desc) & (1 << ireg)) 1016 mips_push_register (&sp, ireg); 1017 1018 /* Save floating point registers starting with high order word */ 1019 PROC_FREG_MASK(proc_desc) = 1020 mips_fpu == MIPS_FPU_DOUBLE ? FLOAT_REG_SAVE_MASK 1021 : mips_fpu == MIPS_FPU_SINGLE ? FLOAT_SINGLE_REG_SAVE_MASK : 0; 1022 PROC_FREG_OFFSET(proc_desc) = sp - old_sp; /* offset of (Saved D18) from FP */ 1023 for (ireg = 32; --ireg >= 0; ) 1024 if (PROC_FREG_MASK(proc_desc) & (1 << ireg)) 1025 mips_push_register (&sp, ireg + FP0_REGNUM); 1026 1027 /* Update the stack pointer. Set the procedure's starting and ending 1028 addresses to point to the place on the stack where we'll be writing the 1029 dummy code (in mips_push_arguments). */ 1030 write_register (SP_REGNUM, sp); 1031 PROC_LOW_ADDR(proc_desc) = sp - CALL_DUMMY_SIZE + CALL_DUMMY_START_OFFSET; 1032 PROC_HIGH_ADDR(proc_desc) = sp; 1033 SET_PROC_DESC_IS_DUMMY(proc_desc); 1034 PROC_PC_REG(proc_desc) = RA_REGNUM; 1035 } 1036 1037 void 1038 mips_pop_frame() 1039 { 1040 register int regnum; 1041 struct frame_info *frame = get_current_frame (); 1042 CORE_ADDR new_sp = FRAME_FP (frame); 1043 1044 mips_extra_func_info_t proc_desc = frame->proc_desc; 1045 1046 write_register (PC_REGNUM, FRAME_SAVED_PC(frame)); 1047 if (frame->saved_regs == NULL) 1048 mips_find_saved_regs (frame); 1049 if (proc_desc) 1050 { 1051 for (regnum = MIPS_NUMREGS; --regnum >= 0; ) 1052 if (PROC_REG_MASK(proc_desc) & (1 << regnum)) 1053 write_register (regnum, 1054 read_memory_integer (frame->saved_regs->regs[regnum], 1055 MIPS_REGSIZE)); 1056 for (regnum = MIPS_NUMREGS; --regnum >= 0; ) 1057 if (PROC_FREG_MASK(proc_desc) & (1 << regnum)) 1058 write_register (regnum + FP0_REGNUM, 1059 read_memory_integer (frame->saved_regs->regs[regnum + FP0_REGNUM], MIPS_REGSIZE)); 1060 } 1061 write_register (SP_REGNUM, new_sp); 1062 flush_cached_frames (); 1063 1064 if (proc_desc && PROC_DESC_IS_DUMMY(proc_desc)) 1065 { 1066 struct linked_proc_info *pi_ptr, *prev_ptr; 1067 1068 for (pi_ptr = linked_proc_desc_table, prev_ptr = NULL; 1069 pi_ptr != NULL; 1070 prev_ptr = pi_ptr, pi_ptr = pi_ptr->next) 1071 { 1072 if (&pi_ptr->info == proc_desc) 1073 break; 1074 } 1075 1076 if (pi_ptr == NULL) 1077 error ("Can't locate dummy extra frame info\n"); 1078 1079 if (prev_ptr != NULL) 1080 prev_ptr->next = pi_ptr->next; 1081 else 1082 linked_proc_desc_table = pi_ptr->next; 1083 1084 free (pi_ptr); 1085 1086 write_register (HI_REGNUM, 1087 read_memory_integer (new_sp - 2*MIPS_REGSIZE, MIPS_REGSIZE)); 1088 write_register (LO_REGNUM, 1089 read_memory_integer (new_sp - 3*MIPS_REGSIZE, MIPS_REGSIZE)); 1090 if (mips_fpu != MIPS_FPU_NONE) 1091 write_register (FCRCS_REGNUM, 1092 read_memory_integer (new_sp - 4*MIPS_REGSIZE, MIPS_REGSIZE)); 1093 } 1094 } 1095 1096 static void 1097 mips_print_register (regnum, all) 1098 int regnum, all; 1099 { 1100 char raw_buffer[MAX_REGISTER_RAW_SIZE]; 1101 1102 /* Get the data in raw format. */ 1103 if (read_relative_register_raw_bytes (regnum, raw_buffer)) 1104 { 1105 printf_filtered ("%s: [Invalid]", reg_names[regnum]); 1106 return; 1107 } 1108 1109 /* If an even floating pointer register, also print as double. */ 1110 if (regnum >= FP0_REGNUM && regnum < FP0_REGNUM+MIPS_NUMREGS 1111 && !((regnum-FP0_REGNUM) & 1)) 1112 { 1113 char dbuffer[MAX_REGISTER_RAW_SIZE]; 1114 1115 read_relative_register_raw_bytes (regnum, dbuffer); 1116 read_relative_register_raw_bytes (regnum+1, dbuffer+4); /* FIXME!! */ 1117 #ifdef REGISTER_CONVERT_TO_TYPE 1118 REGISTER_CONVERT_TO_TYPE(regnum, builtin_type_double, dbuffer); 1119 #endif 1120 printf_filtered ("(d%d: ", regnum-FP0_REGNUM); 1121 val_print (builtin_type_double, dbuffer, 0, 1122 gdb_stdout, 0, 1, 0, Val_pretty_default); 1123 printf_filtered ("); "); 1124 } 1125 fputs_filtered (reg_names[regnum], gdb_stdout); 1126 1127 /* The problem with printing numeric register names (r26, etc.) is that 1128 the user can't use them on input. Probably the best solution is to 1129 fix it so that either the numeric or the funky (a2, etc.) names 1130 are accepted on input. */ 1131 if (regnum < MIPS_NUMREGS) 1132 printf_filtered ("(r%d): ", regnum); 1133 else 1134 printf_filtered (": "); 1135 1136 /* If virtual format is floating, print it that way. */ 1137 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum)) == TYPE_CODE_FLT) 1138 val_print (REGISTER_VIRTUAL_TYPE (regnum), raw_buffer, 0, 1139 gdb_stdout, 0, 1, 0, Val_pretty_default); 1140 /* Else print as integer in hex. */ 1141 else 1142 print_scalar_formatted (raw_buffer, REGISTER_VIRTUAL_TYPE (regnum), 1143 'x', 0, gdb_stdout); 1144 } 1145 1146 /* Replacement for generic do_registers_info. */ 1147 1148 void 1149 mips_do_registers_info (regnum, fpregs) 1150 int regnum; 1151 int fpregs; 1152 { 1153 if (regnum != -1) 1154 { 1155 if (*(reg_names[regnum]) == '\0') 1156 error ("Not a valid register for the current processor type"); 1157 1158 mips_print_register (regnum, 0); 1159 printf_filtered ("\n"); 1160 } 1161 else 1162 { 1163 int did_newline = 0; 1164 1165 for (regnum = 0; regnum < NUM_REGS; ) 1166 { 1167 if (((!fpregs) && regnum >= FP0_REGNUM && regnum <= FCRIR_REGNUM) 1168 || *(reg_names[regnum]) == '\0') 1169 { 1170 regnum++; 1171 continue; 1172 } 1173 mips_print_register (regnum, 1); 1174 regnum++; 1175 printf_filtered ("; "); 1176 did_newline = 0; 1177 if ((regnum & 3) == 0) 1178 { 1179 printf_filtered ("\n"); 1180 did_newline = 1; 1181 } 1182 } 1183 if (!did_newline) 1184 printf_filtered ("\n"); 1185 } 1186 } 1187 1188 /* Return number of args passed to a frame. described by FIP. 1189 Can return -1, meaning no way to tell. */ 1190 1191 int 1192 mips_frame_num_args (frame) 1193 struct frame_info *frame; 1194 { 1195 #if 0 /* FIXME Use or lose this! */ 1196 struct chain_info_t *p; 1197 1198 p = mips_find_cached_frame (FRAME_FP (frame)); 1199 if (p->valid) 1200 return p->the_info.numargs; 1201 #endif 1202 return -1; 1203 } 1204 1205 /* Is this a branch with a delay slot? */ 1206 1207 static int is_delayed PARAMS ((unsigned long)); 1208 1209 static int 1210 is_delayed (insn) 1211 unsigned long insn; 1212 { 1213 int i; 1214 for (i = 0; i < NUMOPCODES; ++i) 1215 if (mips_opcodes[i].pinfo != INSN_MACRO 1216 && (insn & mips_opcodes[i].mask) == mips_opcodes[i].match) 1217 break; 1218 return (i < NUMOPCODES 1219 && (mips_opcodes[i].pinfo & (INSN_UNCOND_BRANCH_DELAY 1220 | INSN_COND_BRANCH_DELAY 1221 | INSN_COND_BRANCH_LIKELY))); 1222 } 1223 1224 int 1225 mips_step_skips_delay (pc) 1226 CORE_ADDR pc; 1227 { 1228 char buf[4]; /* FIXME!! */ 1229 1230 if (target_read_memory (pc, buf, 4) != 0) /* FIXME!! */ 1231 /* If error reading memory, guess that it is not a delayed branch. */ 1232 return 0; 1233 return is_delayed ((unsigned long)extract_unsigned_integer (buf, 4)); /* FIXME */ 1234 } 1235 1236 /* To skip prologues, I use this predicate. Returns either PC itself 1237 if the code at PC does not look like a function prologue; otherwise 1238 returns an address that (if we're lucky) follows the prologue. If 1239 LENIENT, then we must skip everything which is involved in setting 1240 up the frame (it's OK to skip more, just so long as we don't skip 1241 anything which might clobber the registers which are being saved. 1242 We must skip more in the case where part of the prologue is in the 1243 delay slot of a non-prologue instruction). */ 1244 1245 CORE_ADDR 1246 mips_skip_prologue (pc, lenient) 1247 CORE_ADDR pc; 1248 int lenient; 1249 { 1250 t_inst inst; 1251 unsigned offset; 1252 int seen_sp_adjust = 0; 1253 int load_immediate_bytes = 0; 1254 CORE_ADDR post_prologue_pc; 1255 1256 /* See if we can determine the end of the prologue via the symbol table. 1257 If so, then return either PC, or the PC after the prologue, whichever 1258 is greater. */ 1259 1260 post_prologue_pc = after_prologue (pc, NULL); 1261 1262 if (post_prologue_pc != 0) 1263 return max (pc, post_prologue_pc); 1264 1265 /* Can't determine prologue from the symbol table, need to examine 1266 instructions. */ 1267 1268 /* Skip the typical prologue instructions. These are the stack adjustment 1269 instruction and the instructions that save registers on the stack 1270 or in the gcc frame. */ 1271 for (offset = 0; offset < 100; offset += MIPS_INSTLEN) /* FIXME!! */ 1272 { 1273 char buf[MIPS_INSTLEN]; 1274 int status; 1275 1276 status = read_memory_nobpt (pc + offset, buf, MIPS_INSTLEN); 1277 if (status) 1278 memory_error (status, pc + offset); 1279 inst = (unsigned long)extract_unsigned_integer (buf, MIPS_INSTLEN); 1280 1281 #if 0 1282 if (lenient && is_delayed (inst)) 1283 continue; 1284 #endif 1285 1286 if ((inst & 0xffff0000) == 0x27bd0000) /* addiu $sp,$sp,offset */ 1287 seen_sp_adjust = 1; 1288 else if (inst == 0x03a1e823 || /* subu $sp,$sp,$at */ 1289 inst == 0x03a8e823) /* subu $sp,$sp,$t0 */ 1290 seen_sp_adjust = 1; 1291 else if ((inst & 0xFFE00000) == 0xAFA00000 && (inst & 0x001F0000)) 1292 continue; /* sw reg,n($sp) */ 1293 /* reg != $zero */ 1294 else if ((inst & 0xFFE00000) == 0xE7A00000) /* swc1 freg,n($sp) */ 1295 continue; 1296 else if ((inst & 0xF3E00000) == 0xA3C00000 && (inst & 0x001F0000)) 1297 /* sx reg,n($s8) */ 1298 continue; /* reg != $zero */ 1299 1300 /* move $s8,$sp. With different versions of gas this will be either 1301 `addu $s8,$sp,$zero' or `or $s8,$sp,$zero'. Accept either. */ 1302 else if (inst == 0x03A0F021 || inst == 0x03a0f025) 1303 continue; 1304 1305 else if ((inst & 0xFF9F07FF) == 0x00800021) /* move reg,$a0-$a3 */ 1306 continue; 1307 else if ((inst & 0xffff0000) == 0x3c1c0000) /* lui $gp,n */ 1308 continue; 1309 else if ((inst & 0xffff0000) == 0x279c0000) /* addiu $gp,$gp,n */ 1310 continue; 1311 else if (inst == 0x0399e021 /* addu $gp,$gp,$t9 */ 1312 || inst == 0x033ce021) /* addu $gp,$t9,$gp */ 1313 continue; 1314 /* The following instructions load $at or $t0 with an immediate 1315 value in preparation for a stack adjustment via 1316 subu $sp,$sp,[$at,$t0]. These instructions could also initialize 1317 a local variable, so we accept them only before a stack adjustment 1318 instruction was seen. */ 1319 else if (!seen_sp_adjust) 1320 { 1321 if ((inst & 0xffff0000) == 0x3c010000 || /* lui $at,n */ 1322 (inst & 0xffff0000) == 0x3c080000) /* lui $t0,n */ 1323 { 1324 load_immediate_bytes += MIPS_INSTLEN; /* FIXME!! */ 1325 continue; 1326 } 1327 else if ((inst & 0xffff0000) == 0x34210000 || /* ori $at,$at,n */ 1328 (inst & 0xffff0000) == 0x35080000 || /* ori $t0,$t0,n */ 1329 (inst & 0xffff0000) == 0x34010000 || /* ori $at,$zero,n */ 1330 (inst & 0xffff0000) == 0x34080000) /* ori $t0,$zero,n */ 1331 { 1332 load_immediate_bytes += MIPS_INSTLEN; /* FIXME!! */ 1333 continue; 1334 } 1335 else 1336 break; 1337 } 1338 else 1339 break; 1340 } 1341 1342 /* In a frameless function, we might have incorrectly 1343 skipped some load immediate instructions. Undo the skipping 1344 if the load immediate was not followed by a stack adjustment. */ 1345 if (load_immediate_bytes && !seen_sp_adjust) 1346 offset -= load_immediate_bytes; 1347 return pc + offset; 1348 } 1349 1350 #if 0 1351 /* The lenient prologue stuff should be superceded by the code in 1352 init_extra_frame_info which looks to see whether the stores mentioned 1353 in the proc_desc have actually taken place. */ 1354 1355 /* Is address PC in the prologue (loosely defined) for function at 1356 STARTADDR? */ 1357 1358 static int 1359 mips_in_lenient_prologue (startaddr, pc) 1360 CORE_ADDR startaddr; 1361 CORE_ADDR pc; 1362 { 1363 CORE_ADDR end_prologue = mips_skip_prologue (startaddr, 1); 1364 return pc >= startaddr && pc < end_prologue; 1365 } 1366 #endif 1367 1368 /* Given a return value in `regbuf' with a type `valtype', 1369 extract and copy its value into `valbuf'. */ 1370 void 1371 mips_extract_return_value (valtype, regbuf, valbuf) 1372 struct type *valtype; 1373 char regbuf[REGISTER_BYTES]; 1374 char *valbuf; 1375 { 1376 int regnum; 1377 int offset = 0; 1378 1379 regnum = 2; 1380 if (TYPE_CODE (valtype) == TYPE_CODE_FLT 1381 && (mips_fpu == MIPS_FPU_DOUBLE 1382 || (mips_fpu == MIPS_FPU_SINGLE && TYPE_LENGTH (valtype) <= 4))) /* FIXME!! */ 1383 regnum = FP0_REGNUM; 1384 1385 if (TARGET_BYTE_ORDER == BIG_ENDIAN 1386 && TYPE_CODE (valtype) != TYPE_CODE_FLT 1387 && TYPE_LENGTH (valtype) < REGISTER_RAW_SIZE (regnum)) 1388 offset = REGISTER_RAW_SIZE (regnum) - TYPE_LENGTH (valtype); 1389 1390 memcpy (valbuf, regbuf + REGISTER_BYTE (regnum) + offset, 1391 TYPE_LENGTH (valtype)); 1392 #ifdef REGISTER_CONVERT_TO_TYPE 1393 REGISTER_CONVERT_TO_TYPE(regnum, valtype, valbuf); 1394 #endif 1395 } 1396 1397 /* Given a return value in `regbuf' with a type `valtype', 1398 write it's value into the appropriate register. */ 1399 void 1400 mips_store_return_value (valtype, valbuf) 1401 struct type *valtype; 1402 char *valbuf; 1403 { 1404 int regnum; 1405 char raw_buffer[MAX_REGISTER_RAW_SIZE]; 1406 1407 regnum = 2; 1408 if (TYPE_CODE (valtype) == TYPE_CODE_FLT 1409 && (mips_fpu == MIPS_FPU_DOUBLE 1410 || (mips_fpu == MIPS_FPU_SINGLE && TYPE_LENGTH (valtype) <= 4))) /* FIXME!! */ 1411 regnum = FP0_REGNUM; 1412 1413 memcpy(raw_buffer, valbuf, TYPE_LENGTH (valtype)); 1414 1415 #ifdef REGISTER_CONVERT_FROM_TYPE 1416 REGISTER_CONVERT_FROM_TYPE(regnum, valtype, raw_buffer); 1417 #endif 1418 1419 write_register_bytes(REGISTER_BYTE (regnum), raw_buffer, TYPE_LENGTH (valtype)); 1420 } 1421 1422 /* Exported procedure: Is PC in the signal trampoline code */ 1423 1424 int 1425 in_sigtramp (pc, ignore) 1426 CORE_ADDR pc; 1427 char *ignore; /* function name */ 1428 { 1429 if (sigtramp_address == 0) 1430 fixup_sigtramp (); 1431 return (pc >= sigtramp_address && pc < sigtramp_end); 1432 } 1433 1434 /* Command to set FPU type. mips_fpu_string will have been set to the 1435 user's argument. Set mips_fpu based on mips_fpu_string, and then 1436 canonicalize mips_fpu_string. */ 1437 1438 /*ARGSUSED*/ 1439 static void 1440 mips_set_fpu_command (args, from_tty, c) 1441 char *args; 1442 int from_tty; 1443 struct cmd_list_element *c; 1444 { 1445 char *err = NULL; 1446 1447 if (mips_fpu_string == NULL || *mips_fpu_string == '\0') 1448 mips_fpu = MIPS_FPU_DOUBLE; 1449 else if (strcasecmp (mips_fpu_string, "double") == 0 1450 || strcasecmp (mips_fpu_string, "on") == 0 1451 || strcasecmp (mips_fpu_string, "1") == 0 1452 || strcasecmp (mips_fpu_string, "yes") == 0) 1453 mips_fpu = MIPS_FPU_DOUBLE; 1454 else if (strcasecmp (mips_fpu_string, "none") == 0 1455 || strcasecmp (mips_fpu_string, "off") == 0 1456 || strcasecmp (mips_fpu_string, "0") == 0 1457 || strcasecmp (mips_fpu_string, "no") == 0) 1458 mips_fpu = MIPS_FPU_NONE; 1459 else if (strcasecmp (mips_fpu_string, "single") == 0) 1460 mips_fpu = MIPS_FPU_SINGLE; 1461 else 1462 err = strsave (mips_fpu_string); 1463 1464 if (mips_fpu_string != NULL) 1465 free (mips_fpu_string); 1466 1467 switch (mips_fpu) 1468 { 1469 case MIPS_FPU_DOUBLE: 1470 mips_fpu_string = strsave ("double"); 1471 break; 1472 case MIPS_FPU_SINGLE: 1473 mips_fpu_string = strsave ("single"); 1474 break; 1475 case MIPS_FPU_NONE: 1476 mips_fpu_string = strsave ("none"); 1477 break; 1478 } 1479 1480 if (err != NULL) 1481 { 1482 struct cleanup *cleanups = make_cleanup (free, err); 1483 error ("Unknown FPU type `%s'. Use `double', `none', or `single'.", 1484 err); 1485 do_cleanups (cleanups); 1486 } 1487 } 1488 1489 static void 1490 mips_show_fpu_command (args, from_tty, c) 1491 char *args; 1492 int from_tty; 1493 struct cmd_list_element *c; 1494 { 1495 } 1496 1497 /* Command to set the processor type. */ 1498 1499 void 1500 mips_set_processor_type_command (args, from_tty) 1501 char *args; 1502 int from_tty; 1503 { 1504 int i; 1505 1506 if (tmp_mips_processor_type == NULL || *tmp_mips_processor_type == '\0') 1507 { 1508 printf_unfiltered ("The known MIPS processor types are as follows:\n\n"); 1509 for (i = 0; mips_processor_type_table[i].name != NULL; ++i) 1510 printf_unfiltered ("%s\n", mips_processor_type_table[i].name); 1511 1512 /* Restore the value. */ 1513 tmp_mips_processor_type = strsave (mips_processor_type); 1514 1515 return; 1516 } 1517 1518 if (!mips_set_processor_type (tmp_mips_processor_type)) 1519 { 1520 error ("Unknown processor type `%s'.", tmp_mips_processor_type); 1521 /* Restore its value. */ 1522 tmp_mips_processor_type = strsave (mips_processor_type); 1523 } 1524 } 1525 1526 static void 1527 mips_show_processor_type_command (args, from_tty) 1528 char *args; 1529 int from_tty; 1530 { 1531 } 1532 1533 /* Modify the actual processor type. */ 1534 1535 int 1536 mips_set_processor_type (str) 1537 char *str; 1538 { 1539 int i, j; 1540 1541 if (str == NULL) 1542 return 0; 1543 1544 for (i = 0; mips_processor_type_table[i].name != NULL; ++i) 1545 { 1546 if (strcasecmp (str, mips_processor_type_table[i].name) == 0) 1547 { 1548 mips_processor_type = str; 1549 1550 for (j = 0; j < NUM_REGS; ++j) 1551 reg_names[j] = mips_processor_type_table[i].regnames[j]; 1552 1553 return 1; 1554 1555 /* FIXME tweak fpu flag too */ 1556 } 1557 } 1558 1559 return 0; 1560 } 1561 1562 /* Attempt to identify the particular processor model by reading the 1563 processor id. */ 1564 1565 char * 1566 mips_read_processor_type () 1567 { 1568 CORE_ADDR prid; 1569 1570 prid = read_register (PRID_REGNUM); 1571 1572 if ((prid & ~0xf) == 0x700) 1573 return savestring ("r3041", strlen("r3041")); 1574 1575 return NULL; 1576 } 1577 1578 /* Just like reinit_frame_cache, but with the right arguments to be 1579 callable as an sfunc. */ 1580 1581 static void 1582 reinit_frame_cache_sfunc (args, from_tty, c) 1583 char *args; 1584 int from_tty; 1585 struct cmd_list_element *c; 1586 { 1587 reinit_frame_cache (); 1588 } 1589 1590 static int 1591 gdb_print_insn_mips (memaddr, info) 1592 bfd_vma memaddr; 1593 disassemble_info *info; 1594 { 1595 if (TARGET_BYTE_ORDER == BIG_ENDIAN) 1596 return print_insn_big_mips (memaddr, info); 1597 else 1598 return print_insn_little_mips (memaddr, info); 1599 } 1600 1601 void 1602 _initialize_mips_tdep () 1603 { 1604 struct cmd_list_element *c; 1605 1606 tm_print_insn = gdb_print_insn_mips; 1607 1608 /* Let the user turn off floating point and set the fence post for 1609 heuristic_proc_start. */ 1610 1611 c = add_set_cmd ("mipsfpu", class_support, var_string_noescape, 1612 (char *) &mips_fpu_string, 1613 "Set use of floating point coprocessor.\n\ 1614 Set to `none' to avoid using floating point instructions when calling\n\ 1615 functions or dealing with return values. Set to `single' to use only\n\ 1616 single precision floating point as on the R4650. Set to `double' for\n\ 1617 normal floating point support.", 1618 &setlist); 1619 c->function.sfunc = mips_set_fpu_command; 1620 c = add_show_from_set (c, &showlist); 1621 c->function.sfunc = mips_show_fpu_command; 1622 1623 mips_fpu = MIPS_FPU_DOUBLE; 1624 mips_fpu_string = strsave ("double"); 1625 1626 c = add_set_cmd ("processor", class_support, var_string_noescape, 1627 (char *) &tmp_mips_processor_type, 1628 "Set the type of MIPS processor in use.\n\ 1629 Set this to be able to access processor-type-specific registers.\n\ 1630 ", 1631 &setlist); 1632 c->function.cfunc = mips_set_processor_type_command; 1633 c = add_show_from_set (c, &showlist); 1634 c->function.cfunc = mips_show_processor_type_command; 1635 1636 tmp_mips_processor_type = strsave (DEFAULT_MIPS_TYPE); 1637 mips_set_processor_type_command (strsave (DEFAULT_MIPS_TYPE), 0); 1638 1639 /* We really would like to have both "0" and "unlimited" work, but 1640 command.c doesn't deal with that. So make it a var_zinteger 1641 because the user can always use "999999" or some such for unlimited. */ 1642 c = add_set_cmd ("heuristic-fence-post", class_support, var_zinteger, 1643 (char *) &heuristic_fence_post, 1644 "\ 1645 Set the distance searched for the start of a function.\n\ 1646 If you are debugging a stripped executable, GDB needs to search through the\n\ 1647 program for the start of a function. This command sets the distance of the\n\ 1648 search. The only need to set it is when debugging a stripped executable.", 1649 &setlist); 1650 /* We need to throw away the frame cache when we set this, since it 1651 might change our ability to get backtraces. */ 1652 c->function.sfunc = reinit_frame_cache_sfunc; 1653 add_show_from_set (c, &showlist); 1654 } 1655