1 /* Definitions to make GDB run on a mips box under 4.3bsd. 2 Copyright 1986, 1987, 1989, 1991, 1992, 1993, 1994, 1995 3 Free Software Foundation, Inc. 4 Contributed by Per Bothner (bothner@cs.wisc.edu) at U.Wisconsin 5 and by Alessandro Forin (af@cs.cmu.edu) at CMU.. 6 7 This file is part of GDB. 8 9 This program is free software; you can redistribute it and/or modify 10 it under the terms of the GNU General Public License as published by 11 the Free Software Foundation; either version 2 of the License, or 12 (at your option) any later version. 13 14 This program is distributed in the hope that it will be useful, 15 but WITHOUT ANY WARRANTY; without even the implied warranty of 16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 GNU General Public License for more details. 18 19 You should have received a copy of the GNU General Public License 20 along with this program; if not, write to the Free Software 21 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ 22 23 #ifndef TM_MIPS_H 24 #define TM_MIPS_H 1 25 26 #ifdef __STDC__ 27 struct frame_info; 28 struct symbol; 29 struct type; 30 struct value; 31 #endif 32 33 #include <bfd.h> 34 #include "coff/sym.h" /* Needed for PDR below. */ 35 #include "coff/symconst.h" 36 37 #if !defined (TARGET_BYTE_ORDER) 38 #define TARGET_BYTE_ORDER LITTLE_ENDIAN 39 #endif 40 41 #if !defined (GDB_TARGET_IS_MIPS64) 42 #define GDB_TARGET_IS_MIPS64 0 43 #endif 44 45 #if !defined (TARGET_MONITOR_PROMPT) 46 #define TARGET_MONITOR_PROMPT "<IDT>" 47 #endif 48 49 /* Floating point is IEEE compliant */ 50 #define IEEE_FLOAT 51 52 /* Some MIPS boards are provided both with and without a floating 53 point coprocessor. The MIPS R4650 chip has only single precision 54 floating point. We provide a user settable variable to tell gdb 55 what type of floating point to use. */ 56 57 enum mips_fpu_type 58 { 59 MIPS_FPU_DOUBLE, /* Full double precision floating point. */ 60 MIPS_FPU_SINGLE, /* Single precision floating point (R4650). */ 61 MIPS_FPU_NONE /* No floating point. */ 62 }; 63 64 extern enum mips_fpu_type mips_fpu; 65 66 /* The name of the usual type of MIPS processor that is in the target 67 system. */ 68 69 #define DEFAULT_MIPS_TYPE "generic" 70 71 /* Offset from address of function to start of its code. 72 Zero on most machines. */ 73 74 #define FUNCTION_START_OFFSET 0 75 76 /* Advance PC across any function entry prologue instructions 77 to reach some "real" code. */ 78 79 #define SKIP_PROLOGUE(pc) pc = mips_skip_prologue (pc, 0) 80 extern CORE_ADDR mips_skip_prologue PARAMS ((CORE_ADDR addr, int lenient)); 81 82 /* Return non-zero if PC points to an instruction which will cause a step 83 to execute both the instruction at PC and an instruction at PC+4. */ 84 #define STEP_SKIPS_DELAY(pc) (mips_step_skips_delay (pc)) 85 extern int mips_step_skips_delay PARAMS ((CORE_ADDR)); 86 87 /* Immediately after a function call, return the saved pc. 88 Can't always go through the frames for this because on some machines 89 the new frame is not set up until the new function executes 90 some instructions. */ 91 92 #define SAVED_PC_AFTER_CALL(frame) read_register(RA_REGNUM) 93 94 /* Are we currently handling a signal */ 95 96 extern int in_sigtramp PARAMS ((CORE_ADDR, char *)); 97 #define IN_SIGTRAMP(pc, name) in_sigtramp(pc, name) 98 99 /* Stack grows downward. */ 100 101 #define INNER_THAN < 102 103 #define BIG_ENDIAN 4321 104 #if TARGET_BYTE_ORDER == BIG_ENDIAN 105 #define BREAKPOINT {0, 0x5, 0, 0xd} 106 #else 107 #define BREAKPOINT {0xd, 0, 0x5, 0} 108 #endif 109 110 /* Amount PC must be decremented by after a breakpoint. 111 This is often the number of bytes in BREAKPOINT 112 but not always. */ 113 114 #define DECR_PC_AFTER_BREAK 0 115 116 /* Nonzero if instruction at PC is a return instruction. "j ra" on mips. */ 117 118 #define ABOUT_TO_RETURN(pc) (read_memory_integer (pc, 4) == 0x3e00008) 119 120 /* Say how long (ordinary) registers are. This is a piece of bogosity 121 used in push_word and a few other places; REGISTER_RAW_SIZE is the 122 real way to know how big a register is. */ 123 124 #define REGISTER_SIZE 4 125 126 /* The size of a register. This is predefined in tm-mips64.h. We 127 can't use REGISTER_SIZE because that is used for various other 128 things. */ 129 130 #ifndef MIPS_REGSIZE 131 #define MIPS_REGSIZE 4 132 #endif 133 134 /* Number of machine registers */ 135 136 #define NUM_REGS 90 137 138 /* Initializer for an array of names of registers. 139 There should be NUM_REGS strings in this initializer. */ 140 141 #define REGISTER_NAMES \ 142 { "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", \ 143 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", \ 144 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", \ 145 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", \ 146 "sr", "lo", "hi", "bad", "cause","pc", \ 147 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", \ 148 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", \ 149 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",\ 150 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",\ 151 "fsr", "fir", "fp", "", \ 152 "", "", "", "", "", "", "", "", \ 153 "", "", "", "", "", "", "", "", \ 154 } 155 156 /* Register numbers of various important registers. 157 Note that some of these values are "real" register numbers, 158 and correspond to the general registers of the machine, 159 and some are "phony" register numbers which are too large 160 to be actual register numbers as far as the user is concerned 161 but do serve to get the desired values when passed to read_register. */ 162 163 #define ZERO_REGNUM 0 /* read-only register, always 0 */ 164 #define V0_REGNUM 2 /* Function integer return value */ 165 #define A0_REGNUM 4 /* Loc of first arg during a subr call */ 166 #define SP_REGNUM 29 /* Contains address of top of stack */ 167 #define RA_REGNUM 31 /* Contains return address value */ 168 #define PS_REGNUM 32 /* Contains processor status */ 169 #define HI_REGNUM 34 /* Multiple/divide temp */ 170 #define LO_REGNUM 33 /* ... */ 171 #define BADVADDR_REGNUM 35 /* bad vaddr for addressing exception */ 172 #define CAUSE_REGNUM 36 /* describes last exception */ 173 #define PC_REGNUM 37 /* Contains program counter */ 174 #define FP0_REGNUM 38 /* Floating point register 0 (single float) */ 175 #define FCRCS_REGNUM 70 /* FP control/status */ 176 #define FCRIR_REGNUM 71 /* FP implementation/revision */ 177 #define FP_REGNUM 72 /* Pseudo register that contains true address of executing stack frame */ 178 #define UNUSED_REGNUM 73 /* Never used, FIXME */ 179 #define FIRST_EMBED_REGNUM 74 /* First CP0 register for embedded use */ 180 #define PRID_REGNUM 89 /* Processor ID */ 181 #define LAST_EMBED_REGNUM 89 /* Last one */ 182 183 /* Define DO_REGISTERS_INFO() to do machine-specific formatting 184 of register dumps. */ 185 186 #define DO_REGISTERS_INFO(_regnum, fp) mips_do_registers_info(_regnum, fp) 187 extern void mips_do_registers_info PARAMS ((int, int)); 188 189 /* Total amount of space needed to store our copies of the machine's 190 register state, the array `registers'. */ 191 192 #define REGISTER_BYTES (NUM_REGS*MIPS_REGSIZE) 193 194 /* Index within `registers' of the first byte of the space for 195 register N. */ 196 197 #define REGISTER_BYTE(N) ((N) * MIPS_REGSIZE) 198 199 /* Number of bytes of storage in the actual machine representation 200 for register N. On mips, all regs are the same size. */ 201 202 #define REGISTER_RAW_SIZE(N) MIPS_REGSIZE 203 204 /* Number of bytes of storage in the program's representation 205 for register N. On mips, all regs are the same size. */ 206 207 #define REGISTER_VIRTUAL_SIZE(N) MIPS_REGSIZE 208 209 /* Largest value REGISTER_RAW_SIZE can have. */ 210 211 #define MAX_REGISTER_RAW_SIZE 8 212 213 /* Largest value REGISTER_VIRTUAL_SIZE can have. */ 214 215 #define MAX_REGISTER_VIRTUAL_SIZE 8 216 217 /* Return the GDB type object for the "standard" data type 218 of data in register N. */ 219 220 #ifndef REGISTER_VIRTUAL_TYPE 221 #define REGISTER_VIRTUAL_TYPE(N) \ 222 (((N) >= FP0_REGNUM && (N) < FP0_REGNUM+32) \ 223 ? builtin_type_float : builtin_type_int) 224 #endif 225 226 #if HOST_BYTE_ORDER == BIG_ENDIAN 227 /* All mips targets store doubles in a register pair with the least 228 significant register in the lower numbered register. 229 If the host is big endian, double register values need conversion between 230 memory and register formats. */ 231 232 #define REGISTER_CONVERT_TO_TYPE(n, type, buffer) \ 233 do {if ((n) >= FP0_REGNUM && (n) < FP0_REGNUM + 32 && \ 234 TYPE_CODE(type) == TYPE_CODE_FLT && TYPE_LENGTH(type) == 8) { \ 235 char __temp[4]; \ 236 memcpy (__temp, ((char *)(buffer))+4, 4); \ 237 memcpy (((char *)(buffer))+4, (buffer), 4); \ 238 memcpy (((char *)(buffer)), __temp, 4); }} while (0) 239 240 #define REGISTER_CONVERT_FROM_TYPE(n, type, buffer) \ 241 do {if ((n) >= FP0_REGNUM && (n) < FP0_REGNUM + 32 && \ 242 TYPE_CODE(type) == TYPE_CODE_FLT && TYPE_LENGTH(type) == 8) { \ 243 char __temp[4]; \ 244 memcpy (__temp, ((char *)(buffer))+4, 4); \ 245 memcpy (((char *)(buffer))+4, (buffer), 4); \ 246 memcpy (((char *)(buffer)), __temp, 4); }} while (0) 247 #endif 248 249 /* Store the address of the place in which to copy the structure the 250 subroutine will return. Handled by mips_push_arguments. */ 251 252 #define STORE_STRUCT_RETURN(addr, sp) /**/ 253 254 /* Extract from an array REGBUF containing the (raw) register state 255 a function return value of type TYPE, and copy that, in virtual format, 256 into VALBUF. XXX floats */ 257 258 #define EXTRACT_RETURN_VALUE(TYPE,REGBUF,VALBUF) \ 259 mips_extract_return_value(TYPE, REGBUF, VALBUF) 260 extern void 261 mips_extract_return_value PARAMS ((struct type *, char [], char *)); 262 263 /* Write into appropriate registers a function return value 264 of type TYPE, given in virtual format. */ 265 266 #define STORE_RETURN_VALUE(TYPE,VALBUF) \ 267 mips_store_return_value(TYPE, VALBUF) 268 extern void mips_store_return_value PARAMS ((struct type *, char *)); 269 270 /* Extract from an array REGBUF containing the (raw) register state 271 the address in which a function should return its structure value, 272 as a CORE_ADDR (or an expression that can be used as one). */ 273 /* The address is passed in a0 upon entry to the function, but when 274 the function exits, the compiler has copied the value to v0. This 275 convention is specified by the System V ABI, so I think we can rely 276 on it. */ 277 278 #define EXTRACT_STRUCT_VALUE_ADDRESS(REGBUF) \ 279 (extract_address (REGBUF + REGISTER_BYTE (V0_REGNUM), \ 280 REGISTER_RAW_SIZE (V0_REGNUM))) 281 282 /* Structures are returned by ref in extra arg0 */ 283 #define USE_STRUCT_CONVENTION(gcc_p, type) 1 284 285 286 /* Describe the pointer in each stack frame to the previous stack frame 287 (its caller). */ 288 289 /* FRAME_CHAIN takes a frame's nominal address 290 and produces the frame's chain-pointer. */ 291 292 #define FRAME_CHAIN(thisframe) (CORE_ADDR) mips_frame_chain (thisframe) 293 extern CORE_ADDR mips_frame_chain PARAMS ((struct frame_info *)); 294 295 /* Define other aspects of the stack frame. */ 296 297 298 /* A macro that tells us whether the function invocation represented 299 by FI does not have a frame on the stack associated with it. If it 300 does not, FRAMELESS is set to 1, else 0. */ 301 /* We handle this differently for mips, and maybe we should not */ 302 303 #define FRAMELESS_FUNCTION_INVOCATION(FI, FRAMELESS) {(FRAMELESS) = 0;} 304 305 /* Saved Pc. */ 306 307 #define FRAME_SAVED_PC(FRAME) (mips_frame_saved_pc(FRAME)) 308 extern CORE_ADDR mips_frame_saved_pc PARAMS ((struct frame_info *)); 309 310 #define FRAME_ARGS_ADDRESS(fi) (fi)->frame 311 312 #define FRAME_LOCALS_ADDRESS(fi) (fi)->frame 313 314 /* Return number of args passed to a frame. 315 Can return -1, meaning no way to tell. */ 316 317 #define FRAME_NUM_ARGS(num, fi) (num = mips_frame_num_args(fi)) 318 extern int mips_frame_num_args PARAMS ((struct frame_info *)); 319 320 /* Return number of bytes at start of arglist that are not really args. */ 321 322 #define FRAME_ARGS_SKIP 0 323 324 /* Put here the code to store, into a struct frame_saved_regs, 325 the addresses of the saved registers of frame described by FRAME_INFO. 326 This includes special registers such as pc and fp saved in special 327 ways in the stack frame. sp is even more special: 328 the address we return for it IS the sp for the next frame. */ 329 330 #define FRAME_FIND_SAVED_REGS(frame_info, frame_saved_regs) \ 331 do { \ 332 if ((frame_info)->saved_regs == NULL) \ 333 mips_find_saved_regs (frame_info); \ 334 (frame_saved_regs) = *(frame_info)->saved_regs; \ 335 (frame_saved_regs).regs[SP_REGNUM] = (frame_info)->frame; \ 336 } while (0) 337 extern void mips_find_saved_regs PARAMS ((struct frame_info *)); 338 339 340 /* Things needed for making the inferior call functions. */ 341 342 /* Stack must be aligned on 32-bit boundaries when synthesizing 343 function calls. We don't need STACK_ALIGN, PUSH_ARGUMENTS will 344 handle it. */ 345 346 #define PUSH_ARGUMENTS(nargs, args, sp, struct_return, struct_addr) \ 347 sp = mips_push_arguments((nargs), (args), (sp), (struct_return), (struct_addr)) 348 extern CORE_ADDR 349 mips_push_arguments PARAMS ((int, struct value **, CORE_ADDR, int, CORE_ADDR)); 350 351 /* Push an empty stack frame, to record the current PC, etc. */ 352 353 #define PUSH_DUMMY_FRAME mips_push_dummy_frame() 354 extern void mips_push_dummy_frame PARAMS ((void)); 355 356 /* Discard from the stack the innermost frame, restoring all registers. */ 357 358 #define POP_FRAME mips_pop_frame() 359 extern void mips_pop_frame PARAMS ((void)); 360 361 #define MK_OP(op,rs,rt,offset) (((op)<<26)|((rs)<<21)|((rt)<<16)|(offset)) 362 #ifndef OP_LDFPR 363 #define OP_LDFPR 061 /* lwc1 */ 364 #endif 365 #ifndef OP_LDGPR 366 #define OP_LDGPR 043 /* lw */ 367 #endif 368 #define CALL_DUMMY_SIZE (16*4) 369 #define Dest_Reg 2 370 #define CALL_DUMMY {\ 371 MK_OP(0,RA_REGNUM,0,8), /* jr $ra # Fake ABOUT_TO_RETURN ...*/\ 372 0, /* nop # ... to stop raw backtrace*/\ 373 0x27bd0000, /* addu sp,?0 # Pseudo prologue */\ 374 /* Start here; reload FP regs, then GP regs: */\ 375 MK_OP(OP_LDFPR,SP_REGNUM,12,0 ), /* l[wd]c1 $f12,0(sp) */\ 376 MK_OP(OP_LDFPR,SP_REGNUM,13, MIPS_REGSIZE), /* l[wd]c1 $f13,{4,8}(sp) */\ 377 MK_OP(OP_LDFPR,SP_REGNUM,14,2*MIPS_REGSIZE), /* l[wd]c1 $f14,{8,16}(sp) */\ 378 MK_OP(OP_LDFPR,SP_REGNUM,15,3*MIPS_REGSIZE), /* l[wd]c1 $f15,{12,24}(sp) */\ 379 MK_OP(OP_LDGPR,SP_REGNUM, 4,0 ), /* l[wd] $r4,0(sp) */\ 380 MK_OP(OP_LDGPR,SP_REGNUM, 5, MIPS_REGSIZE), /* l[wd] $r5,{4,8}(sp) */\ 381 MK_OP(OP_LDGPR,SP_REGNUM, 6,2*MIPS_REGSIZE), /* l[wd] $r6,{8,16}(sp) */\ 382 MK_OP(OP_LDGPR,SP_REGNUM, 7,3*MIPS_REGSIZE), /* l[wd] $r7,{12,24}(sp) */\ 383 (017<<26)| (Dest_Reg << 16), /* lui $r31,<target upper 16 bits>*/\ 384 MK_OP(13,Dest_Reg,Dest_Reg,0), /* ori $r31,$r31,<lower 16 bits>*/ \ 385 (Dest_Reg<<21) | (31<<11) | 9, /* jalr $r31 */\ 386 MK_OP(OP_LDGPR,SP_REGNUM, 7,3*MIPS_REGSIZE), /* l[wd] $r7,{12,24}(sp) */\ 387 0x5000d, /* bpt */\ 388 } 389 390 #define CALL_DUMMY_START_OFFSET 12 391 392 #define CALL_DUMMY_BREAKPOINT_OFFSET (CALL_DUMMY_START_OFFSET + (12 * 4)) 393 394 /* Insert the specified number of args and function address 395 into a call sequence of the above form stored at DUMMYNAME. */ 396 397 /* For big endian mips machines we need to switch the order of the 398 words with a floating-point value (it was already coerced to a double 399 by mips_push_arguments). */ 400 #define FIX_CALL_DUMMY(dummyname, start_sp, fun, nargs, args, rettype, gcc_p) \ 401 do \ 402 { \ 403 store_unsigned_integer \ 404 (dummyname + 11 * 4, 4, \ 405 (extract_unsigned_integer (dummyname + 11 * 4, 4) \ 406 | (((fun) >> 16) & 0xffff))); \ 407 store_unsigned_integer \ 408 (dummyname + 12 * 4, 4, \ 409 (extract_unsigned_integer (dummyname + 12 * 4, 4) \ 410 | ((fun) & 0xffff))); \ 411 if (mips_fpu == MIPS_FPU_NONE) \ 412 { \ 413 store_unsigned_integer (dummyname + 3 * 4, 4, \ 414 (unsigned LONGEST) 0); \ 415 store_unsigned_integer (dummyname + 4 * 4, 4, \ 416 (unsigned LONGEST) 0); \ 417 store_unsigned_integer (dummyname + 5 * 4, 4, \ 418 (unsigned LONGEST) 0); \ 419 store_unsigned_integer (dummyname + 6 * 4, 4, \ 420 (unsigned LONGEST) 0); \ 421 } \ 422 else if (mips_fpu == MIPS_FPU_SINGLE) \ 423 { \ 424 /* This isn't right. mips_push_arguments will call \ 425 value_arg_coerce, which will convert all float arguments \ 426 to doubles. If the function prototype is float, though, \ 427 it will be expecting a float argument in a float \ 428 register. */ \ 429 store_unsigned_integer (dummyname + 4 * 4, 4, \ 430 (unsigned LONGEST) 0); \ 431 store_unsigned_integer (dummyname + 6 * 4, 4, \ 432 (unsigned LONGEST) 0); \ 433 } \ 434 else if (TARGET_BYTE_ORDER == BIG_ENDIAN \ 435 && ! GDB_TARGET_IS_MIPS64) \ 436 { \ 437 if (nargs > 0 \ 438 && TYPE_CODE (VALUE_TYPE (args[0])) == TYPE_CODE_FLT) \ 439 { \ 440 if (TYPE_LENGTH (VALUE_TYPE (args[0])) > 8) \ 441 error ("floating point value too large to pass to function");\ 442 store_unsigned_integer \ 443 (dummyname + 3 * 4, 4, MK_OP (OP_LDFPR, SP_REGNUM, 12, 4));\ 444 store_unsigned_integer \ 445 (dummyname + 4 * 4, 4, MK_OP (OP_LDFPR, SP_REGNUM, 13, 0));\ 446 } \ 447 if (nargs > 1 \ 448 && TYPE_CODE (VALUE_TYPE (args[1])) == TYPE_CODE_FLT) \ 449 { \ 450 if (TYPE_LENGTH (VALUE_TYPE (args[1])) > 8) \ 451 error ("floating point value too large to pass to function");\ 452 store_unsigned_integer \ 453 (dummyname + 5 * 4, 4, MK_OP (OP_LDFPR, SP_REGNUM, 14, 12));\ 454 store_unsigned_integer \ 455 (dummyname + 6 * 4, 4, MK_OP (OP_LDFPR, SP_REGNUM, 15, 8));\ 456 } \ 457 } \ 458 } \ 459 while (0) 460 461 /* There's a mess in stack frame creation. See comments in blockframe.c 462 near reference to INIT_FRAME_PC_FIRST. */ 463 464 #define INIT_FRAME_PC(fromleaf, prev) /* nada */ 465 466 #define INIT_FRAME_PC_FIRST(fromleaf, prev) \ 467 (prev)->pc = ((fromleaf) ? SAVED_PC_AFTER_CALL ((prev)->next) : \ 468 (prev)->next ? FRAME_SAVED_PC ((prev)->next) : read_pc ()); 469 470 /* Special symbol found in blocks associated with routines. We can hang 471 mips_extra_func_info_t's off of this. */ 472 473 #define MIPS_EFI_SYMBOL_NAME "__GDB_EFI_INFO__" 474 extern void ecoff_relocate_efi PARAMS ((struct symbol *, CORE_ADDR)); 475 476 /* Specific information about a procedure. 477 This overlays the MIPS's PDR records, 478 mipsread.c (ab)uses this to save memory */ 479 480 typedef struct mips_extra_func_info { 481 long numargs; /* number of args to procedure (was iopt) */ 482 bfd_vma high_addr; /* upper address bound */ 483 PDR pdr; /* Procedure descriptor record */ 484 } *mips_extra_func_info_t; 485 486 #define EXTRA_FRAME_INFO \ 487 mips_extra_func_info_t proc_desc; \ 488 int num_args;\ 489 struct frame_saved_regs *saved_regs; 490 491 #define INIT_EXTRA_FRAME_INFO(fromleaf, fci) init_extra_frame_info(fci) 492 extern void init_extra_frame_info PARAMS ((struct frame_info *)); 493 494 #define PRINT_EXTRA_FRAME_INFO(fi) \ 495 { \ 496 if (fi && fi->proc_desc && fi->proc_desc->pdr.framereg < NUM_REGS) \ 497 printf_filtered (" frame pointer is at %s+%d\n", \ 498 reg_names[fi->proc_desc->pdr.framereg], \ 499 fi->proc_desc->pdr.frameoffset); \ 500 } 501 502 /* It takes two values to specify a frame on the MIPS. 503 504 In fact, the *PC* is the primary value that sets up a frame. The 505 PC is looked up to see what function it's in; symbol information 506 from that function tells us which register is the frame pointer 507 base, and what offset from there is the "virtual frame pointer". 508 (This is usually an offset from SP.) On most non-MIPS machines, 509 the primary value is the SP, and the PC, if needed, disambiguates 510 multiple functions with the same SP. But on the MIPS we can't do 511 that since the PC is not stored in the same part of the frame every 512 time. This does not seem to be a very clever way to set up frames, 513 but there is nothing we can do about that). */ 514 515 #define SETUP_ARBITRARY_FRAME(argc, argv) setup_arbitrary_frame (argc, argv) 516 extern struct frame_info *setup_arbitrary_frame PARAMS ((int, CORE_ADDR *)); 517 518 /* Convert a dbx stab register number (from `r' declaration) to a gdb REGNUM */ 519 520 #define STAB_REG_TO_REGNUM(num) ((num) < 32 ? (num) : (num)+FP0_REGNUM-38) 521 522 /* Convert a ecoff register number to a gdb REGNUM */ 523 524 #define ECOFF_REG_TO_REGNUM(num) ((num) < 32 ? (num) : (num)+FP0_REGNUM-32) 525 526 /* If the current gcc for for this target does not produce correct debugging 527 information for float parameters, both prototyped and unprototyped, then 528 define this macro. This forces gdb to always assume that floats are 529 passed as doubles and then converted in the callee. 530 531 For the mips chip, it appears that the debug info marks the parameters as 532 floats regardless of whether the function is prototyped, but the actual 533 values are passed as doubles for the non-prototyped case and floats for 534 the prototyped case. Thus we choose to make the non-prototyped case work 535 for C and break the prototyped case, since the non-prototyped case is 536 probably much more common. (FIXME). */ 537 538 #define COERCE_FLOAT_TO_DOUBLE (current_language -> la_language == language_c) 539 540 /* These are defined in mdebugread.c and are used in mips-tdep.c */ 541 extern CORE_ADDR sigtramp_address, sigtramp_end; 542 extern void fixup_sigtramp PARAMS ((void)); 543 544 /* Defined in mips-tdep.c and used in remote-mips.c */ 545 extern char *mips_read_processor_type PARAMS ((void)); 546 547 #ifndef TARGET_MIPS 548 #define TARGET_MIPS 549 #endif 550 551 #endif /* TM_MIPS_H */ 552