1@c Copyright (C) 1991, 92-98, 1999 Free Software Foundation, Inc. 2@c This is part of the GAS manual. 3@c For copying conditions, see the file as.texinfo. 4@ifset GENERIC 5@page 6@node M32R-Dependent 7@chapter M32R Dependent Features 8@end ifset 9@ifclear GENERIC 10@node Machine Dependencies 11@chapter M32R Dependent Features 12@end ifclear 13 14@cindex M32R support 15@menu 16* M32R-Opts:: M32R Options 17* M32R-Warnings:: M32R Warnings 18@end menu 19 20@node M32R-Opts 21@section M32R Options 22 23@cindex options, M32R 24@cindex M32R options 25 26The Mitsubishi M32R version of @code{@value{AS}} has a few machine 27dependent options: 28 29@table @code 30@item -m32rx 31@cindex @samp{-m32rx} option, M32RX 32@cindex architecture options, M32RX 33@cindex M32R architecture options 34@code{@value{AS}} can assemble code for several different members of the 35Mitsubishi M32R family. Normally the default is to assemble code for 36the M32R microprocessor. This option may be used to change the default 37to the M32RX microprocessor, which adds some more instructions to the 38basic M32R instruction set, and some additional parameters to some of 39the original instructions. 40 41@item -m32r 42@cindex @samp{-m32r} option, M32R 43@cindex architecture options, M32R 44@cindex M32R architecture options 45This option can be used to restore the assembler's default behaviour of 46assembling for the M32R microprocessor. This can be useful if the 47default has been changed by a previous command line option. 48 49@item -warn-explicit-parallel-conflicts 50@cindex @samp{-warn-explicit-parallel-conflicts} option, M32RX 51Instructs @code{@value{AS}} to produce warning messages when 52questionable parallel instructions are encountered. This option is 53enabled by default, but @code{@value{GCC}} disables it when it invokes 54@code{@value{AS}} directly. Questionable instructions are those whoes 55behaviour would be different if they were executed sequentially. For 56example the code fragment @samp{mv r1, r2 || mv r3, r1} produces a 57different result from @samp{mv r1, r2 \n mv r3, r1} since the former 58moves r1 into r3 and then r2 into r1, whereas the later moves r2 into r1 59and r3. 60 61@item -Wp 62@cindex @samp{-Wp} option, M32RX 63This is a shorter synonym for the @emph{-warn-explicit-parallel-conflicts} 64option. 65 66@item -no-warn-explicit-parallel-conflicts 67@cindex @samp{-no-warn-explicit-parallel-conflicts} option, M32RX 68Instructs @code{@value{AS}} not to produce warning messages when 69questionable parallel instructions are encountered. 70 71@item -Wnp 72@cindex @samp{-Wnp} option, M32RX 73This is a shorter synonym for the @emph{-no-warn-explicit-parallel-conflicts} 74option. 75 76@end table 77 78@node M32R-Warnings 79@section M32R Warnings 80 81@cindex warnings, M32R 82@cindex M32R warnings 83 84There are several warning and error messages that can be produced by 85@code{@value{AS}} which are specific to the M32R: 86 87@table @code 88 89@item output of 1st instruction is the same as an input to 2nd instruction - is this intentional ? 90This message is only produced if warnings for explicit parallel 91conflicts have been enabled. It indicates that the assembler has 92encountered a parallel instruction in which the destination register of 93the left hand instruction is used as an input register in the right hand 94instruction. For example in this code fragment 95@samp{mv r1, r2 || neg r3, r1} register r1 is the destination of the 96move instruction and the input to the neg instruction. 97 98@item output of 2nd instruction is the same as an input to 1st instruction - is this intentional ? 99This message is only produced if warnings for explicit parallel 100conflicts have been enabled. It indicates that the assembler has 101encountered a parallel instruction in which the destination register of 102the right hand instruction is used as an input register in the left hand 103instruction. For example in this code fragment 104@samp{mv r1, r2 || neg r2, r3} register r2 is the destination of the 105neg instruction and the input to the move instruction. 106 107@item instruction @samp{...} is for the M32RX only 108This message is produced when the assembler encounters an instruction 109which is only supported by the M32Rx processor, and the @samp{-m32rx} 110command line flag has not been specified to allow assembly of such 111instructions. 112 113@item unknown instruction @samp{...} 114This message is produced when the assembler encounters an instruction 115which it doe snot recognise. 116 117@item only the NOP instruction can be issued in parallel on the m32r 118This message is produced when the assembler encounters a parallel 119instruction which does not involve a NOP instruction and the 120@samp{-m32rx} command line flag has not been specified. Only the M32Rx 121processor is able to execute two instructions in parallel. 122 123@item instruction @samp{...} cannot be executed in parallel. 124This message is produced when the assembler encounters a parallel 125instruction which is made up of one or two instructions which cannot be 126executed in parallel. 127 128@item Instructions share the same execution pipeline 129This message is produced when the assembler encounters a parallel 130instruction whoes components both use the same execution pipeline. 131 132@item Instructions write to the same destination register. 133This message is produced when the assembler encounters a parallel 134instruction where both components attempt to modify the same register. 135For example these code fragments will produce this message: 136@samp{mv r1, r2 || neg r1, r3} 137@samp{jl r0 || mv r14, r1} 138@samp{st r2, @@-r1 || mv r1, r3} 139@samp{mv r1, r2 || ld r0, @@r1+} 140@samp{cmp r1, r2 || addx r3, r4} (Both write to the condition bit) 141 142@end table 143