1 /* tc-m32r.c -- Assembler for the Mitsubishi M32R. 2 Copyright (C) 1996, 1997, 1998, 1999 Free Software Foundation. 3 4 This file is part of GAS, the GNU Assembler. 5 6 GAS is free software; you can redistribute it and/or modify 7 it under the terms of the GNU General Public License as published by 8 the Free Software Foundation; either version 2, or (at your option) 9 any later version. 10 11 GAS is distributed in the hope that it will be useful, 12 but WITHOUT ANY WARRANTY; without even the implied warranty of 13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 GNU General Public License for more details. 15 16 You should have received a copy of the GNU General Public License 17 along with GAS; see the file COPYING. If not, write to 18 the Free Software Foundation, 59 Temple Place - Suite 330, 19 Boston, MA 02111-1307, USA. */ 20 21 #include <stdio.h> 22 #include <ctype.h> 23 #include "as.h" 24 #include "subsegs.h" 25 #include "symcat.h" 26 #include "opcodes/m32r-desc.h" 27 #include "opcodes/m32r-opc.h" 28 #include "cgen.h" 29 30 /* Linked list of symbols that are debugging symbols to be defined as the 31 beginning of the current instruction. */ 32 typedef struct sym_link 33 { 34 struct sym_link *next; 35 symbolS *symbol; 36 } sym_linkS; 37 38 static sym_linkS *debug_sym_link = (sym_linkS *)0; 39 40 /* Structure to hold all of the different components describing 41 an individual instruction. */ 42 typedef struct 43 { 44 const CGEN_INSN * insn; 45 const CGEN_INSN * orig_insn; 46 CGEN_FIELDS fields; 47 #if CGEN_INT_INSN_P 48 CGEN_INSN_INT buffer [1]; 49 #define INSN_VALUE(buf) (*(buf)) 50 #else 51 unsigned char buffer [CGEN_MAX_INSN_SIZE]; 52 #define INSN_VALUE(buf) (buf) 53 #endif 54 char * addr; 55 fragS * frag; 56 int num_fixups; 57 fixS * fixups [GAS_CGEN_MAX_FIXUPS]; 58 int indices [MAX_OPERAND_INSTANCES]; 59 sym_linkS *debug_sym_link; 60 } 61 m32r_insn; 62 63 /* prev_insn.insn is non-null if last insn was a 16 bit insn on a 32 bit 64 boundary (i.e. was the first of two 16 bit insns). */ 65 static m32r_insn prev_insn; 66 67 /* Non-zero if we've seen a relaxable insn since the last 32 bit 68 alignment request. */ 69 static int seen_relaxable_p = 0; 70 71 /* Non-zero if -relax specified, in which case sufficient relocs are output 72 for the linker to do relaxing. 73 We do simple forms of relaxing internally, but they are always done. 74 This flag does not apply to them. */ 75 static int m32r_relax; 76 77 #if 0 /* not supported yet */ 78 /* If non-NULL, pointer to cpu description file to read. 79 This allows runtime additions to the assembler. */ 80 static const char * m32r_cpu_desc; 81 #endif 82 83 /* Non-zero if warn when a high/shigh reloc has no matching low reloc. 84 Each high/shigh reloc must be paired with it's low cousin in order to 85 properly calculate the addend in a relocatable link (since there is a 86 potential carry from the low to the high/shigh). 87 This option is off by default though for user-written assembler code it 88 might make sense to make the default be on (i.e. have gcc pass a flag 89 to turn it off). This warning must not be on for GCC created code as 90 optimization may delete the low but not the high/shigh (at least we 91 shouldn't assume or require it to). */ 92 static int warn_unmatched_high = 0; 93 94 /* Non-zero if -m32rx has been specified, in which case support for the 95 extended M32RX instruction set should be enabled. */ 96 static int enable_m32rx = 0; 97 98 /* Non-zero if -m32rx -hidden has been specified, in which case support for 99 the special M32RX instruction set should be enabled. */ 100 static int enable_special = 0; 101 102 /* Non-zero if the programmer should be warned when an explicit parallel 103 instruction might have constraint violations. */ 104 static int warn_explicit_parallel_conflicts = 1; 105 106 /* Non-zero if insns can be made parallel. */ 107 static int optimize; 108 109 /* stuff for .scomm symbols. */ 110 static segT sbss_section; 111 static asection scom_section; 112 static asymbol scom_symbol; 113 114 const char comment_chars[] = ";"; 115 const char line_comment_chars[] = "#"; 116 const char line_separator_chars[] = ""; 117 const char EXP_CHARS[] = "eE"; 118 const char FLT_CHARS[] = "dD"; 119 120 /* Relocations against symbols are done in two 121 parts, with a HI relocation and a LO relocation. Each relocation 122 has only 16 bits of space to store an addend. This means that in 123 order for the linker to handle carries correctly, it must be able 124 to locate both the HI and the LO relocation. This means that the 125 relocations must appear in order in the relocation table. 126 127 In order to implement this, we keep track of each unmatched HI 128 relocation. We then sort them so that they immediately precede the 129 corresponding LO relocation. */ 130 131 struct m32r_hi_fixup 132 { 133 struct m32r_hi_fixup * next; /* Next HI fixup. */ 134 fixS * fixp; /* This fixup. */ 135 segT seg; /* The section this fixup is in. */ 136 137 }; 138 139 /* The list of unmatched HI relocs. */ 140 141 static struct m32r_hi_fixup * m32r_hi_fixup_list; 142 143 144 static void 145 allow_m32rx (on) 146 int on; 147 { 148 enable_m32rx = on; 149 150 if (stdoutput != NULL) 151 bfd_set_arch_mach (stdoutput, TARGET_ARCH, 152 enable_m32rx ? bfd_mach_m32rx : bfd_mach_m32r); 153 } 154 155 #define M32R_SHORTOPTS "O" 156 const char * md_shortopts = M32R_SHORTOPTS; 157 158 struct option md_longopts[] = 159 { 160 #define OPTION_M32R (OPTION_MD_BASE) 161 #define OPTION_M32RX (OPTION_M32R + 1) 162 #define OPTION_WARN_PARALLEL (OPTION_M32RX + 1) 163 #define OPTION_NO_WARN_PARALLEL (OPTION_WARN_PARALLEL + 1) 164 #define OPTION_SPECIAL (OPTION_NO_WARN_PARALLEL + 1) 165 #define OPTION_WARN_UNMATCHED (OPTION_SPECIAL + 1) 166 #define OPTION_NO_WARN_UNMATCHED (OPTION_WARN_UNMATCHED + 1) 167 {"m32r", no_argument, NULL, OPTION_M32R}, 168 {"m32rx", no_argument, NULL, OPTION_M32RX}, 169 {"warn-explicit-parallel-conflicts", no_argument, NULL, OPTION_WARN_PARALLEL}, 170 {"Wp", no_argument, NULL, OPTION_WARN_PARALLEL}, 171 {"no-warn-explicit-parallel-conflicts", no_argument, NULL, OPTION_NO_WARN_PARALLEL}, 172 {"Wnp", no_argument, NULL, OPTION_NO_WARN_PARALLEL}, 173 {"hidden", no_argument, NULL, OPTION_SPECIAL}, 174 /* Sigh. I guess all warnings must now have both variants. */ 175 {"warn-unmatched-high", no_argument, NULL, OPTION_WARN_UNMATCHED}, 176 {"Wuh", no_argument, NULL, OPTION_WARN_UNMATCHED}, 177 {"no-warn-unmatched-high", no_argument, NULL, OPTION_NO_WARN_UNMATCHED}, 178 {"Wnuh", no_argument, NULL, OPTION_NO_WARN_UNMATCHED}, 179 180 #if 0 /* not supported yet */ 181 #define OPTION_RELAX (OPTION_NO_WARN_UNMATCHED + 1) 182 #define OPTION_CPU_DESC (OPTION_RELAX + 1) 183 {"relax", no_argument, NULL, OPTION_RELAX}, 184 {"cpu-desc", required_argument, NULL, OPTION_CPU_DESC}, 185 #endif 186 {NULL, no_argument, NULL, 0} 187 }; 188 size_t md_longopts_size = sizeof (md_longopts); 189 190 int 191 md_parse_option (c, arg) 192 int c; 193 char * arg; 194 { 195 switch (c) 196 { 197 case 'O': 198 optimize = 1; 199 break; 200 201 case OPTION_M32R: 202 allow_m32rx (0); 203 break; 204 205 case OPTION_M32RX: 206 allow_m32rx (1); 207 break; 208 209 case OPTION_WARN_PARALLEL: 210 warn_explicit_parallel_conflicts = 1; 211 break; 212 213 case OPTION_NO_WARN_PARALLEL: 214 warn_explicit_parallel_conflicts = 0; 215 break; 216 217 case OPTION_SPECIAL: 218 if (enable_m32rx) 219 enable_special = 1; 220 else 221 { 222 /* Pretend that we do not recognise this option. */ 223 as_bad (_("Unrecognised option: -hidden")); 224 return 0; 225 } 226 break; 227 228 case OPTION_WARN_UNMATCHED: 229 warn_unmatched_high = 1; 230 break; 231 232 case OPTION_NO_WARN_UNMATCHED: 233 warn_unmatched_high = 0; 234 break; 235 236 #if 0 /* not supported yet */ 237 case OPTION_RELAX: 238 m32r_relax = 1; 239 break; 240 case OPTION_CPU_DESC: 241 m32r_cpu_desc = arg; 242 break; 243 #endif 244 245 default: 246 return 0; 247 } 248 249 return 1; 250 } 251 252 void 253 md_show_usage (stream) 254 FILE * stream; 255 { 256 fprintf (stream, _(" M32R specific command line options:\n")); 257 258 fprintf (stream, _("\ 259 -m32r disable support for the m32rx instruction set\n")); 260 fprintf (stream, _("\ 261 -m32rx support the extended m32rx instruction set\n")); 262 fprintf (stream, _("\ 263 -O try to combine instructions in parallel\n")); 264 265 fprintf (stream, _("\ 266 -warn-explicit-parallel-conflicts warn when parallel instructions\n")); 267 fprintf (stream, _("\ 268 violate contraints\n")); 269 fprintf (stream, _("\ 270 -no-warn-explicit-parallel-conflicts do not warn when parallel\n")); 271 fprintf (stream, _("\ 272 instructions violate contraints\n")); 273 fprintf (stream, _("\ 274 -Wp synonym for -warn-explicit-parallel-conflicts\n")); 275 fprintf (stream, _("\ 276 -Wnp synonym for -no-warn-explicit-parallel-conflicts\n")); 277 278 fprintf (stream, _("\ 279 -warn-unmatched-high warn when an (s)high reloc has no matching low reloc\n")); 280 fprintf (stream, _("\ 281 -no-warn-unmatched-high do not warn about missing low relocs\n")); 282 fprintf (stream, _("\ 283 -Wuh synonym for -warn-unmatched-high\n")); 284 fprintf (stream, _("\ 285 -Wnuh synonym for -no-warn-unmatched-high\n")); 286 287 #if 0 288 fprintf (stream, _("\ 289 -relax create linker relaxable code\n")); 290 fprintf (stream, _("\ 291 -cpu-desc provide runtime cpu description file\n")); 292 #endif 293 } 294 295 static void fill_insn PARAMS ((int)); 296 static void m32r_scomm PARAMS ((int)); 297 static void debug_sym PARAMS ((int)); 298 static void expand_debug_syms PARAMS ((sym_linkS *, int)); 299 300 /* Set by md_assemble for use by m32r_fill_insn. */ 301 static subsegT prev_subseg; 302 static segT prev_seg; 303 304 /* The target specific pseudo-ops which we support. */ 305 const pseudo_typeS md_pseudo_table[] = 306 { 307 { "word", cons, 4 }, 308 { "fillinsn", fill_insn, 0 }, 309 { "scomm", m32r_scomm, 0 }, 310 { "debugsym", debug_sym, 0 }, 311 /* Not documented as so far there is no need for them.... */ 312 { "m32r", allow_m32rx, 0 }, 313 { "m32rx", allow_m32rx, 1 }, 314 { NULL, NULL, 0 } 315 }; 316 317 /* FIXME: Should be machine generated. */ 318 #define NOP_INSN 0x7000 319 #define PAR_NOP_INSN 0xf000 /* can only be used in 2nd slot */ 320 321 /* When we align the .text section, insert the correct NOP pattern. 322 N is the power of 2 alignment. LEN is the length of pattern FILL. 323 MAX is the maximum number of characters to skip when doing the alignment, 324 or 0 if there is no maximum. */ 325 326 int 327 m32r_do_align (n, fill, len, max) 328 int n; 329 const char * fill; 330 int len; 331 int max; 332 { 333 /* Only do this if the fill pattern wasn't specified. */ 334 if (fill == NULL 335 && subseg_text_p (now_seg) 336 /* Only do this special handling if aligning to at least a 337 4 byte boundary. */ 338 && n > 1 339 /* Only do this special handling if we're allowed to emit at 340 least two bytes. */ 341 && (max == 0 || max > 1)) 342 { 343 static const unsigned char nop_pattern[] = { 0xf0, 0x00 }; 344 345 #if 0 346 /* First align to a 2 byte boundary, in case there is an odd .byte. */ 347 /* FIXME: How much memory will cause gas to use when assembling a big 348 program? Perhaps we can avoid the frag_align call? */ 349 frag_align (1, 0, 0); 350 #endif 351 /* Next align to a 4 byte boundary (we know n >= 2) using a parallel 352 nop. */ 353 frag_align_pattern (2, nop_pattern, sizeof nop_pattern, 0); 354 /* If doing larger alignments use a repeating sequence of appropriate 355 nops. */ 356 if (n > 2) 357 { 358 static const unsigned char multi_nop_pattern[] = 359 { 0x70, 0x00, 0xf0, 0x00 }; 360 frag_align_pattern (n, multi_nop_pattern, sizeof multi_nop_pattern, 361 max ? max - 2 : 0); 362 } 363 364 prev_insn.insn = NULL; 365 return 1; 366 } 367 368 return 0; 369 } 370 371 /* If the last instruction was the first of 2 16 bit insns, 372 output a nop to move the PC to a 32 bit boundary. 373 374 This is done via an alignment specification since branch relaxing 375 may make it unnecessary. 376 377 Internally, we need to output one of these each time a 32 bit insn is 378 seen after an insn that is relaxable. */ 379 380 static void 381 fill_insn (ignore) 382 int ignore; 383 { 384 (void) m32r_do_align (2, NULL, 0, 0); 385 prev_insn.insn = NULL; 386 seen_relaxable_p = 0; 387 } 388 389 /* Record the symbol so that when we output the insn, we can create 390 a symbol that is at the start of the instruction. This is used 391 to emit the label for the start of a breakpoint without causing 392 the assembler to emit a NOP if the previous instruction was a 393 16 bit instruction. */ 394 395 static void 396 debug_sym (ignore) 397 int ignore; 398 { 399 register char *name; 400 register char delim; 401 register char *end_name; 402 register symbolS *symbolP; 403 register sym_linkS *link; 404 405 name = input_line_pointer; 406 delim = get_symbol_end (); 407 end_name = input_line_pointer; 408 409 if ((symbolP = symbol_find (name)) == NULL 410 && (symbolP = md_undefined_symbol (name)) == NULL) 411 { 412 symbolP = symbol_new (name, undefined_section, 0, &zero_address_frag); 413 } 414 415 symbol_table_insert (symbolP); 416 if (S_IS_DEFINED (symbolP) && S_GET_SEGMENT (symbolP) != reg_section) 417 /* xgettext:c-format */ 418 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP)); 419 420 else 421 { 422 link = (sym_linkS *) xmalloc (sizeof (sym_linkS)); 423 link->symbol = symbolP; 424 link->next = debug_sym_link; 425 debug_sym_link = link; 426 symbol_get_obj (symbolP)->local = 1; 427 } 428 429 *end_name = delim; 430 demand_empty_rest_of_line (); 431 } 432 433 /* Second pass to expanding the debug symbols, go through linked 434 list of symbols and reassign the address. */ 435 436 static void 437 expand_debug_syms (syms, align) 438 sym_linkS *syms; 439 int align; 440 { 441 char *save_input_line = input_line_pointer; 442 sym_linkS *next_syms; 443 444 if (!syms) 445 return; 446 447 (void) m32r_do_align (align, NULL, 0, 0); 448 for (; syms != (sym_linkS *)0; syms = next_syms) 449 { 450 symbolS *symbolP = syms->symbol; 451 next_syms = syms->next; 452 input_line_pointer = ".\n"; 453 pseudo_set (symbolP); 454 free ((char *)syms); 455 } 456 457 input_line_pointer = save_input_line; 458 } 459 460 /* Cover function to fill_insn called after a label and at end of assembly. 461 The result is always 1: we're called in a conditional to see if the 462 current line is a label. */ 463 464 int 465 m32r_fill_insn (done) 466 int done; 467 { 468 if (prev_seg != NULL) 469 { 470 segT seg = now_seg; 471 subsegT subseg = now_subseg; 472 473 subseg_set (prev_seg, prev_subseg); 474 475 fill_insn (0); 476 477 subseg_set (seg, subseg); 478 } 479 480 if (done && debug_sym_link) 481 { 482 expand_debug_syms (debug_sym_link, 1); 483 debug_sym_link = (sym_linkS *)0; 484 } 485 486 return 1; 487 } 488 489 void 490 md_begin () 491 { 492 flagword applicable; 493 segT seg; 494 subsegT subseg; 495 496 /* Initialize the `cgen' interface. */ 497 498 /* Set the machine number and endian. */ 499 gas_cgen_cpu_desc = m32r_cgen_cpu_open (CGEN_CPU_OPEN_MACHS, 0, 500 CGEN_CPU_OPEN_ENDIAN, 501 CGEN_ENDIAN_BIG, 502 CGEN_CPU_OPEN_END); 503 m32r_cgen_init_asm (gas_cgen_cpu_desc); 504 505 /* The operand instance table is used during optimization to determine 506 which insns can be executed in parallel. It is also used to give 507 warnings regarding operand interference in parallel insns. */ 508 m32r_cgen_init_opinst_table (gas_cgen_cpu_desc); 509 510 /* This is a callback from cgen to gas to parse operands. */ 511 cgen_set_parse_operand_fn (gas_cgen_cpu_desc, gas_cgen_parse_operand); 512 513 #if 0 /* not supported yet */ 514 /* If a runtime cpu description file was provided, parse it. */ 515 if (m32r_cpu_desc != NULL) 516 { 517 const char * errmsg; 518 519 errmsg = cgen_read_cpu_file (gas_cgen_cpu_desc, m32r_cpu_desc); 520 if (errmsg != NULL) 521 as_bad ("%s: %s", m32r_cpu_desc, errmsg); 522 } 523 #endif 524 525 /* Save the current subseg so we can restore it [it's the default one and 526 we don't want the initial section to be .sbss]. */ 527 seg = now_seg; 528 subseg = now_subseg; 529 530 /* The sbss section is for local .scomm symbols. */ 531 sbss_section = subseg_new (".sbss", 0); 532 533 /* This is copied from perform_an_assembly_pass. */ 534 applicable = bfd_applicable_section_flags (stdoutput); 535 bfd_set_section_flags (stdoutput, sbss_section, applicable & SEC_ALLOC); 536 537 #if 0 /* What does this do? [see perform_an_assembly_pass] */ 538 seg_info (bss_section)->bss = 1; 539 #endif 540 541 subseg_set (seg, subseg); 542 543 /* We must construct a fake section similar to bfd_com_section 544 but with the name .scommon. */ 545 scom_section = bfd_com_section; 546 scom_section.name = ".scommon"; 547 scom_section.output_section = & scom_section; 548 scom_section.symbol = & scom_symbol; 549 scom_section.symbol_ptr_ptr = & scom_section.symbol; 550 scom_symbol = * bfd_com_section.symbol; 551 scom_symbol.name = ".scommon"; 552 scom_symbol.section = & scom_section; 553 554 allow_m32rx (enable_m32rx); 555 } 556 557 #define OPERAND_IS_COND_BIT(operand, indices, index) \ 558 ((operand)->hw_type == HW_H_COND \ 559 || ((operand)->hw_type == HW_H_PSW) \ 560 || ((operand)->hw_type == HW_H_CR \ 561 && (indices [index] == 0 || indices [index] == 1))) 562 563 /* Returns true if an output of instruction 'a' is referenced by an operand 564 of instruction 'b'. If 'check_outputs' is true then b's outputs are 565 checked, otherwise its inputs are examined. */ 566 567 static int 568 first_writes_to_seconds_operands (a, b, check_outputs) 569 m32r_insn * a; 570 m32r_insn * b; 571 const int check_outputs; 572 { 573 const CGEN_OPINST * a_operands = CGEN_INSN_OPERANDS (a->insn); 574 const CGEN_OPINST * b_ops = CGEN_INSN_OPERANDS (b->insn); 575 int a_index; 576 577 /* If at least one of the instructions takes no operands, then there is 578 nothing to check. There really are instructions without operands, 579 eg 'nop'. */ 580 if (a_operands == NULL || b_ops == NULL) 581 return 0; 582 583 /* Scan the operand list of 'a' looking for an output operand. */ 584 for (a_index = 0; 585 a_operands->type != CGEN_OPINST_END; 586 a_index ++, a_operands ++) 587 { 588 if (a_operands->type == CGEN_OPINST_OUTPUT) 589 { 590 int b_index; 591 const CGEN_OPINST * b_operands = b_ops; 592 593 /* Special Case: 594 The Condition bit 'C' is a shadow of the CBR register (control 595 register 1) and also a shadow of bit 31 of the program status 596 word (control register 0). For now this is handled here, rather 597 than by cgen.... */ 598 599 if (OPERAND_IS_COND_BIT (a_operands, a->indices, a_index)) 600 { 601 /* Scan operand list of 'b' looking for another reference to the 602 condition bit, which goes in the right direction. */ 603 for (b_index = 0; 604 b_operands->type != CGEN_OPINST_END; 605 b_index ++, b_operands ++) 606 { 607 if ((b_operands->type 608 == (check_outputs 609 ? CGEN_OPINST_OUTPUT 610 : CGEN_OPINST_INPUT)) 611 && OPERAND_IS_COND_BIT (b_operands, b->indices, b_index)) 612 return 1; 613 } 614 } 615 else 616 { 617 /* Scan operand list of 'b' looking for an operand that 618 references the same hardware element, and which goes in the 619 right direction. */ 620 for (b_index = 0; 621 b_operands->type != CGEN_OPINST_END; 622 b_index ++, b_operands ++) 623 { 624 if ((b_operands->type 625 == (check_outputs 626 ? CGEN_OPINST_OUTPUT 627 : CGEN_OPINST_INPUT)) 628 && (b_operands->hw_type == a_operands->hw_type) 629 && (a->indices [a_index] == b->indices [b_index])) 630 return 1; 631 } 632 } 633 } 634 } 635 636 return 0; 637 } 638 639 /* Returns true if the insn can (potentially) alter the program counter. */ 640 641 static int 642 writes_to_pc (a) 643 m32r_insn * a; 644 { 645 #if 0 /* Once PC operands are working.... */ 646 const CGEN_OPINST * a_operands == CGEN_INSN_OPERANDS (gas_cgen_cpu_desc, 647 a->insn); 648 649 if (a_operands == NULL) 650 return 0; 651 652 while (a_operands->type != CGEN_OPINST_END) 653 { 654 if (a_operands->operand != NULL 655 && CGEN_OPERAND_INDEX (gas_cgen_cpu_desc, a_operands->operand) == M32R_OPERAND_PC) 656 return 1; 657 658 a_operands ++; 659 } 660 #else 661 if (CGEN_INSN_ATTR_VALUE (a->insn, CGEN_INSN_UNCOND_CTI) 662 || CGEN_INSN_ATTR_VALUE (a->insn, CGEN_INSN_COND_CTI)) 663 return 1; 664 #endif 665 return 0; 666 } 667 668 /* Returns NULL if the two 16 bit insns can be executed in parallel, 669 otherwise it returns a pointer to an error message explaining why not. */ 670 671 static const char * 672 can_make_parallel (a, b) 673 m32r_insn * a; 674 m32r_insn * b; 675 { 676 PIPE_ATTR a_pipe; 677 PIPE_ATTR b_pipe; 678 679 /* Make sure the instructions are the right length. */ 680 if ( CGEN_FIELDS_BITSIZE (& a->fields) != 16 681 || CGEN_FIELDS_BITSIZE (& b->fields) != 16) 682 abort(); 683 684 if (first_writes_to_seconds_operands (a, b, true)) 685 return _("Instructions write to the same destination register."); 686 687 a_pipe = CGEN_INSN_ATTR_VALUE (a->insn, CGEN_INSN_PIPE); 688 b_pipe = CGEN_INSN_ATTR_VALUE (b->insn, CGEN_INSN_PIPE); 689 690 /* Make sure that the instructions use the correct execution pipelines. */ 691 if ( a_pipe == PIPE_NONE 692 || b_pipe == PIPE_NONE) 693 return _("Instructions do not use parallel execution pipelines."); 694 695 /* Leave this test for last, since it is the only test that can 696 go away if the instructions are swapped, and we want to make 697 sure that any other errors are detected before this happens. */ 698 if ( a_pipe == PIPE_S 699 || b_pipe == PIPE_O) 700 return _("Instructions share the same execution pipeline"); 701 702 return NULL; 703 } 704 705 /* Force the top bit of the second 16-bit insn to be set. */ 706 707 static void 708 make_parallel (buffer) 709 CGEN_INSN_BYTES_PTR buffer; 710 { 711 #if CGEN_INT_INSN_P 712 *buffer |= 0x8000; 713 #else 714 buffer [CGEN_CPU_ENDIAN (gas_cgen_cpu_desc) == CGEN_ENDIAN_BIG ? 0 : 1] 715 |= 0x80; 716 #endif 717 } 718 719 /* Same as make_parallel except buffer contains the bytes in target order. */ 720 721 static void 722 target_make_parallel (buffer) 723 char *buffer; 724 { 725 buffer [CGEN_CPU_ENDIAN (gas_cgen_cpu_desc) == CGEN_ENDIAN_BIG ? 0 : 1] 726 |= 0x80; 727 } 728 729 /* Assemble two instructions with an explicit parallel operation (||) or 730 sequential operation (->). */ 731 732 static void 733 assemble_two_insns (str, str2, parallel_p) 734 char * str; 735 char * str2; 736 int parallel_p; 737 { 738 char * str3; 739 m32r_insn first; 740 m32r_insn second; 741 char * errmsg; 742 char save_str2 = *str2; 743 744 * str2 = 0; /* Seperate the two instructions. */ 745 746 /* Make sure the two insns begin on a 32 bit boundary. 747 This is also done for the serial case (foo -> bar), relaxing doesn't 748 affect insns written like this. 749 Note that we must always do this as we can't assume anything about 750 whether we're currently on a 32 bit boundary or not. Relaxing may 751 change this. */ 752 fill_insn (0); 753 754 first.debug_sym_link = debug_sym_link; 755 debug_sym_link = (sym_linkS *)0; 756 757 /* Parse the first instruction. */ 758 if (! (first.insn = m32r_cgen_assemble_insn 759 (gas_cgen_cpu_desc, str, & first.fields, first.buffer, & errmsg))) 760 { 761 as_bad (errmsg); 762 return; 763 } 764 765 /* Check it. */ 766 if (CGEN_FIELDS_BITSIZE (&first.fields) != 16) 767 { 768 /* xgettext:c-format */ 769 as_bad (_("not a 16 bit instruction '%s'"), str); 770 return; 771 } 772 else if (! enable_special 773 && CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_SPECIAL)) 774 { 775 /* xgettext:c-format */ 776 as_bad (_("unknown instruction '%s'"), str); 777 return; 778 } 779 else if (! enable_m32rx 780 /* FIXME: Need standard macro to perform this test. */ 781 && CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_MACH) == (1 << MACH_M32RX)) 782 { 783 /* xgettext:c-format */ 784 as_bad (_("instruction '%s' is for the M32RX only"), str); 785 return; 786 } 787 788 /* Check to see if this is an allowable parallel insn. */ 789 if (parallel_p && CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_PIPE) == PIPE_NONE) 790 { 791 /* xgettext:c-format */ 792 as_bad (_("instruction '%s' cannot be executed in parallel."), str); 793 return; 794 } 795 796 *str2 = save_str2; /* Restore the original assembly text, just in case it is needed. */ 797 str3 = str; /* Save the original string pointer. */ 798 str = str2 + 2; /* Advanced past the parsed string. */ 799 str2 = str3; /* Remember the entire string in case it is needed for error messages. */ 800 801 /* Convert the opcode to lower case. */ 802 { 803 char *s2 = str; 804 805 while (isspace (*s2 ++)) 806 continue; 807 808 --s2; 809 810 while (isalnum (*s2)) 811 { 812 if (isupper ((unsigned char) *s2)) 813 *s2 = tolower (*s2); 814 s2 ++; 815 } 816 } 817 818 /* Preserve any fixups that have been generated and reset the list to empty. */ 819 gas_cgen_save_fixups (); 820 821 /* Get the indices of the operands of the instruction. */ 822 /* FIXME: CGEN_FIELDS is already recorded, but relying on that fact 823 doesn't seem right. Perhaps allow passing fields like we do insn. */ 824 /* FIXME: ALIAS insns do not have operands, so we use this function 825 to find the equivalent insn and overwrite the value stored in our 826 structure. We still need the original insn, however, since this 827 may have certain attributes that are not present in the unaliased 828 version (eg relaxability). When aliases behave differently this 829 may have to change. */ 830 first.orig_insn = first.insn; 831 { 832 CGEN_FIELDS tmp_fields; 833 first.insn = cgen_lookup_get_insn_operands 834 (gas_cgen_cpu_desc, NULL, INSN_VALUE (first.buffer), NULL, 16, 835 first.indices, &tmp_fields); 836 } 837 838 if (first.insn == NULL) 839 as_fatal (_("internal error: lookup/get operands failed")); 840 841 second.debug_sym_link = NULL; 842 843 /* Parse the second instruction. */ 844 if (! (second.insn = m32r_cgen_assemble_insn 845 (gas_cgen_cpu_desc, str, & second.fields, second.buffer, & errmsg))) 846 { 847 as_bad (errmsg); 848 return; 849 } 850 851 /* Check it. */ 852 if (CGEN_FIELDS_BITSIZE (&second.fields) != 16) 853 { 854 /* xgettext:c-format */ 855 as_bad (_("not a 16 bit instruction '%s'"), str); 856 return; 857 } 858 else if (! enable_special 859 && CGEN_INSN_ATTR_VALUE (second.insn, CGEN_INSN_SPECIAL)) 860 { 861 /* xgettext:c-format */ 862 as_bad (_("unknown instruction '%s'"), str); 863 return; 864 } 865 else if (! enable_m32rx 866 && CGEN_INSN_ATTR_VALUE (second.insn, CGEN_INSN_MACH) == (1 << MACH_M32RX)) 867 { 868 /* xgettext:c-format */ 869 as_bad (_("instruction '%s' is for the M32RX only"), str); 870 return; 871 } 872 873 /* Check to see if this is an allowable parallel insn. */ 874 if (parallel_p && CGEN_INSN_ATTR_VALUE (second.insn, CGEN_INSN_PIPE) == PIPE_NONE) 875 { 876 /* xgettext:c-format */ 877 as_bad (_("instruction '%s' cannot be executed in parallel."), str); 878 return; 879 } 880 881 if (parallel_p && ! enable_m32rx) 882 { 883 if (CGEN_INSN_NUM (first.insn) != M32R_INSN_NOP 884 && CGEN_INSN_NUM (second.insn) != M32R_INSN_NOP) 885 { 886 /* xgettext:c-format */ 887 as_bad (_("'%s': only the NOP instruction can be issued in parallel on the m32r"), str2); 888 return; 889 } 890 } 891 892 /* Get the indices of the operands of the instruction. */ 893 second.orig_insn = second.insn; 894 { 895 CGEN_FIELDS tmp_fields; 896 second.insn = cgen_lookup_get_insn_operands 897 (gas_cgen_cpu_desc, NULL, INSN_VALUE (second.buffer), NULL, 16, 898 second.indices, &tmp_fields); 899 } 900 901 if (second.insn == NULL) 902 as_fatal (_("internal error: lookup/get operands failed")); 903 904 /* We assume that if the first instruction writes to a register that is 905 read by the second instruction it is because the programmer intended 906 this to happen, (after all they have explicitly requested that these 907 two instructions be executed in parallel). Although if the global 908 variable warn_explicit_parallel_conflicts is true then we do generate 909 a warning message. Similarly we assume that parallel branch and jump 910 instructions are deliberate and should not produce errors. */ 911 912 if (parallel_p && warn_explicit_parallel_conflicts) 913 { 914 if (first_writes_to_seconds_operands (& first, & second, false)) 915 /* xgettext:c-format */ 916 as_warn (_("%s: output of 1st instruction is the same as an input to 2nd instruction - is this intentional ?"), str2); 917 918 if (first_writes_to_seconds_operands (& second, & first, false)) 919 /* xgettext:c-format */ 920 as_warn (_("%s: output of 2nd instruction is the same as an input to 1st instruction - is this intentional ?"), str2); 921 } 922 923 if (!parallel_p 924 || (errmsg = (char *) can_make_parallel (& first, & second)) == NULL) 925 { 926 /* Get the fixups for the first instruction. */ 927 gas_cgen_swap_fixups (); 928 929 /* Write it out. */ 930 expand_debug_syms (first.debug_sym_link, 1); 931 gas_cgen_finish_insn (first.orig_insn, first.buffer, 932 CGEN_FIELDS_BITSIZE (& first.fields), 0, NULL); 933 934 /* Force the top bit of the second insn to be set. */ 935 if (parallel_p) 936 make_parallel (second.buffer); 937 938 /* Get its fixups. */ 939 gas_cgen_restore_fixups (); 940 941 /* Write it out. */ 942 expand_debug_syms (second.debug_sym_link, 1); 943 gas_cgen_finish_insn (second.orig_insn, second.buffer, 944 CGEN_FIELDS_BITSIZE (& second.fields), 0, NULL); 945 } 946 /* Try swapping the instructions to see if they work that way. */ 947 else if (can_make_parallel (& second, & first) == NULL) 948 { 949 /* Write out the second instruction first. */ 950 expand_debug_syms (second.debug_sym_link, 1); 951 gas_cgen_finish_insn (second.orig_insn, second.buffer, 952 CGEN_FIELDS_BITSIZE (& second.fields), 0, NULL); 953 954 /* Force the top bit of the first instruction to be set. */ 955 make_parallel (first.buffer); 956 957 /* Get the fixups for the first instruction. */ 958 gas_cgen_restore_fixups (); 959 960 /* Write out the first instruction. */ 961 expand_debug_syms (first.debug_sym_link, 1); 962 gas_cgen_finish_insn (first.orig_insn, first.buffer, 963 CGEN_FIELDS_BITSIZE (& first.fields), 0, NULL); 964 } 965 else 966 { 967 as_bad ("'%s': %s", str2, errmsg); 968 return; 969 } 970 971 /* Set these so m32r_fill_insn can use them. */ 972 prev_seg = now_seg; 973 prev_subseg = now_subseg; 974 } 975 976 void 977 md_assemble (str) 978 char * str; 979 { 980 m32r_insn insn; 981 char * errmsg; 982 char * str2 = NULL; 983 984 /* Initialize GAS's cgen interface for a new instruction. */ 985 gas_cgen_init_parse (); 986 987 /* Look for a parallel instruction seperator. */ 988 if ((str2 = strstr (str, "||")) != NULL) 989 { 990 assemble_two_insns (str, str2, 1); 991 return; 992 } 993 994 /* Also look for a sequential instruction seperator. */ 995 if ((str2 = strstr (str, "->")) != NULL) 996 { 997 assemble_two_insns (str, str2, 0); 998 return; 999 } 1000 1001 insn.debug_sym_link = debug_sym_link; 1002 debug_sym_link = (sym_linkS *)0; 1003 1004 insn.insn = m32r_cgen_assemble_insn 1005 (gas_cgen_cpu_desc, str, & insn.fields, insn.buffer, & errmsg); 1006 1007 if (!insn.insn) 1008 { 1009 as_bad (errmsg); 1010 return; 1011 } 1012 1013 if (! enable_special 1014 && CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_SPECIAL)) 1015 { 1016 /* xgettext:c-format */ 1017 as_bad (_("unknown instruction '%s'"), str); 1018 return; 1019 } 1020 else if (! enable_m32rx 1021 && CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_MACH) == (1 << MACH_M32RX)) 1022 { 1023 /* xgettext:c-format */ 1024 as_bad (_("instruction '%s' is for the M32RX only"), str); 1025 return; 1026 } 1027 1028 if (CGEN_INSN_BITSIZE (insn.insn) == 32) 1029 { 1030 /* 32 bit insns must live on 32 bit boundaries. */ 1031 if (prev_insn.insn || seen_relaxable_p) 1032 { 1033 /* ??? If calling fill_insn too many times turns us into a memory 1034 pig, can we call a fn to assemble a nop instead of 1035 !seen_relaxable_p? */ 1036 fill_insn (0); 1037 } 1038 1039 expand_debug_syms (insn.debug_sym_link, 2); 1040 1041 /* Doesn't really matter what we pass for RELAX_P here. */ 1042 gas_cgen_finish_insn (insn.insn, insn.buffer, 1043 CGEN_FIELDS_BITSIZE (& insn.fields), 1, NULL); 1044 } 1045 else 1046 { 1047 int on_32bit_boundary_p; 1048 int swap = false; 1049 1050 if (CGEN_INSN_BITSIZE (insn.insn) != 16) 1051 abort(); 1052 1053 insn.orig_insn = insn.insn; 1054 1055 /* If the previous insn was relaxable, then it may be expanded 1056 to fill the current 16 bit slot. Emit a NOP here to occupy 1057 this slot, so that we can start at optimizing at a 32 bit 1058 boundary. */ 1059 if (prev_insn.insn && seen_relaxable_p && optimize) 1060 fill_insn (0); 1061 1062 if (enable_m32rx) 1063 { 1064 /* Get the indices of the operands of the instruction. 1065 FIXME: See assemble_parallel for notes on orig_insn. */ 1066 { 1067 CGEN_FIELDS tmp_fields; 1068 insn.insn = cgen_lookup_get_insn_operands 1069 (gas_cgen_cpu_desc, NULL, INSN_VALUE (insn.buffer), NULL, 1070 16, insn.indices, &tmp_fields); 1071 } 1072 1073 if (insn.insn == NULL) 1074 as_fatal (_("internal error: lookup/get operands failed")); 1075 } 1076 1077 /* Compute whether we're on a 32 bit boundary or not. 1078 prev_insn.insn is NULL when we're on a 32 bit boundary. */ 1079 on_32bit_boundary_p = prev_insn.insn == NULL; 1080 1081 /* Look to see if this instruction can be combined with the 1082 previous instruction to make one, parallel, 32 bit instruction. 1083 If the previous instruction (potentially) changed the flow of 1084 program control, then it cannot be combined with the current 1085 instruction. If the current instruction is relaxable, then it 1086 might be replaced with a longer version, so we cannot combine it. 1087 Also if the output of the previous instruction is used as an 1088 input to the current instruction then it cannot be combined. 1089 Otherwise call can_make_parallel() with both orderings of the 1090 instructions to see if they can be combined. */ 1091 if ( ! on_32bit_boundary_p 1092 && enable_m32rx 1093 && optimize 1094 && CGEN_INSN_ATTR_VALUE (insn.orig_insn, CGEN_INSN_RELAXABLE) == 0 1095 && ! writes_to_pc (& prev_insn) 1096 && ! first_writes_to_seconds_operands (& prev_insn, &insn, false) 1097 ) 1098 { 1099 if (can_make_parallel (& prev_insn, & insn) == NULL) 1100 make_parallel (insn.buffer); 1101 else if (can_make_parallel (& insn, & prev_insn) == NULL) 1102 swap = true; 1103 } 1104 1105 expand_debug_syms (insn.debug_sym_link, 1); 1106 1107 { 1108 int i; 1109 finished_insnS fi; 1110 1111 /* Ensure each pair of 16 bit insns is in the same frag. */ 1112 frag_grow (4); 1113 1114 gas_cgen_finish_insn (insn.orig_insn, insn.buffer, 1115 CGEN_FIELDS_BITSIZE (& insn.fields), 1116 1 /*relax_p*/, &fi); 1117 insn.addr = fi.addr; 1118 insn.frag = fi.frag; 1119 insn.num_fixups = fi.num_fixups; 1120 for (i = 0; i < fi.num_fixups; ++i) 1121 insn.fixups[i] = fi.fixups[i]; 1122 } 1123 1124 if (swap) 1125 { 1126 int i,tmp; 1127 1128 #define SWAP_BYTES(a,b) tmp = a; a = b; b = tmp 1129 1130 /* Swap the two insns */ 1131 SWAP_BYTES (prev_insn.addr [0], insn.addr [0]); 1132 SWAP_BYTES (prev_insn.addr [1], insn.addr [1]); 1133 1134 target_make_parallel (insn.addr); 1135 1136 /* Swap any relaxable frags recorded for the two insns. */ 1137 /* FIXME: Clarify. relaxation precludes parallel insns */ 1138 if (prev_insn.frag->fr_opcode == prev_insn.addr) 1139 prev_insn.frag->fr_opcode = insn.addr; 1140 else if (insn.frag->fr_opcode == insn.addr) 1141 insn.frag->fr_opcode = prev_insn.addr; 1142 1143 /* Update the addresses in any fixups. 1144 Note that we don't have to handle the case where each insn is in 1145 a different frag as we ensure they're in the same frag above. */ 1146 for (i = 0; i < prev_insn.num_fixups; ++i) 1147 prev_insn.fixups[i]->fx_where += 2; 1148 for (i = 0; i < insn.num_fixups; ++i) 1149 insn.fixups[i]->fx_where -= 2; 1150 } 1151 1152 /* Keep track of whether we've seen a pair of 16 bit insns. 1153 prev_insn.insn is NULL when we're on a 32 bit boundary. */ 1154 if (on_32bit_boundary_p) 1155 prev_insn = insn; 1156 else 1157 prev_insn.insn = NULL; 1158 1159 /* If the insn needs the following one to be on a 32 bit boundary 1160 (e.g. subroutine calls), fill this insn's slot. */ 1161 if (on_32bit_boundary_p 1162 && CGEN_INSN_ATTR_VALUE (insn.orig_insn, CGEN_INSN_FILL_SLOT) != 0) 1163 fill_insn (0); 1164 1165 /* If this is a relaxable insn (can be replaced with a larger version) 1166 mark the fact so that we can emit an alignment directive for a 1167 following 32 bit insn if we see one. */ 1168 if (CGEN_INSN_ATTR_VALUE (insn.orig_insn, CGEN_INSN_RELAXABLE) != 0) 1169 seen_relaxable_p = 1; 1170 } 1171 1172 /* Set these so m32r_fill_insn can use them. */ 1173 prev_seg = now_seg; 1174 prev_subseg = now_subseg; 1175 } 1176 1177 /* The syntax in the manual says constants begin with '#'. 1178 We just ignore it. */ 1179 1180 void 1181 md_operand (expressionP) 1182 expressionS * expressionP; 1183 { 1184 if (* input_line_pointer == '#') 1185 { 1186 input_line_pointer ++; 1187 expression (expressionP); 1188 } 1189 } 1190 1191 valueT 1192 md_section_align (segment, size) 1193 segT segment; 1194 valueT size; 1195 { 1196 int align = bfd_get_section_alignment (stdoutput, segment); 1197 return ((size + (1 << align) - 1) & (-1 << align)); 1198 } 1199 1200 symbolS * 1201 md_undefined_symbol (name) 1202 char * name; 1203 { 1204 return 0; 1205 } 1206 1207 /* .scomm pseudo-op handler. 1208 1209 This is a new pseudo-op to handle putting objects in .scommon. 1210 By doing this the linker won't need to do any work and more importantly 1211 it removes the implicit -G arg necessary to correctly link the object file. 1212 */ 1213 1214 static void 1215 m32r_scomm (ignore) 1216 int ignore; 1217 { 1218 register char * name; 1219 register char c; 1220 register char * p; 1221 offsetT size; 1222 register symbolS * symbolP; 1223 offsetT align; 1224 int align2; 1225 1226 name = input_line_pointer; 1227 c = get_symbol_end (); 1228 1229 /* just after name is now '\0' */ 1230 p = input_line_pointer; 1231 * p = c; 1232 SKIP_WHITESPACE (); 1233 if (* input_line_pointer != ',') 1234 { 1235 as_bad (_("Expected comma after symbol-name: rest of line ignored.")); 1236 ignore_rest_of_line (); 1237 return; 1238 } 1239 1240 input_line_pointer ++; /* skip ',' */ 1241 if ((size = get_absolute_expression ()) < 0) 1242 { 1243 /* xgettext:c-format */ 1244 as_warn (_(".SCOMMon length (%ld.) <0! Ignored."), (long) size); 1245 ignore_rest_of_line (); 1246 return; 1247 } 1248 1249 /* The third argument to .scomm is the alignment. */ 1250 if (* input_line_pointer != ',') 1251 align = 8; 1252 else 1253 { 1254 ++ input_line_pointer; 1255 align = get_absolute_expression (); 1256 if (align <= 0) 1257 { 1258 as_warn (_("ignoring bad alignment")); 1259 align = 8; 1260 } 1261 } 1262 /* Convert to a power of 2 alignment. */ 1263 if (align) 1264 { 1265 for (align2 = 0; (align & 1) == 0; align >>= 1, ++ align2) 1266 continue; 1267 if (align != 1) 1268 { 1269 as_bad (_("Common alignment not a power of 2")); 1270 ignore_rest_of_line (); 1271 return; 1272 } 1273 } 1274 else 1275 align2 = 0; 1276 1277 * p = 0; 1278 symbolP = symbol_find_or_make (name); 1279 * p = c; 1280 1281 if (S_IS_DEFINED (symbolP)) 1282 { 1283 /* xgettext:c-format */ 1284 as_bad (_("Ignoring attempt to re-define symbol `%s'."), 1285 S_GET_NAME (symbolP)); 1286 ignore_rest_of_line (); 1287 return; 1288 } 1289 1290 if (S_GET_VALUE (symbolP) && S_GET_VALUE (symbolP) != (valueT) size) 1291 { 1292 /* xgettext:c-format */ 1293 as_bad (_("Length of .scomm \"%s\" is already %ld. Not changed to %ld."), 1294 S_GET_NAME (symbolP), 1295 (long) S_GET_VALUE (symbolP), 1296 (long) size); 1297 1298 ignore_rest_of_line (); 1299 return; 1300 } 1301 1302 if (symbol_get_obj (symbolP)->local) 1303 { 1304 segT old_sec = now_seg; 1305 int old_subsec = now_subseg; 1306 char * pfrag; 1307 1308 record_alignment (sbss_section, align2); 1309 subseg_set (sbss_section, 0); 1310 1311 if (align2) 1312 frag_align (align2, 0, 0); 1313 1314 if (S_GET_SEGMENT (symbolP) == sbss_section) 1315 symbol_get_frag (symbolP)->fr_symbol = 0; 1316 1317 symbol_set_frag (symbolP, frag_now); 1318 1319 pfrag = frag_var (rs_org, 1, 1, (relax_substateT) 0, symbolP, size, 1320 (char *) 0); 1321 * pfrag = 0; 1322 S_SET_SIZE (symbolP, size); 1323 S_SET_SEGMENT (symbolP, sbss_section); 1324 S_CLEAR_EXTERNAL (symbolP); 1325 subseg_set (old_sec, old_subsec); 1326 } 1327 else 1328 { 1329 S_SET_VALUE (symbolP, (valueT) size); 1330 S_SET_ALIGN (symbolP, align2); 1331 S_SET_EXTERNAL (symbolP); 1332 S_SET_SEGMENT (symbolP, & scom_section); 1333 } 1334 1335 demand_empty_rest_of_line (); 1336 } 1337 1338 /* Interface to relax_segment. */ 1339 1340 /* FIXME: Build table by hand, get it working, then machine generate. */ 1341 1342 const relax_typeS md_relax_table[] = 1343 { 1344 /* The fields are: 1345 1) most positive reach of this state, 1346 2) most negative reach of this state, 1347 3) how many bytes this mode will add to the size of the current frag 1348 4) which index into the table to try if we can't fit into this one. */ 1349 1350 /* The first entry must be unused because an `rlx_more' value of zero ends 1351 each list. */ 1352 {1, 1, 0, 0}, 1353 1354 /* The displacement used by GAS is from the end of the 2 byte insn, 1355 so we subtract 2 from the following. */ 1356 /* 16 bit insn, 8 bit disp -> 10 bit range. 1357 This doesn't handle a branch in the right slot at the border: 1358 the "& -4" isn't taken into account. It's not important enough to 1359 complicate things over it, so we subtract an extra 2 (or + 2 in -ve 1360 case). */ 1361 {511 - 2 - 2, -512 - 2 + 2, 0, 2 }, 1362 /* 32 bit insn, 24 bit disp -> 26 bit range. */ 1363 {0x2000000 - 1 - 2, -0x2000000 - 2, 2, 0 }, 1364 /* Same thing, but with leading nop for alignment. */ 1365 {0x2000000 - 1 - 2, -0x2000000 - 2, 4, 0 } 1366 }; 1367 1368 long 1369 m32r_relax_frag (fragP, stretch) 1370 fragS * fragP; 1371 long stretch; 1372 { 1373 /* Address of branch insn. */ 1374 long address = fragP->fr_address + fragP->fr_fix - 2; 1375 long growth = 0; 1376 1377 /* Keep 32 bit insns aligned on 32 bit boundaries. */ 1378 if (fragP->fr_subtype == 2) 1379 { 1380 if ((address & 3) != 0) 1381 { 1382 fragP->fr_subtype = 3; 1383 growth = 2; 1384 } 1385 } 1386 else if (fragP->fr_subtype == 3) 1387 { 1388 if ((address & 3) == 0) 1389 { 1390 fragP->fr_subtype = 2; 1391 growth = -2; 1392 } 1393 } 1394 else 1395 { 1396 growth = relax_frag (fragP, stretch); 1397 1398 /* Long jump on odd halfword boundary? */ 1399 if (fragP->fr_subtype == 2 && (address & 3) != 0) 1400 { 1401 fragP->fr_subtype = 3; 1402 growth += 2; 1403 } 1404 } 1405 1406 return growth; 1407 } 1408 1409 /* Return an initial guess of the length by which a fragment must grow to 1410 hold a branch to reach its destination. 1411 Also updates fr_type/fr_subtype as necessary. 1412 1413 Called just before doing relaxation. 1414 Any symbol that is now undefined will not become defined. 1415 The guess for fr_var is ACTUALLY the growth beyond fr_fix. 1416 Whatever we do to grow fr_fix or fr_var contributes to our returned value. 1417 Although it may not be explicit in the frag, pretend fr_var starts with a 1418 0 value. */ 1419 1420 int 1421 md_estimate_size_before_relax (fragP, segment) 1422 fragS * fragP; 1423 segT segment; 1424 { 1425 int old_fr_fix = fragP->fr_fix; 1426 1427 /* The only thing we have to handle here are symbols outside of the 1428 current segment. They may be undefined or in a different segment in 1429 which case linker scripts may place them anywhere. 1430 However, we can't finish the fragment here and emit the reloc as insn 1431 alignment requirements may move the insn about. */ 1432 1433 if (S_GET_SEGMENT (fragP->fr_symbol) != segment) 1434 { 1435 /* The symbol is undefined in this segment. 1436 Change the relaxation subtype to the max allowable and leave 1437 all further handling to md_convert_frag. */ 1438 fragP->fr_subtype = 2; 1439 1440 #if 0 /* Can't use this, but leave in for illustration. */ 1441 /* Change 16 bit insn to 32 bit insn. */ 1442 fragP->fr_opcode[0] |= 0x80; 1443 1444 /* Increase known (fixed) size of fragment. */ 1445 fragP->fr_fix += 2; 1446 1447 /* Create a relocation for it. */ 1448 fix_new (fragP, old_fr_fix, 4, 1449 fragP->fr_symbol, 1450 fragP->fr_offset, 1 /* pcrel */, 1451 /* FIXME: Can't use a real BFD reloc here. 1452 gas_cgen_md_apply_fix3 can't handle it. */ 1453 BFD_RELOC_M32R_26_PCREL); 1454 1455 /* Mark this fragment as finished. */ 1456 frag_wane (fragP); 1457 #else 1458 { 1459 const CGEN_INSN * insn; 1460 int i; 1461 1462 /* Update the recorded insn. 1463 Fortunately we don't have to look very far. 1464 FIXME: Change this to record in the instruction the next higher 1465 relaxable insn to use. */ 1466 for (i = 0, insn = fragP->fr_cgen.insn; i < 4; i++, insn++) 1467 { 1468 if ((strcmp (CGEN_INSN_MNEMONIC (insn), 1469 CGEN_INSN_MNEMONIC (fragP->fr_cgen.insn)) 1470 == 0) 1471 && CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_RELAX)) 1472 break; 1473 } 1474 if (i == 4) 1475 abort (); 1476 1477 fragP->fr_cgen.insn = insn; 1478 return 2; 1479 } 1480 #endif 1481 } 1482 1483 return (fragP->fr_var + fragP->fr_fix - old_fr_fix); 1484 } 1485 1486 /* *fragP has been relaxed to its final size, and now needs to have 1487 the bytes inside it modified to conform to the new size. 1488 1489 Called after relaxation is finished. 1490 fragP->fr_type == rs_machine_dependent. 1491 fragP->fr_subtype is the subtype of what the address relaxed to. */ 1492 1493 void 1494 md_convert_frag (abfd, sec, fragP) 1495 bfd * abfd; 1496 segT sec; 1497 fragS * fragP; 1498 { 1499 char * opcode; 1500 char * displacement; 1501 int target_address; 1502 int opcode_address; 1503 int extension; 1504 int addend; 1505 1506 opcode = fragP->fr_opcode; 1507 1508 /* Address opcode resides at in file space. */ 1509 opcode_address = fragP->fr_address + fragP->fr_fix - 2; 1510 1511 switch (fragP->fr_subtype) 1512 { 1513 case 1 : 1514 extension = 0; 1515 displacement = & opcode[1]; 1516 break; 1517 case 2 : 1518 opcode[0] |= 0x80; 1519 extension = 2; 1520 displacement = & opcode[1]; 1521 break; 1522 case 3 : 1523 opcode[2] = opcode[0] | 0x80; 1524 md_number_to_chars (opcode, PAR_NOP_INSN, 2); 1525 opcode_address += 2; 1526 extension = 4; 1527 displacement = & opcode[3]; 1528 break; 1529 default : 1530 abort (); 1531 } 1532 1533 if (S_GET_SEGMENT (fragP->fr_symbol) != sec) 1534 { 1535 /* symbol must be resolved by linker */ 1536 if (fragP->fr_offset & 3) 1537 as_warn (_("Addend to unresolved symbol not on word boundary.")); 1538 addend = fragP->fr_offset >> 2; 1539 } 1540 else 1541 { 1542 /* Address we want to reach in file space. */ 1543 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset; 1544 target_address += symbol_get_frag (fragP->fr_symbol)->fr_address; 1545 addend = (target_address - (opcode_address & -4)) >> 2; 1546 } 1547 1548 /* Create a relocation for symbols that must be resolved by the linker. 1549 Otherwise output the completed insn. */ 1550 1551 if (S_GET_SEGMENT (fragP->fr_symbol) != sec) 1552 { 1553 assert (fragP->fr_subtype != 1); 1554 assert (fragP->fr_cgen.insn != 0); 1555 gas_cgen_record_fixup (fragP, 1556 /* Offset of branch insn in frag. */ 1557 fragP->fr_fix + extension - 4, 1558 fragP->fr_cgen.insn, 1559 4 /*length*/, 1560 /* FIXME: quick hack */ 1561 #if 0 1562 cgen_operand_lookup_by_num (gas_cgen_cpu_desc, 1563 fragP->fr_cgen.opindex), 1564 #else 1565 cgen_operand_lookup_by_num (gas_cgen_cpu_desc, 1566 M32R_OPERAND_DISP24), 1567 #endif 1568 fragP->fr_cgen.opinfo, 1569 fragP->fr_symbol, fragP->fr_offset); 1570 } 1571 1572 #define SIZE_FROM_RELAX_STATE(n) ((n) == 1 ? 1 : 3) 1573 1574 md_number_to_chars (displacement, (valueT) addend, 1575 SIZE_FROM_RELAX_STATE (fragP->fr_subtype)); 1576 1577 fragP->fr_fix += extension; 1578 } 1579 1580 /* Functions concerning relocs. */ 1581 1582 /* The location from which a PC relative jump should be calculated, 1583 given a PC relative reloc. */ 1584 1585 long 1586 md_pcrel_from_section (fixP, sec) 1587 fixS * fixP; 1588 segT sec; 1589 { 1590 if (fixP->fx_addsy != (symbolS *) NULL 1591 && (! S_IS_DEFINED (fixP->fx_addsy) 1592 || S_GET_SEGMENT (fixP->fx_addsy) != sec)) 1593 { 1594 /* The symbol is undefined (or is defined but not in this section). 1595 Let the linker figure it out. */ 1596 return 0; 1597 } 1598 1599 return (fixP->fx_frag->fr_address + fixP->fx_where) & -4L; 1600 } 1601 1602 /* Return the bfd reloc type for OPERAND of INSN at fixup FIXP. 1603 Returns BFD_RELOC_NONE if no reloc type can be found. 1604 *FIXP may be modified if desired. */ 1605 1606 bfd_reloc_code_real_type 1607 md_cgen_lookup_reloc (insn, operand, fixP) 1608 const CGEN_INSN * insn; 1609 const CGEN_OPERAND * operand; 1610 fixS * fixP; 1611 { 1612 switch (operand->type) 1613 { 1614 case M32R_OPERAND_DISP8 : return BFD_RELOC_M32R_10_PCREL; 1615 case M32R_OPERAND_DISP16 : return BFD_RELOC_M32R_18_PCREL; 1616 case M32R_OPERAND_DISP24 : return BFD_RELOC_M32R_26_PCREL; 1617 case M32R_OPERAND_UIMM24 : return BFD_RELOC_M32R_24; 1618 case M32R_OPERAND_HI16 : 1619 case M32R_OPERAND_SLO16 : 1620 case M32R_OPERAND_ULO16 : 1621 /* If low/high/shigh/sda was used, it is recorded in `opinfo'. */ 1622 if (fixP->fx_cgen.opinfo != 0) 1623 return fixP->fx_cgen.opinfo; 1624 break; 1625 default : /* avoid -Wall warning */ 1626 break; 1627 } 1628 return BFD_RELOC_NONE; 1629 } 1630 1631 /* Record a HI16 reloc for later matching with its LO16 cousin. */ 1632 1633 static void 1634 m32r_record_hi16 (reloc_type, fixP, seg) 1635 int reloc_type; 1636 fixS * fixP; 1637 segT seg; 1638 { 1639 struct m32r_hi_fixup * hi_fixup; 1640 1641 assert (reloc_type == BFD_RELOC_M32R_HI16_SLO 1642 || reloc_type == BFD_RELOC_M32R_HI16_ULO); 1643 1644 hi_fixup = ((struct m32r_hi_fixup *) 1645 xmalloc (sizeof (struct m32r_hi_fixup))); 1646 hi_fixup->fixp = fixP; 1647 hi_fixup->seg = now_seg; 1648 hi_fixup->next = m32r_hi_fixup_list; 1649 1650 m32r_hi_fixup_list = hi_fixup; 1651 } 1652 1653 /* Called while parsing an instruction to create a fixup. 1654 We need to check for HI16 relocs and queue them up for later sorting. */ 1655 1656 fixS * 1657 m32r_cgen_record_fixup_exp (frag, where, insn, length, operand, opinfo, exp) 1658 fragS * frag; 1659 int where; 1660 const CGEN_INSN * insn; 1661 int length; 1662 const CGEN_OPERAND * operand; 1663 int opinfo; 1664 expressionS * exp; 1665 { 1666 fixS * fixP = gas_cgen_record_fixup_exp (frag, where, insn, length, 1667 operand, opinfo, exp); 1668 1669 switch (operand->type) 1670 { 1671 case M32R_OPERAND_HI16 : 1672 /* If low/high/shigh/sda was used, it is recorded in `opinfo'. */ 1673 if (fixP->fx_cgen.opinfo == BFD_RELOC_M32R_HI16_SLO 1674 || fixP->fx_cgen.opinfo == BFD_RELOC_M32R_HI16_ULO) 1675 m32r_record_hi16 (fixP->fx_cgen.opinfo, fixP, now_seg); 1676 break; 1677 default : /* avoid -Wall warning */ 1678 break; 1679 } 1680 1681 return fixP; 1682 } 1683 1684 /* Return BFD reloc type from opinfo field in a fixS. 1685 It's tricky using fx_r_type in m32r_frob_file because the values 1686 are BFD_RELOC_UNUSED + operand number. */ 1687 #define FX_OPINFO_R_TYPE(f) ((f)->fx_cgen.opinfo) 1688 1689 /* Sort any unmatched HI16 relocs so that they immediately precede 1690 the corresponding LO16 reloc. This is called before md_apply_fix and 1691 tc_gen_reloc. */ 1692 1693 void 1694 m32r_frob_file () 1695 { 1696 struct m32r_hi_fixup * l; 1697 1698 for (l = m32r_hi_fixup_list; l != NULL; l = l->next) 1699 { 1700 segment_info_type * seginfo; 1701 int pass; 1702 1703 assert (FX_OPINFO_R_TYPE (l->fixp) == BFD_RELOC_M32R_HI16_SLO 1704 || FX_OPINFO_R_TYPE (l->fixp) == BFD_RELOC_M32R_HI16_ULO); 1705 1706 /* Check quickly whether the next fixup happens to be a matching low. */ 1707 if (l->fixp->fx_next != NULL 1708 && FX_OPINFO_R_TYPE (l->fixp->fx_next) == BFD_RELOC_M32R_LO16 1709 && l->fixp->fx_addsy == l->fixp->fx_next->fx_addsy 1710 && l->fixp->fx_offset == l->fixp->fx_next->fx_offset) 1711 continue; 1712 1713 /* Look through the fixups for this segment for a matching `low'. 1714 When we find one, move the high/shigh just in front of it. We do 1715 this in two passes. In the first pass, we try to find a 1716 unique `low'. In the second pass, we permit multiple high's 1717 relocs for a single `low'. */ 1718 seginfo = seg_info (l->seg); 1719 for (pass = 0; pass < 2; pass++) 1720 { 1721 fixS * f; 1722 fixS * prev; 1723 1724 prev = NULL; 1725 for (f = seginfo->fix_root; f != NULL; f = f->fx_next) 1726 { 1727 /* Check whether this is a `low' fixup which matches l->fixp. */ 1728 if (FX_OPINFO_R_TYPE (f) == BFD_RELOC_M32R_LO16 1729 && f->fx_addsy == l->fixp->fx_addsy 1730 && f->fx_offset == l->fixp->fx_offset 1731 && (pass == 1 1732 || prev == NULL 1733 || (FX_OPINFO_R_TYPE (prev) != BFD_RELOC_M32R_HI16_SLO 1734 && FX_OPINFO_R_TYPE (prev) != BFD_RELOC_M32R_HI16_ULO) 1735 || prev->fx_addsy != f->fx_addsy 1736 || prev->fx_offset != f->fx_offset)) 1737 { 1738 fixS ** pf; 1739 1740 /* Move l->fixp before f. */ 1741 for (pf = &seginfo->fix_root; 1742 * pf != l->fixp; 1743 pf = & (* pf)->fx_next) 1744 assert (* pf != NULL); 1745 1746 * pf = l->fixp->fx_next; 1747 1748 l->fixp->fx_next = f; 1749 if (prev == NULL) 1750 seginfo->fix_root = l->fixp; 1751 else 1752 prev->fx_next = l->fixp; 1753 1754 break; 1755 } 1756 1757 prev = f; 1758 } 1759 1760 if (f != NULL) 1761 break; 1762 1763 if (pass == 1 1764 && warn_unmatched_high) 1765 as_warn_where (l->fixp->fx_file, l->fixp->fx_line, 1766 _("Unmatched high/shigh reloc")); 1767 } 1768 } 1769 } 1770 1771 /* See whether we need to force a relocation into the output file. 1772 This is used to force out switch and PC relative relocations when 1773 relaxing. */ 1774 1775 int 1776 m32r_force_relocation (fix) 1777 fixS * fix; 1778 { 1779 if (fix->fx_r_type == BFD_RELOC_VTABLE_INHERIT 1780 || fix->fx_r_type == BFD_RELOC_VTABLE_ENTRY) 1781 return 1; 1782 1783 if (! m32r_relax) 1784 return 0; 1785 1786 return (fix->fx_pcrel 1787 || 0 /* ??? */); 1788 } 1789 1790 /* Write a value out to the object file, using the appropriate endianness. */ 1791 1792 void 1793 md_number_to_chars (buf, val, n) 1794 char * buf; 1795 valueT val; 1796 int n; 1797 { 1798 if (target_big_endian) 1799 number_to_chars_bigendian (buf, val, n); 1800 else 1801 number_to_chars_littleendian (buf, val, n); 1802 } 1803 1804 /* Turn a string in input_line_pointer into a floating point constant of type 1805 type, and store the appropriate bytes in *litP. The number of LITTLENUMS 1806 emitted is stored in *sizeP . An error message is returned, or NULL on OK. 1807 */ 1808 1809 /* Equal to MAX_PRECISION in atof-ieee.c */ 1810 #define MAX_LITTLENUMS 6 1811 1812 char * 1813 md_atof (type, litP, sizeP) 1814 char type; 1815 char *litP; 1816 int *sizeP; 1817 { 1818 int i; 1819 int prec; 1820 LITTLENUM_TYPE words [MAX_LITTLENUMS]; 1821 char * t; 1822 char * atof_ieee (); 1823 1824 switch (type) 1825 { 1826 case 'f': 1827 case 'F': 1828 case 's': 1829 case 'S': 1830 prec = 2; 1831 break; 1832 1833 case 'd': 1834 case 'D': 1835 case 'r': 1836 case 'R': 1837 prec = 4; 1838 break; 1839 1840 /* FIXME: Some targets allow other format chars for bigger sizes here. */ 1841 1842 default: 1843 * sizeP = 0; 1844 return _("Bad call to md_atof()"); 1845 } 1846 1847 t = atof_ieee (input_line_pointer, type, words); 1848 if (t) 1849 input_line_pointer = t; 1850 * sizeP = prec * sizeof (LITTLENUM_TYPE); 1851 1852 if (target_big_endian) 1853 { 1854 for (i = 0; i < prec; i++) 1855 { 1856 md_number_to_chars (litP, (valueT) words[i], 1857 sizeof (LITTLENUM_TYPE)); 1858 litP += sizeof (LITTLENUM_TYPE); 1859 } 1860 } 1861 else 1862 { 1863 for (i = prec - 1; i >= 0; i--) 1864 { 1865 md_number_to_chars (litP, (valueT) words[i], 1866 sizeof (LITTLENUM_TYPE)); 1867 litP += sizeof (LITTLENUM_TYPE); 1868 } 1869 } 1870 1871 return 0; 1872 } 1873 1874 void 1875 m32r_elf_section_change_hook () 1876 { 1877 /* If we have reached the end of a section and we have just emitted a 1878 16 bit insn, then emit a nop to make sure that the section ends on 1879 a 32 bit boundary. */ 1880 1881 if (prev_insn.insn || seen_relaxable_p) 1882 (void) m32r_fill_insn (0); 1883 } 1884 1885 boolean 1886 m32r_fix_adjustable (fixP) 1887 fixS *fixP; 1888 { 1889 1890 bfd_reloc_code_real_type reloc_type; 1891 1892 if ((int) fixP->fx_r_type >= (int) BFD_RELOC_UNUSED) 1893 { 1894 const CGEN_INSN *insn = NULL; 1895 int opindex = (int) fixP->fx_r_type - (int) BFD_RELOC_UNUSED; 1896 const CGEN_OPERAND *operand = cgen_operand_lookup_by_num(gas_cgen_cpu_desc, opindex); 1897 reloc_type = md_cgen_lookup_reloc (insn, operand, fixP); 1898 } 1899 else 1900 reloc_type = fixP->fx_r_type; 1901 1902 if (fixP->fx_addsy == NULL) 1903 return 1; 1904 1905 /* Prevent all adjustments to global symbols. */ 1906 if (S_IS_EXTERN (fixP->fx_addsy)) 1907 return 0; 1908 if (S_IS_WEAK (fixP->fx_addsy)) 1909 return 0; 1910 1911 /* We need the symbol name for the VTABLE entries */ 1912 if (reloc_type == BFD_RELOC_VTABLE_INHERIT 1913 || reloc_type == BFD_RELOC_VTABLE_ENTRY) 1914 return 0; 1915 1916 return 1; 1917 } 1918