1*3d8817e4Smiod /* s390-opc.c -- S390 opcode list 2*3d8817e4Smiod Copyright 2000, 2001, 2003 Free Software Foundation, Inc. 3*3d8817e4Smiod Contributed by Martin Schwidefsky (schwidefsky@de.ibm.com). 4*3d8817e4Smiod 5*3d8817e4Smiod This file is part of GDB, GAS, and the GNU binutils. 6*3d8817e4Smiod 7*3d8817e4Smiod This program is free software; you can redistribute it and/or modify 8*3d8817e4Smiod it under the terms of the GNU General Public License as published by 9*3d8817e4Smiod the Free Software Foundation; either version 2 of the License, or 10*3d8817e4Smiod (at your option) any later version. 11*3d8817e4Smiod 12*3d8817e4Smiod This program is distributed in the hope that it will be useful, 13*3d8817e4Smiod but WITHOUT ANY WARRANTY; without even the implied warranty of 14*3d8817e4Smiod MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15*3d8817e4Smiod GNU General Public License for more details. 16*3d8817e4Smiod 17*3d8817e4Smiod You should have received a copy of the GNU General Public License 18*3d8817e4Smiod along with this program; if not, write to the Free Software 19*3d8817e4Smiod Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 20*3d8817e4Smiod 02110-1301, USA. */ 21*3d8817e4Smiod 22*3d8817e4Smiod #include <stdio.h> 23*3d8817e4Smiod #include "ansidecl.h" 24*3d8817e4Smiod #include "opcode/s390.h" 25*3d8817e4Smiod 26*3d8817e4Smiod /* This file holds the S390 opcode table. The opcode table 27*3d8817e4Smiod includes almost all of the extended instruction mnemonics. This 28*3d8817e4Smiod permits the disassembler to use them, and simplifies the assembler 29*3d8817e4Smiod logic, at the cost of increasing the table size. The table is 30*3d8817e4Smiod strictly constant data, so the compiler should be able to put it in 31*3d8817e4Smiod the .text section. 32*3d8817e4Smiod 33*3d8817e4Smiod This file also holds the operand table. All knowledge about 34*3d8817e4Smiod inserting operands into instructions and vice-versa is kept in this 35*3d8817e4Smiod file. */ 36*3d8817e4Smiod 37*3d8817e4Smiod /* The operands table. 38*3d8817e4Smiod The fields are bits, shift, insert, extract, flags. */ 39*3d8817e4Smiod 40*3d8817e4Smiod const struct s390_operand s390_operands[] = 41*3d8817e4Smiod { 42*3d8817e4Smiod #define UNUSED 0 43*3d8817e4Smiod { 0, 0, 0 }, /* Indicates the end of the operand list */ 44*3d8817e4Smiod 45*3d8817e4Smiod #define R_8 1 /* GPR starting at position 8 */ 46*3d8817e4Smiod { 4, 8, S390_OPERAND_GPR }, 47*3d8817e4Smiod #define R_12 2 /* GPR starting at position 12 */ 48*3d8817e4Smiod { 4, 12, S390_OPERAND_GPR }, 49*3d8817e4Smiod #define R_16 3 /* GPR starting at position 16 */ 50*3d8817e4Smiod { 4, 16, S390_OPERAND_GPR }, 51*3d8817e4Smiod #define R_20 4 /* GPR starting at position 20 */ 52*3d8817e4Smiod { 4, 20, S390_OPERAND_GPR }, 53*3d8817e4Smiod #define R_24 5 /* GPR starting at position 24 */ 54*3d8817e4Smiod { 4, 24, S390_OPERAND_GPR }, 55*3d8817e4Smiod #define R_28 6 /* GPR starting at position 28 */ 56*3d8817e4Smiod { 4, 28, S390_OPERAND_GPR }, 57*3d8817e4Smiod #define R_32 7 /* GPR starting at position 32 */ 58*3d8817e4Smiod { 4, 32, S390_OPERAND_GPR }, 59*3d8817e4Smiod 60*3d8817e4Smiod #define F_8 8 /* FPR starting at position 8 */ 61*3d8817e4Smiod { 4, 8, S390_OPERAND_FPR }, 62*3d8817e4Smiod #define F_12 9 /* FPR starting at position 12 */ 63*3d8817e4Smiod { 4, 12, S390_OPERAND_FPR }, 64*3d8817e4Smiod #define F_16 10 /* FPR starting at position 16 */ 65*3d8817e4Smiod { 4, 16, S390_OPERAND_FPR }, 66*3d8817e4Smiod #define F_20 11 /* FPR starting at position 16 */ 67*3d8817e4Smiod { 4, 16, S390_OPERAND_FPR }, 68*3d8817e4Smiod #define F_24 12 /* FPR starting at position 24 */ 69*3d8817e4Smiod { 4, 24, S390_OPERAND_FPR }, 70*3d8817e4Smiod #define F_28 13 /* FPR starting at position 28 */ 71*3d8817e4Smiod { 4, 28, S390_OPERAND_FPR }, 72*3d8817e4Smiod #define F_32 14 /* FPR starting at position 32 */ 73*3d8817e4Smiod { 4, 32, S390_OPERAND_FPR }, 74*3d8817e4Smiod 75*3d8817e4Smiod #define A_8 15 /* Access reg. starting at position 8 */ 76*3d8817e4Smiod { 4, 8, S390_OPERAND_AR }, 77*3d8817e4Smiod #define A_12 16 /* Access reg. starting at position 12 */ 78*3d8817e4Smiod { 4, 12, S390_OPERAND_AR }, 79*3d8817e4Smiod #define A_24 17 /* Access reg. starting at position 24 */ 80*3d8817e4Smiod { 4, 24, S390_OPERAND_AR }, 81*3d8817e4Smiod #define A_28 18 /* Access reg. starting at position 28 */ 82*3d8817e4Smiod { 4, 28, S390_OPERAND_AR }, 83*3d8817e4Smiod 84*3d8817e4Smiod #define C_8 19 /* Control reg. starting at position 8 */ 85*3d8817e4Smiod { 4, 8, S390_OPERAND_CR }, 86*3d8817e4Smiod #define C_12 20 /* Control reg. starting at position 12 */ 87*3d8817e4Smiod { 4, 12, S390_OPERAND_CR }, 88*3d8817e4Smiod 89*3d8817e4Smiod #define B_16 21 /* Base register starting at position 16 */ 90*3d8817e4Smiod { 4, 16, S390_OPERAND_BASE|S390_OPERAND_GPR }, 91*3d8817e4Smiod #define B_32 22 /* Base register starting at position 32 */ 92*3d8817e4Smiod { 4, 32, S390_OPERAND_BASE|S390_OPERAND_GPR }, 93*3d8817e4Smiod 94*3d8817e4Smiod #define X_12 23 /* Index register starting at position 12 */ 95*3d8817e4Smiod { 4, 12, S390_OPERAND_INDEX|S390_OPERAND_GPR }, 96*3d8817e4Smiod 97*3d8817e4Smiod #define D_20 24 /* Displacement starting at position 20 */ 98*3d8817e4Smiod { 12, 20, S390_OPERAND_DISP }, 99*3d8817e4Smiod #define D_36 25 /* Displacement starting at position 36 */ 100*3d8817e4Smiod { 12, 36, S390_OPERAND_DISP }, 101*3d8817e4Smiod #define D20_20 26 /* 20 bit displacement starting at 20 */ 102*3d8817e4Smiod { 20, 20, S390_OPERAND_DISP|S390_OPERAND_SIGNED }, 103*3d8817e4Smiod 104*3d8817e4Smiod #define L4_8 27 /* 4 bit length starting at position 8 */ 105*3d8817e4Smiod { 4, 8, S390_OPERAND_LENGTH }, 106*3d8817e4Smiod #define L4_12 28 /* 4 bit length starting at position 12 */ 107*3d8817e4Smiod { 4, 12, S390_OPERAND_LENGTH }, 108*3d8817e4Smiod #define L8_8 29 /* 8 bit length starting at position 8 */ 109*3d8817e4Smiod { 8, 8, S390_OPERAND_LENGTH }, 110*3d8817e4Smiod 111*3d8817e4Smiod #define U4_8 30 /* 4 bit unsigned value starting at 8 */ 112*3d8817e4Smiod { 4, 8, 0 }, 113*3d8817e4Smiod #define U4_12 31 /* 4 bit unsigned value starting at 12 */ 114*3d8817e4Smiod { 4, 12, 0 }, 115*3d8817e4Smiod #define U4_16 32 /* 4 bit unsigned value starting at 16 */ 116*3d8817e4Smiod { 4, 16, 0 }, 117*3d8817e4Smiod #define U4_20 33 /* 4 bit unsigned value starting at 20 */ 118*3d8817e4Smiod { 4, 20, 0 }, 119*3d8817e4Smiod #define U8_8 34 /* 8 bit unsigned value starting at 8 */ 120*3d8817e4Smiod { 8, 8, 0 }, 121*3d8817e4Smiod #define U8_16 35 /* 8 bit unsigned value starting at 16 */ 122*3d8817e4Smiod { 8, 16, 0 }, 123*3d8817e4Smiod #define I16_16 36 /* 16 bit signed value starting at 16 */ 124*3d8817e4Smiod { 16, 16, S390_OPERAND_SIGNED }, 125*3d8817e4Smiod #define U16_16 37 /* 16 bit unsigned value starting at 16 */ 126*3d8817e4Smiod { 16, 16, 0 }, 127*3d8817e4Smiod #define J16_16 38 /* PC relative jump offset at 16 */ 128*3d8817e4Smiod { 16, 16, S390_OPERAND_PCREL }, 129*3d8817e4Smiod #define J32_16 39 /* PC relative long offset at 16 */ 130*3d8817e4Smiod { 32, 16, S390_OPERAND_PCREL }, 131*3d8817e4Smiod #define I32_16 40 /* 32 bit signed value starting at 16 */ 132*3d8817e4Smiod { 32, 16, S390_OPERAND_SIGNED }, 133*3d8817e4Smiod #define U32_16 41 /* 32 bit unsigned value starting at 16 */ 134*3d8817e4Smiod { 32, 16, 0 }, 135*3d8817e4Smiod #define M_16 42 /* 4 bit optional mask starting at 16 */ 136*3d8817e4Smiod { 4, 16, S390_OPERAND_OPTIONAL } 137*3d8817e4Smiod }; 138*3d8817e4Smiod 139*3d8817e4Smiod 140*3d8817e4Smiod /* Macros used to form opcodes. */ 141*3d8817e4Smiod 142*3d8817e4Smiod /* 8/16/48 bit opcodes. */ 143*3d8817e4Smiod #define OP8(x) { x, 0x00, 0x00, 0x00, 0x00, 0x00 } 144*3d8817e4Smiod #define OP16(x) { x >> 8, x & 255, 0x00, 0x00, 0x00, 0x00 } 145*3d8817e4Smiod #define OP48(x) { x >> 40, (x >> 32) & 255, (x >> 24) & 255, \ 146*3d8817e4Smiod (x >> 16) & 255, (x >> 8) & 255, x & 255} 147*3d8817e4Smiod 148*3d8817e4Smiod /* The new format of the INSTR_x_y and MASK_x_y defines is based 149*3d8817e4Smiod on the following rules: 150*3d8817e4Smiod 1) the middle part of the definition (x in INSTR_x_y) is the official 151*3d8817e4Smiod names of the instruction format that you can find in the principals 152*3d8817e4Smiod of operation. 153*3d8817e4Smiod 2) the last part of the definition (y in INSTR_x_y) gives you an idea 154*3d8817e4Smiod which operands the binary represenation of the instruction has. 155*3d8817e4Smiod The meanings of the letters in y are: 156*3d8817e4Smiod a - access register 157*3d8817e4Smiod c - control register 158*3d8817e4Smiod d - displacement, 12 bit 159*3d8817e4Smiod f - floating pointer register 160*3d8817e4Smiod i - signed integer, 4, 8, 16 or 32 bit 161*3d8817e4Smiod l - length, 4 or 8 bit 162*3d8817e4Smiod p - pc relative 163*3d8817e4Smiod r - general purpose register 164*3d8817e4Smiod u - unsigned integer, 4, 8, 16 or 32 bit 165*3d8817e4Smiod m - mode field, 4 bit 166*3d8817e4Smiod 0 - operand skipped. 167*3d8817e4Smiod The order of the letters reflects the layout of the format in 168*3d8817e4Smiod storage and not the order of the paramaters of the instructions. 169*3d8817e4Smiod The use of the letters is not a 100% match with the PoP but it is 170*3d8817e4Smiod quite close. 171*3d8817e4Smiod 172*3d8817e4Smiod For example the instruction "mvo" is defined in the PoP as follows: 173*3d8817e4Smiod 174*3d8817e4Smiod MVO D1(L1,B1),D2(L2,B2) [SS] 175*3d8817e4Smiod 176*3d8817e4Smiod -------------------------------------- 177*3d8817e4Smiod | 'F1' | L1 | L2 | B1 | D1 | B2 | D2 | 178*3d8817e4Smiod -------------------------------------- 179*3d8817e4Smiod 0 8 12 16 20 32 36 180*3d8817e4Smiod 181*3d8817e4Smiod The instruction format is: INSTR_SS_LLRDRD / MASK_SS_LLRDRD. */ 182*3d8817e4Smiod 183*3d8817e4Smiod #define INSTR_E 2, { 0,0,0,0,0,0 } /* e.g. pr */ 184*3d8817e4Smiod #define INSTR_RIE_RRP 6, { R_8,R_12,J16_16,0,0,0 } /* e.g. brxhg */ 185*3d8817e4Smiod #define INSTR_RIL_0P 6, { J32_16,0,0,0,0 } /* e.g. jg */ 186*3d8817e4Smiod #define INSTR_RIL_RP 6, { R_8,J32_16,0,0,0,0 } /* e.g. brasl */ 187*3d8817e4Smiod #define INSTR_RIL_UP 6, { U4_8,J32_16,0,0,0,0 } /* e.g. brcl */ 188*3d8817e4Smiod #define INSTR_RIL_RI 6, { R_8,I32_16,0,0,0,0 } /* e.g. afi */ 189*3d8817e4Smiod #define INSTR_RIL_RU 6, { R_8,U32_16,0,0,0,0 } /* e.g. alfi */ 190*3d8817e4Smiod #define INSTR_RI_0P 4, { J16_16,0,0,0,0,0 } /* e.g. j */ 191*3d8817e4Smiod #define INSTR_RI_RI 4, { R_8,I16_16,0,0,0,0 } /* e.g. ahi */ 192*3d8817e4Smiod #define INSTR_RI_RP 4, { R_8,J16_16,0,0,0,0 } /* e.g. brct */ 193*3d8817e4Smiod #define INSTR_RI_RU 4, { R_8,U16_16,0,0,0,0 } /* e.g. tml */ 194*3d8817e4Smiod #define INSTR_RI_UP 4, { U4_8,J16_16,0,0,0,0 } /* e.g. brc */ 195*3d8817e4Smiod #define INSTR_RRE_00 4, { 0,0,0,0,0,0 } /* e.g. palb */ 196*3d8817e4Smiod #define INSTR_RRE_0R 4, { R_28,0,0,0,0,0 } /* e.g. tb */ 197*3d8817e4Smiod #define INSTR_RRE_AA 4, { A_24,A_28,0,0,0,0 } /* e.g. cpya */ 198*3d8817e4Smiod #define INSTR_RRE_AR 4, { A_24,R_28,0,0,0,0 } /* e.g. sar */ 199*3d8817e4Smiod #define INSTR_RRE_F0 4, { F_24,0,0,0,0,0 } /* e.g. sqer */ 200*3d8817e4Smiod #define INSTR_RRE_FF 4, { F_24,F_28,0,0,0,0 } /* e.g. debr */ 201*3d8817e4Smiod #define INSTR_RRE_R0 4, { R_24,0,0,0,0,0 } /* e.g. ipm */ 202*3d8817e4Smiod #define INSTR_RRE_RA 4, { R_24,A_28,0,0,0,0 } /* e.g. ear */ 203*3d8817e4Smiod #define INSTR_RRE_RF 4, { R_24,F_28,0,0,0,0 } /* e.g. cefbr */ 204*3d8817e4Smiod #define INSTR_RRE_RR 4, { R_24,R_28,0,0,0,0 } /* e.g. lura */ 205*3d8817e4Smiod #define INSTR_RRF_F0FF 4, { F_16,F_24,F_28,0,0,0 } /* e.g. madbr */ 206*3d8817e4Smiod #define INSTR_RRF_FUFF 4, { F_24,F_16,F_28,U4_20,0,0 } /* e.g. didbr */ 207*3d8817e4Smiod #define INSTR_RRF_RURR 4, { R_24,R_28,R_16,U4_20,0,0 } /* e.g. .insn */ 208*3d8817e4Smiod #define INSTR_RRF_R0RR 4, { R_24,R_28,R_16,0,0,0 } /* e.g. idte */ 209*3d8817e4Smiod #define INSTR_RRF_U0FF 4, { F_24,U4_16,F_28,0,0,0 } /* e.g. cfxbr */ 210*3d8817e4Smiod #define INSTR_RRF_U0FR 4, { F_24,U4_16,R_28,0,0,0 } /* e.g. cfebr */ 211*3d8817e4Smiod #define INSTR_RRF_U0FR 4, { F_24,U4_16,R_28,0,0,0 } /* e.g. cfxbr */ 212*3d8817e4Smiod #define INSTR_RRF_M0RR 4, { R_24,R_28,M_16,0,0,0 } /* e.g. sske */ 213*3d8817e4Smiod #define INSTR_RR_0R 2, { R_12, 0,0,0,0,0 } /* e.g. br */ 214*3d8817e4Smiod #define INSTR_RR_FF 2, { F_8,F_12,0,0,0,0 } /* e.g. adr */ 215*3d8817e4Smiod #define INSTR_RR_R0 2, { R_8, 0,0,0,0,0 } /* e.g. spm */ 216*3d8817e4Smiod #define INSTR_RR_RR 2, { R_8,R_12,0,0,0,0 } /* e.g. lr */ 217*3d8817e4Smiod #define INSTR_RR_U0 2, { U8_8, 0,0,0,0,0 } /* e.g. svc */ 218*3d8817e4Smiod #define INSTR_RR_UR 2, { U4_8,R_12,0,0,0,0 } /* e.g. bcr */ 219*3d8817e4Smiod #define INSTR_RSE_RRRD 6, { R_8,R_12,D_20,B_16,0,0 } /* e.g. lmh */ 220*3d8817e4Smiod #define INSTR_RSE_CCRD 6, { C_8,C_12,D_20,B_16,0,0 } /* e.g. lmh */ 221*3d8817e4Smiod #define INSTR_RSE_RURD 6, { R_8,U4_12,D_20,B_16,0,0 } /* e.g. icmh */ 222*3d8817e4Smiod #define INSTR_RSL_R0RD 6, { R_8,D_20,B_16,0,0,0 } /* e.g. tp */ 223*3d8817e4Smiod #define INSTR_RSI_RRP 4, { R_8,R_12,J16_16,0,0,0 } /* e.g. brxh */ 224*3d8817e4Smiod #define INSTR_RSY_RRRD 6, { R_8,R_12,D20_20,B_16,0,0 } /* e.g. stmy */ 225*3d8817e4Smiod #define INSTR_RSY_RURD 6, { R_8,U4_12,D20_20,B_16,0,0 } /* e.g. icmh */ 226*3d8817e4Smiod #define INSTR_RSY_AARD 6, { A_8,A_12,D20_20,B_16,0,0 } /* e.g. lamy */ 227*3d8817e4Smiod #define INSTR_RSY_CCRD 6, { C_8,C_12,D20_20,B_16,0,0 } /* e.g. lamy */ 228*3d8817e4Smiod #define INSTR_RS_AARD 4, { A_8,A_12,D_20,B_16,0,0 } /* e.g. lam */ 229*3d8817e4Smiod #define INSTR_RS_CCRD 4, { C_8,C_12,D_20,B_16,0,0 } /* e.g. lctl */ 230*3d8817e4Smiod #define INSTR_RS_R0RD 4, { R_8,D_20,B_16,0,0,0 } /* e.g. sll */ 231*3d8817e4Smiod #define INSTR_RS_RRRD 4, { R_8,R_12,D_20,B_16,0,0 } /* e.g. cs */ 232*3d8817e4Smiod #define INSTR_RS_RURD 4, { R_8,U4_12,D_20,B_16,0,0 } /* e.g. icm */ 233*3d8817e4Smiod #define INSTR_RXE_FRRD 6, { F_8,D_20,X_12,B_16,0,0 } /* e.g. axbr */ 234*3d8817e4Smiod #define INSTR_RXE_RRRD 6, { R_8,D_20,X_12,B_16,0,0 } /* e.g. lg */ 235*3d8817e4Smiod #define INSTR_RXF_FRRDF 6, { F_32,F_8,D_20,X_12,B_16,0 } /* e.g. madb */ 236*3d8817e4Smiod #define INSTR_RXF_RRRDR 6, { R_32,R_8,D_20,X_12,B_16,0 } /* e.g. .insn */ 237*3d8817e4Smiod #define INSTR_RXY_RRRD 6, { R_8,D20_20,X_12,B_16,0,0 } /* e.g. ly */ 238*3d8817e4Smiod #define INSTR_RXY_FRRD 6, { F_8,D20_20,X_12,B_16,0,0 } /* e.g. ley */ 239*3d8817e4Smiod #define INSTR_RX_0RRD 4, { D_20,X_12,B_16,0,0,0 } /* e.g. be */ 240*3d8817e4Smiod #define INSTR_RX_FRRD 4, { F_8,D_20,X_12,B_16,0,0 } /* e.g. ae */ 241*3d8817e4Smiod #define INSTR_RX_RRRD 4, { R_8,D_20,X_12,B_16,0,0 } /* e.g. l */ 242*3d8817e4Smiod #define INSTR_RX_URRD 4, { U4_8,D_20,X_12,B_16,0,0 } /* e.g. bc */ 243*3d8817e4Smiod #define INSTR_SI_URD 4, { D_20,B_16,U8_8,0,0,0 } /* e.g. cli */ 244*3d8817e4Smiod #define INSTR_SIY_URD 6, { D20_20,B_16,U8_8,0,0,0 } /* e.g. tmy */ 245*3d8817e4Smiod #define INSTR_SSE_RDRD 6, { D_20,B_16,D_36,B_32,0,0 } /* e.g. mvsdk */ 246*3d8817e4Smiod #define INSTR_SS_L0RDRD 6, { D_20,L8_8,B_16,D_36,B_32,0 } /* e.g. mvc */ 247*3d8817e4Smiod #define INSTR_SS_LIRDRD 6, { D_20,L4_8,B_16,D_36,B_32,U4_12 } /* e.g. srp */ 248*3d8817e4Smiod #define INSTR_SS_LLRDRD 6, { D_20,L4_8,B_16,D_36,L4_12,B_32 } /* e.g. pack */ 249*3d8817e4Smiod #define INSTR_SS_RRRDRD 6, { D_20,R_8,B_16,D_36,B_32,R_12 } /* e.g. mvck */ 250*3d8817e4Smiod #define INSTR_SS_RRRDRD2 6, { R_8,D_20,B_16,R_12,D_36,B_32 } /* e.g. plo */ 251*3d8817e4Smiod #define INSTR_SS_RRRDRD3 6, { R_8,R_12,D_20,B_16,D_36,B_32 } /* e.g. lmd */ 252*3d8817e4Smiod #define INSTR_S_00 4, { 0,0,0,0,0,0 } /* e.g. hsch */ 253*3d8817e4Smiod #define INSTR_S_RD 4, { D_20,B_16,0,0,0,0 } /* e.g. lpsw */ 254*3d8817e4Smiod #define INSTR_SSF_RRDRD 6, { D_20,B_16,D_36,B_32,R_8,0 } /* e.g. mvcos */ 255*3d8817e4Smiod 256*3d8817e4Smiod #define MASK_E { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } 257*3d8817e4Smiod #define MASK_RIE_RRP { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } 258*3d8817e4Smiod #define MASK_RIL_0P { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } 259*3d8817e4Smiod #define MASK_RIL_RP { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } 260*3d8817e4Smiod #define MASK_RIL_UP { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } 261*3d8817e4Smiod #define MASK_RIL_RI { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } 262*3d8817e4Smiod #define MASK_RIL_RU { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } 263*3d8817e4Smiod #define MASK_RI_0P { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } 264*3d8817e4Smiod #define MASK_RI_RI { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } 265*3d8817e4Smiod #define MASK_RI_RP { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } 266*3d8817e4Smiod #define MASK_RI_RU { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } 267*3d8817e4Smiod #define MASK_RI_UP { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } 268*3d8817e4Smiod #define MASK_RRE_00 { 0xff, 0xff, 0xff, 0xff, 0x00, 0x00 } 269*3d8817e4Smiod #define MASK_RRE_0R { 0xff, 0xff, 0xff, 0xf0, 0x00, 0x00 } 270*3d8817e4Smiod #define MASK_RRE_AA { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } 271*3d8817e4Smiod #define MASK_RRE_AR { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } 272*3d8817e4Smiod #define MASK_RRE_F0 { 0xff, 0xff, 0xff, 0x0f, 0x00, 0x00 } 273*3d8817e4Smiod #define MASK_RRE_FF { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } 274*3d8817e4Smiod #define MASK_RRE_R0 { 0xff, 0xff, 0xff, 0x0f, 0x00, 0x00 } 275*3d8817e4Smiod #define MASK_RRE_RA { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } 276*3d8817e4Smiod #define MASK_RRE_RF { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } 277*3d8817e4Smiod #define MASK_RRE_RR { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } 278*3d8817e4Smiod #define MASK_RRF_F0FF { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } 279*3d8817e4Smiod #define MASK_RRF_FUFF { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } 280*3d8817e4Smiod #define MASK_RRF_RURR { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } 281*3d8817e4Smiod #define MASK_RRF_R0RR { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } 282*3d8817e4Smiod #define MASK_RRF_U0FF { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } 283*3d8817e4Smiod #define MASK_RRF_U0FR { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } 284*3d8817e4Smiod #define MASK_RRF_U0FR { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } 285*3d8817e4Smiod #define MASK_RRF_M0RR { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } 286*3d8817e4Smiod #define MASK_RR_0R { 0xff, 0xf0, 0x00, 0x00, 0x00, 0x00 } 287*3d8817e4Smiod #define MASK_RR_FF { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } 288*3d8817e4Smiod #define MASK_RR_R0 { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } 289*3d8817e4Smiod #define MASK_RR_RR { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } 290*3d8817e4Smiod #define MASK_RR_U0 { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } 291*3d8817e4Smiod #define MASK_RR_UR { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } 292*3d8817e4Smiod #define MASK_RSE_RRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } 293*3d8817e4Smiod #define MASK_RSE_CCRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } 294*3d8817e4Smiod #define MASK_RSE_RURD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } 295*3d8817e4Smiod #define MASK_RSL_R0RD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } 296*3d8817e4Smiod #define MASK_RSI_RRP { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } 297*3d8817e4Smiod #define MASK_RS_AARD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } 298*3d8817e4Smiod #define MASK_RS_CCRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } 299*3d8817e4Smiod #define MASK_RS_R0RD { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } 300*3d8817e4Smiod #define MASK_RS_RRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } 301*3d8817e4Smiod #define MASK_RS_RURD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } 302*3d8817e4Smiod #define MASK_RSY_RRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } 303*3d8817e4Smiod #define MASK_RSY_RURD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } 304*3d8817e4Smiod #define MASK_RSY_AARD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } 305*3d8817e4Smiod #define MASK_RSY_CCRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } 306*3d8817e4Smiod #define MASK_RXE_FRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } 307*3d8817e4Smiod #define MASK_RXE_RRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } 308*3d8817e4Smiod #define MASK_RXF_FRRDF { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } 309*3d8817e4Smiod #define MASK_RXF_RRRDR { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } 310*3d8817e4Smiod #define MASK_RXY_RRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } 311*3d8817e4Smiod #define MASK_RXY_FRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } 312*3d8817e4Smiod #define MASK_RX_0RRD { 0xff, 0xf0, 0x00, 0x00, 0x00, 0x00 } 313*3d8817e4Smiod #define MASK_RX_FRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } 314*3d8817e4Smiod #define MASK_RX_RRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } 315*3d8817e4Smiod #define MASK_RX_URRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } 316*3d8817e4Smiod #define MASK_SI_URD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } 317*3d8817e4Smiod #define MASK_SIY_URD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } 318*3d8817e4Smiod #define MASK_SSE_RDRD { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } 319*3d8817e4Smiod #define MASK_SS_L0RDRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } 320*3d8817e4Smiod #define MASK_SS_LIRDRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } 321*3d8817e4Smiod #define MASK_SS_LLRDRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } 322*3d8817e4Smiod #define MASK_SS_RRRDRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } 323*3d8817e4Smiod #define MASK_SS_RRRDRD2 { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } 324*3d8817e4Smiod #define MASK_SS_RRRDRD3 { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } 325*3d8817e4Smiod #define MASK_S_00 { 0xff, 0xff, 0xff, 0xff, 0x00, 0x00 } 326*3d8817e4Smiod #define MASK_S_RD { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } 327*3d8817e4Smiod #define MASK_SSF_RRDRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } 328*3d8817e4Smiod 329*3d8817e4Smiod /* The opcode formats table (blueprints for .insn pseudo mnemonic). */ 330*3d8817e4Smiod 331*3d8817e4Smiod const struct s390_opcode s390_opformats[] = 332*3d8817e4Smiod { 333*3d8817e4Smiod { "e", OP8(0x00LL), MASK_E, INSTR_E, 3, 0 }, 334*3d8817e4Smiod { "ri", OP8(0x00LL), MASK_RI_RI, INSTR_RI_RI, 3, 0 }, 335*3d8817e4Smiod { "rie", OP8(0x00LL), MASK_RIE_RRP, INSTR_RIE_RRP, 3, 0 }, 336*3d8817e4Smiod { "ril", OP8(0x00LL), MASK_RIL_RP, INSTR_RIL_RP, 3, 0 }, 337*3d8817e4Smiod { "rilu", OP8(0x00LL), MASK_RIL_RU, INSTR_RIL_RU, 3, 0 }, 338*3d8817e4Smiod { "rr", OP8(0x00LL), MASK_RR_RR, INSTR_RR_RR, 3, 0 }, 339*3d8817e4Smiod { "rre", OP8(0x00LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0 }, 340*3d8817e4Smiod { "rrf", OP8(0x00LL), MASK_RRF_RURR, INSTR_RRF_RURR, 3, 0 }, 341*3d8817e4Smiod { "rs", OP8(0x00LL), MASK_RS_RRRD, INSTR_RS_RRRD, 3, 0 }, 342*3d8817e4Smiod { "rse", OP8(0x00LL), MASK_RSE_RRRD, INSTR_RSE_RRRD, 3, 0 }, 343*3d8817e4Smiod { "rsi", OP8(0x00LL), MASK_RSI_RRP, INSTR_RSI_RRP, 3, 0 }, 344*3d8817e4Smiod { "rsy", OP8(0x00LL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 3, 3 }, 345*3d8817e4Smiod { "rx", OP8(0x00LL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0 }, 346*3d8817e4Smiod { "rxe", OP8(0x00LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 3, 0 }, 347*3d8817e4Smiod { "rxf", OP8(0x00LL), MASK_RXF_RRRDR, INSTR_RXF_RRRDR,3, 0 }, 348*3d8817e4Smiod { "rxy", OP8(0x00LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 3, 3 }, 349*3d8817e4Smiod { "s", OP8(0x00LL), MASK_S_RD, INSTR_S_RD, 3, 0 }, 350*3d8817e4Smiod { "si", OP8(0x00LL), MASK_SI_URD, INSTR_SI_URD, 3, 0 }, 351*3d8817e4Smiod { "siy", OP8(0x00LL), MASK_SIY_URD, INSTR_SIY_URD, 3, 3 }, 352*3d8817e4Smiod { "ss", OP8(0x00LL), MASK_SS_RRRDRD, INSTR_SS_RRRDRD,3, 0 }, 353*3d8817e4Smiod { "sse", OP8(0x00LL), MASK_SSE_RDRD, INSTR_SSE_RDRD, 3, 0 }, 354*3d8817e4Smiod { "ssf", OP8(0x00LL), MASK_SSF_RRDRD, INSTR_SSF_RRDRD,3, 0 }, 355*3d8817e4Smiod }; 356*3d8817e4Smiod 357*3d8817e4Smiod const int s390_num_opformats = 358*3d8817e4Smiod sizeof (s390_opformats) / sizeof (s390_opformats[0]); 359*3d8817e4Smiod 360*3d8817e4Smiod #include "s390-opc.tab" 361