1*3d8817e4Smiod /* Definitions for opcode table for the sparc. 2*3d8817e4Smiod Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 2000, 2002, 3*3d8817e4Smiod 2003, 2005 Free Software Foundation, Inc. 4*3d8817e4Smiod 5*3d8817e4Smiod This file is part of GAS, the GNU Assembler, GDB, the GNU debugger, and 6*3d8817e4Smiod the GNU Binutils. 7*3d8817e4Smiod 8*3d8817e4Smiod GAS/GDB is free software; you can redistribute it and/or modify 9*3d8817e4Smiod it under the terms of the GNU General Public License as published by 10*3d8817e4Smiod the Free Software Foundation; either version 2, or (at your option) 11*3d8817e4Smiod any later version. 12*3d8817e4Smiod 13*3d8817e4Smiod GAS/GDB is distributed in the hope that it will be useful, 14*3d8817e4Smiod but WITHOUT ANY WARRANTY; without even the implied warranty of 15*3d8817e4Smiod MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16*3d8817e4Smiod GNU General Public License for more details. 17*3d8817e4Smiod 18*3d8817e4Smiod You should have received a copy of the GNU General Public License 19*3d8817e4Smiod along with GAS or GDB; see the file COPYING. If not, write to 20*3d8817e4Smiod the Free Software Foundation, 51 Franklin Street - Fifth Floor, 21*3d8817e4Smiod Boston, MA 02110-1301, USA. */ 22*3d8817e4Smiod 23*3d8817e4Smiod #include "ansidecl.h" 24*3d8817e4Smiod 25*3d8817e4Smiod /* The SPARC opcode table (and other related data) is defined in 26*3d8817e4Smiod the opcodes library in sparc-opc.c. If you change anything here, make 27*3d8817e4Smiod sure you fix up that file, and vice versa. */ 28*3d8817e4Smiod 29*3d8817e4Smiod /* FIXME-someday: perhaps the ,a's and such should be embedded in the 30*3d8817e4Smiod instruction's name rather than the args. This would make gas faster, pinsn 31*3d8817e4Smiod slower, but would mess up some macros a bit. xoxorich. */ 32*3d8817e4Smiod 33*3d8817e4Smiod /* List of instruction sets variations. 34*3d8817e4Smiod These values are such that each element is either a superset of a 35*3d8817e4Smiod preceding each one or they conflict in which case SPARC_OPCODE_CONFLICT_P 36*3d8817e4Smiod returns non-zero. 37*3d8817e4Smiod The values are indices into `sparc_opcode_archs' defined in sparc-opc.c. 38*3d8817e4Smiod Don't change this without updating sparc-opc.c. */ 39*3d8817e4Smiod 40*3d8817e4Smiod enum sparc_opcode_arch_val 41*3d8817e4Smiod { 42*3d8817e4Smiod SPARC_OPCODE_ARCH_V6 = 0, 43*3d8817e4Smiod SPARC_OPCODE_ARCH_V7, 44*3d8817e4Smiod SPARC_OPCODE_ARCH_V8, 45*3d8817e4Smiod SPARC_OPCODE_ARCH_SPARCLET, 46*3d8817e4Smiod SPARC_OPCODE_ARCH_SPARCLITE, 47*3d8817e4Smiod /* V9 variants must appear last. */ 48*3d8817e4Smiod SPARC_OPCODE_ARCH_V9, 49*3d8817e4Smiod SPARC_OPCODE_ARCH_V9A, /* V9 with ultrasparc additions. */ 50*3d8817e4Smiod SPARC_OPCODE_ARCH_V9B, /* V9 with ultrasparc and cheetah additions. */ 51*3d8817e4Smiod SPARC_OPCODE_ARCH_BAD /* Error return from sparc_opcode_lookup_arch. */ 52*3d8817e4Smiod }; 53*3d8817e4Smiod 54*3d8817e4Smiod /* The highest architecture in the table. */ 55*3d8817e4Smiod #define SPARC_OPCODE_ARCH_MAX (SPARC_OPCODE_ARCH_BAD - 1) 56*3d8817e4Smiod 57*3d8817e4Smiod /* Given an enum sparc_opcode_arch_val, return the bitmask to use in 58*3d8817e4Smiod insn encoding/decoding. */ 59*3d8817e4Smiod #define SPARC_OPCODE_ARCH_MASK(arch) (1 << (arch)) 60*3d8817e4Smiod 61*3d8817e4Smiod /* Given a valid sparc_opcode_arch_val, return non-zero if it's v9. */ 62*3d8817e4Smiod #define SPARC_OPCODE_ARCH_V9_P(arch) ((arch) >= SPARC_OPCODE_ARCH_V9) 63*3d8817e4Smiod 64*3d8817e4Smiod /* Table of cpu variants. */ 65*3d8817e4Smiod 66*3d8817e4Smiod typedef struct sparc_opcode_arch 67*3d8817e4Smiod { 68*3d8817e4Smiod const char *name; 69*3d8817e4Smiod /* Mask of sparc_opcode_arch_val's supported. 70*3d8817e4Smiod EG: For v7 this would be 71*3d8817e4Smiod (SPARC_OPCODE_ARCH_MASK (..._V6) | SPARC_OPCODE_ARCH_MASK (..._V7)). 72*3d8817e4Smiod These are short's because sparc_opcode.architecture is. */ 73*3d8817e4Smiod short supported; 74*3d8817e4Smiod } sparc_opcode_arch; 75*3d8817e4Smiod 76*3d8817e4Smiod extern const struct sparc_opcode_arch sparc_opcode_archs[]; 77*3d8817e4Smiod 78*3d8817e4Smiod /* Given architecture name, look up it's sparc_opcode_arch_val value. */ 79*3d8817e4Smiod extern enum sparc_opcode_arch_val sparc_opcode_lookup_arch (const char *); 80*3d8817e4Smiod 81*3d8817e4Smiod /* Return the bitmask of supported architectures for ARCH. */ 82*3d8817e4Smiod #define SPARC_OPCODE_SUPPORTED(ARCH) (sparc_opcode_archs[ARCH].supported) 83*3d8817e4Smiod 84*3d8817e4Smiod /* Non-zero if ARCH1 conflicts with ARCH2. 85*3d8817e4Smiod IE: ARCH1 as a supported bit set that ARCH2 doesn't, and vice versa. */ 86*3d8817e4Smiod #define SPARC_OPCODE_CONFLICT_P(ARCH1, ARCH2) \ 87*3d8817e4Smiod (((SPARC_OPCODE_SUPPORTED (ARCH1) & SPARC_OPCODE_SUPPORTED (ARCH2)) \ 88*3d8817e4Smiod != SPARC_OPCODE_SUPPORTED (ARCH1)) \ 89*3d8817e4Smiod && ((SPARC_OPCODE_SUPPORTED (ARCH1) & SPARC_OPCODE_SUPPORTED (ARCH2)) \ 90*3d8817e4Smiod != SPARC_OPCODE_SUPPORTED (ARCH2))) 91*3d8817e4Smiod 92*3d8817e4Smiod /* Structure of an opcode table entry. */ 93*3d8817e4Smiod 94*3d8817e4Smiod typedef struct sparc_opcode 95*3d8817e4Smiod { 96*3d8817e4Smiod const char *name; 97*3d8817e4Smiod unsigned long match; /* Bits that must be set. */ 98*3d8817e4Smiod unsigned long lose; /* Bits that must not be set. */ 99*3d8817e4Smiod const char *args; 100*3d8817e4Smiod /* This was called "delayed" in versions before the flags. */ 101*3d8817e4Smiod char flags; 102*3d8817e4Smiod short architecture; /* Bitmask of sparc_opcode_arch_val's. */ 103*3d8817e4Smiod } sparc_opcode; 104*3d8817e4Smiod 105*3d8817e4Smiod #define F_DELAYED 1 /* Delayed branch. */ 106*3d8817e4Smiod #define F_ALIAS 2 /* Alias for a "real" instruction. */ 107*3d8817e4Smiod #define F_UNBR 4 /* Unconditional branch. */ 108*3d8817e4Smiod #define F_CONDBR 8 /* Conditional branch. */ 109*3d8817e4Smiod #define F_JSR 16 /* Subroutine call. */ 110*3d8817e4Smiod #define F_FLOAT 32 /* Floating point instruction (not a branch). */ 111*3d8817e4Smiod #define F_FBR 64 /* Floating point branch. */ 112*3d8817e4Smiod /* FIXME: Add F_ANACHRONISTIC flag for v9. */ 113*3d8817e4Smiod 114*3d8817e4Smiod /* All sparc opcodes are 32 bits, except for the `set' instruction (really a 115*3d8817e4Smiod macro), which is 64 bits. It is handled as a special case. 116*3d8817e4Smiod 117*3d8817e4Smiod The match component is a mask saying which bits must match a particular 118*3d8817e4Smiod opcode in order for an instruction to be an instance of that opcode. 119*3d8817e4Smiod 120*3d8817e4Smiod The args component is a string containing one character for each operand of the 121*3d8817e4Smiod instruction. 122*3d8817e4Smiod 123*3d8817e4Smiod Kinds of operands: 124*3d8817e4Smiod # Number used by optimizer. It is ignored. 125*3d8817e4Smiod 1 rs1 register. 126*3d8817e4Smiod 2 rs2 register. 127*3d8817e4Smiod d rd register. 128*3d8817e4Smiod e frs1 floating point register. 129*3d8817e4Smiod v frs1 floating point register (double/even). 130*3d8817e4Smiod V frs1 floating point register (quad/multiple of 4). 131*3d8817e4Smiod f frs2 floating point register. 132*3d8817e4Smiod B frs2 floating point register (double/even). 133*3d8817e4Smiod R frs2 floating point register (quad/multiple of 4). 134*3d8817e4Smiod g frsd floating point register. 135*3d8817e4Smiod H frsd floating point register (double/even). 136*3d8817e4Smiod J frsd floating point register (quad/multiple of 4). 137*3d8817e4Smiod b crs1 coprocessor register 138*3d8817e4Smiod c crs2 coprocessor register 139*3d8817e4Smiod D crsd coprocessor register 140*3d8817e4Smiod m alternate space register (asr) in rd 141*3d8817e4Smiod M alternate space register (asr) in rs1 142*3d8817e4Smiod h 22 high bits. 143*3d8817e4Smiod X 5 bit unsigned immediate 144*3d8817e4Smiod Y 6 bit unsigned immediate 145*3d8817e4Smiod 3 SIAM mode (3 bits). (v9b) 146*3d8817e4Smiod K MEMBAR mask (7 bits). (v9) 147*3d8817e4Smiod j 10 bit Immediate. (v9) 148*3d8817e4Smiod I 11 bit Immediate. (v9) 149*3d8817e4Smiod i 13 bit Immediate. 150*3d8817e4Smiod n 22 bit immediate. 151*3d8817e4Smiod k 2+14 bit PC relative immediate. (v9) 152*3d8817e4Smiod G 19 bit PC relative immediate. (v9) 153*3d8817e4Smiod l 22 bit PC relative immediate. 154*3d8817e4Smiod L 30 bit PC relative immediate. 155*3d8817e4Smiod a Annul. The annul bit is set. 156*3d8817e4Smiod A Alternate address space. Stored as 8 bits. 157*3d8817e4Smiod C Coprocessor state register. 158*3d8817e4Smiod F floating point state register. 159*3d8817e4Smiod p Processor state register. 160*3d8817e4Smiod N Branch predict clear ",pn" (v9) 161*3d8817e4Smiod T Branch predict set ",pt" (v9) 162*3d8817e4Smiod z %icc. (v9) 163*3d8817e4Smiod Z %xcc. (v9) 164*3d8817e4Smiod q Floating point queue. 165*3d8817e4Smiod r Single register that is both rs1 and rd. 166*3d8817e4Smiod O Single register that is both rs2 and rd. 167*3d8817e4Smiod Q Coprocessor queue. 168*3d8817e4Smiod S Special case. 169*3d8817e4Smiod t Trap base register. 170*3d8817e4Smiod w Window invalid mask register. 171*3d8817e4Smiod y Y register. 172*3d8817e4Smiod u sparclet coprocessor registers in rd position 173*3d8817e4Smiod U sparclet coprocessor registers in rs1 position 174*3d8817e4Smiod E %ccr. (v9) 175*3d8817e4Smiod s %fprs. (v9) 176*3d8817e4Smiod P %pc. (v9) 177*3d8817e4Smiod W %tick. (v9) 178*3d8817e4Smiod o %asi. (v9) 179*3d8817e4Smiod 6 %fcc0. (v9) 180*3d8817e4Smiod 7 %fcc1. (v9) 181*3d8817e4Smiod 8 %fcc2. (v9) 182*3d8817e4Smiod 9 %fcc3. (v9) 183*3d8817e4Smiod ! Privileged Register in rd (v9) 184*3d8817e4Smiod ? Privileged Register in rs1 (v9) 185*3d8817e4Smiod * Prefetch function constant. (v9) 186*3d8817e4Smiod x OPF field (v9 impdep). 187*3d8817e4Smiod 0 32/64 bit immediate for set or setx (v9) insns 188*3d8817e4Smiod _ Ancillary state register in rd (v9a) 189*3d8817e4Smiod / Ancillary state register in rs1 (v9a) 190*3d8817e4Smiod 191*3d8817e4Smiod The following chars are unused: (note: ,[] are used as punctuation) 192*3d8817e4Smiod [45]. */ 193*3d8817e4Smiod 194*3d8817e4Smiod #define OP2(x) (((x) & 0x7) << 22) /* Op2 field of format2 insns. */ 195*3d8817e4Smiod #define OP3(x) (((x) & 0x3f) << 19) /* Op3 field of format3 insns. */ 196*3d8817e4Smiod #define OP(x) ((unsigned) ((x) & 0x3) << 30) /* Op field of all insns. */ 197*3d8817e4Smiod #define OPF(x) (((x) & 0x1ff) << 5) /* Opf field of float insns. */ 198*3d8817e4Smiod #define OPF_LOW5(x) OPF ((x) & 0x1f) /* V9. */ 199*3d8817e4Smiod #define F3F(x, y, z) (OP (x) | OP3 (y) | OPF (z)) /* Format3 float insns. */ 200*3d8817e4Smiod #define F3I(x) (((x) & 0x1) << 13) /* Immediate field of format 3 insns. */ 201*3d8817e4Smiod #define F2(x, y) (OP (x) | OP2(y)) /* Format 2 insns. */ 202*3d8817e4Smiod #define F3(x, y, z) (OP (x) | OP3(y) | F3I(z)) /* Format3 insns. */ 203*3d8817e4Smiod #define F1(x) (OP (x)) 204*3d8817e4Smiod #define DISP30(x) ((x) & 0x3fffffff) 205*3d8817e4Smiod #define ASI(x) (((x) & 0xff) << 5) /* Asi field of format3 insns. */ 206*3d8817e4Smiod #define RS2(x) ((x) & 0x1f) /* Rs2 field. */ 207*3d8817e4Smiod #define SIMM13(x) ((x) & 0x1fff) /* Simm13 field. */ 208*3d8817e4Smiod #define RD(x) (((x) & 0x1f) << 25) /* Destination register field. */ 209*3d8817e4Smiod #define RS1(x) (((x) & 0x1f) << 14) /* Rs1 field. */ 210*3d8817e4Smiod #define ASI_RS2(x) (SIMM13 (x)) 211*3d8817e4Smiod #define MEMBAR(x) ((x) & 0x7f) 212*3d8817e4Smiod #define SLCPOP(x) (((x) & 0x7f) << 6) /* Sparclet cpop. */ 213*3d8817e4Smiod 214*3d8817e4Smiod #define ANNUL (1 << 29) 215*3d8817e4Smiod #define BPRED (1 << 19) /* V9. */ 216*3d8817e4Smiod #define IMMED F3I (1) 217*3d8817e4Smiod #define RD_G0 RD (~0) 218*3d8817e4Smiod #define RS1_G0 RS1 (~0) 219*3d8817e4Smiod #define RS2_G0 RS2 (~0) 220*3d8817e4Smiod 221*3d8817e4Smiod extern const struct sparc_opcode sparc_opcodes[]; 222*3d8817e4Smiod extern const int sparc_num_opcodes; 223*3d8817e4Smiod 224*3d8817e4Smiod extern int sparc_encode_asi (const char *); 225*3d8817e4Smiod extern const char *sparc_decode_asi (int); 226*3d8817e4Smiod extern int sparc_encode_membar (const char *); 227*3d8817e4Smiod extern const char *sparc_decode_membar (int); 228*3d8817e4Smiod extern int sparc_encode_prefetch (const char *); 229*3d8817e4Smiod extern const char *sparc_decode_prefetch (int); 230*3d8817e4Smiod extern int sparc_encode_sparclet_cpreg (const char *); 231*3d8817e4Smiod extern const char *sparc_decode_sparclet_cpreg (int); 232*3d8817e4Smiod 233*3d8817e4Smiod /* Local Variables: 234*3d8817e4Smiod fill-column: 131 235*3d8817e4Smiod comment-column: 0 236*3d8817e4Smiod End: */ 237*3d8817e4Smiod 238