1*3d8817e4Smiod /* ARM assembler/disassembler support. 2*3d8817e4Smiod Copyright 2004 Free Software Foundation, Inc. 3*3d8817e4Smiod 4*3d8817e4Smiod This file is part of GDB and GAS. 5*3d8817e4Smiod 6*3d8817e4Smiod GDB and GAS are free software; you can redistribute it and/or 7*3d8817e4Smiod modify it under the terms of the GNU General Public License as 8*3d8817e4Smiod published by the Free Software Foundation; either version 1, or (at 9*3d8817e4Smiod your option) any later version. 10*3d8817e4Smiod 11*3d8817e4Smiod GDB and GAS are distributed in the hope that it will be useful, but 12*3d8817e4Smiod WITHOUT ANY WARRANTY; without even the implied warranty of 13*3d8817e4Smiod MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14*3d8817e4Smiod General Public License for more details. 15*3d8817e4Smiod 16*3d8817e4Smiod You should have received a copy of the GNU General Public License 17*3d8817e4Smiod along with GDB or GAS; see the file COPYING. If not, write to the 18*3d8817e4Smiod Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 19*3d8817e4Smiod 02110-1301, USA. */ 20*3d8817e4Smiod 21*3d8817e4Smiod /* The following bitmasks control CPU extensions: */ 22*3d8817e4Smiod #define ARM_EXT_V1 0x00000001 /* All processors (core set). */ 23*3d8817e4Smiod #define ARM_EXT_V2 0x00000002 /* Multiply instructions. */ 24*3d8817e4Smiod #define ARM_EXT_V2S 0x00000004 /* SWP instructions. */ 25*3d8817e4Smiod #define ARM_EXT_V3 0x00000008 /* MSR MRS. */ 26*3d8817e4Smiod #define ARM_EXT_V3M 0x00000010 /* Allow long multiplies. */ 27*3d8817e4Smiod #define ARM_EXT_V4 0x00000020 /* Allow half word loads. */ 28*3d8817e4Smiod #define ARM_EXT_V4T 0x00000040 /* Thumb. */ 29*3d8817e4Smiod #define ARM_EXT_V5 0x00000080 /* Allow CLZ, etc. */ 30*3d8817e4Smiod #define ARM_EXT_V5T 0x00000100 /* Improved interworking. */ 31*3d8817e4Smiod #define ARM_EXT_V5ExP 0x00000200 /* DSP core set. */ 32*3d8817e4Smiod #define ARM_EXT_V5E 0x00000400 /* DSP Double transfers. */ 33*3d8817e4Smiod #define ARM_EXT_V5J 0x00000800 /* Jazelle extension. */ 34*3d8817e4Smiod #define ARM_EXT_V6 0x00001000 /* ARM V6. */ 35*3d8817e4Smiod #define ARM_EXT_V6K 0x00002000 /* ARM V6K. */ 36*3d8817e4Smiod #define ARM_EXT_V6Z 0x00004000 /* ARM V6Z. */ 37*3d8817e4Smiod #define ARM_EXT_V6T2 0x00008000 /* Thumb-2. */ 38*3d8817e4Smiod #define ARM_EXT_DIV 0x00010000 /* Integer division. */ 39*3d8817e4Smiod /* The 'M' in Arm V7M stands for Microcontroller. 40*3d8817e4Smiod On earlier architecture variants it stands for Multiply. */ 41*3d8817e4Smiod #define ARM_EXT_V5E_NOTM 0x00020000 /* Arm V5E but not Arm V7M. */ 42*3d8817e4Smiod #define ARM_EXT_V6_NOTM 0x00040000 /* Arm V6 but not Arm V7M. */ 43*3d8817e4Smiod #define ARM_EXT_V7 0x00080000 /* Arm V7. */ 44*3d8817e4Smiod #define ARM_EXT_V7A 0x00100000 /* Arm V7A. */ 45*3d8817e4Smiod #define ARM_EXT_V7R 0x00200000 /* Arm V7R. */ 46*3d8817e4Smiod #define ARM_EXT_V7M 0x00400000 /* Arm V7M. */ 47*3d8817e4Smiod 48*3d8817e4Smiod /* Co-processor space extensions. */ 49*3d8817e4Smiod #define ARM_CEXT_XSCALE 0x00000001 /* Allow MIA etc. */ 50*3d8817e4Smiod #define ARM_CEXT_MAVERICK 0x00000002 /* Use Cirrus/DSP coprocessor. */ 51*3d8817e4Smiod #define ARM_CEXT_IWMMXT 0x00000004 /* Intel Wireless MMX technology coprocessor. */ 52*3d8817e4Smiod 53*3d8817e4Smiod #define FPU_ENDIAN_PURE 0x80000000 /* Pure-endian doubles. */ 54*3d8817e4Smiod #define FPU_ENDIAN_BIG 0 /* Double words-big-endian. */ 55*3d8817e4Smiod #define FPU_FPA_EXT_V1 0x40000000 /* Base FPA instruction set. */ 56*3d8817e4Smiod #define FPU_FPA_EXT_V2 0x20000000 /* LFM/SFM. */ 57*3d8817e4Smiod #define FPU_MAVERICK 0x10000000 /* Cirrus Maverick. */ 58*3d8817e4Smiod #define FPU_VFP_EXT_V1xD 0x08000000 /* Base VFP instruction set. */ 59*3d8817e4Smiod #define FPU_VFP_EXT_V1 0x04000000 /* Double-precision insns. */ 60*3d8817e4Smiod #define FPU_VFP_EXT_V2 0x02000000 /* ARM10E VFPr1. */ 61*3d8817e4Smiod 62*3d8817e4Smiod /* Architectures are the sum of the base and extensions. The ARM ARM (rev E) 63*3d8817e4Smiod defines the following: ARMv3, ARMv3M, ARMv4xM, ARMv4, ARMv4TxM, ARMv4T, 64*3d8817e4Smiod ARMv5xM, ARMv5, ARMv5TxM, ARMv5T, ARMv5TExP, ARMv5TE. To these we add 65*3d8817e4Smiod three more to cover cores prior to ARM6. Finally, there are cores which 66*3d8817e4Smiod implement further extensions in the co-processor space. */ 67*3d8817e4Smiod #define ARM_AEXT_V1 ARM_EXT_V1 68*3d8817e4Smiod #define ARM_AEXT_V2 (ARM_AEXT_V1 | ARM_EXT_V2) 69*3d8817e4Smiod #define ARM_AEXT_V2S (ARM_AEXT_V2 | ARM_EXT_V2S) 70*3d8817e4Smiod #define ARM_AEXT_V3 (ARM_AEXT_V2S | ARM_EXT_V3) 71*3d8817e4Smiod #define ARM_AEXT_V3M (ARM_AEXT_V3 | ARM_EXT_V3M) 72*3d8817e4Smiod #define ARM_AEXT_V4xM (ARM_AEXT_V3 | ARM_EXT_V4) 73*3d8817e4Smiod #define ARM_AEXT_V4 (ARM_AEXT_V3M | ARM_EXT_V4) 74*3d8817e4Smiod #define ARM_AEXT_V4TxM (ARM_AEXT_V4xM | ARM_EXT_V4T) 75*3d8817e4Smiod #define ARM_AEXT_V4T (ARM_AEXT_V4 | ARM_EXT_V4T) 76*3d8817e4Smiod #define ARM_AEXT_V5xM (ARM_AEXT_V4xM | ARM_EXT_V5) 77*3d8817e4Smiod #define ARM_AEXT_V5 (ARM_AEXT_V4 | ARM_EXT_V5) 78*3d8817e4Smiod #define ARM_AEXT_V5TxM (ARM_AEXT_V5xM | ARM_EXT_V4T | ARM_EXT_V5T) 79*3d8817e4Smiod #define ARM_AEXT_V5T (ARM_AEXT_V5 | ARM_EXT_V4T | ARM_EXT_V5T) 80*3d8817e4Smiod #define ARM_AEXT_V5TExP (ARM_AEXT_V5T | ARM_EXT_V5ExP) 81*3d8817e4Smiod #define ARM_AEXT_V5TE (ARM_AEXT_V5TExP | ARM_EXT_V5E) 82*3d8817e4Smiod #define ARM_AEXT_V5TEJ (ARM_AEXT_V5TE | ARM_EXT_V5J) 83*3d8817e4Smiod #define ARM_AEXT_V6 (ARM_AEXT_V5TEJ | ARM_EXT_V6) 84*3d8817e4Smiod #define ARM_AEXT_V6K (ARM_AEXT_V6 | ARM_EXT_V6K) 85*3d8817e4Smiod #define ARM_AEXT_V6Z (ARM_AEXT_V6 | ARM_EXT_V6Z) 86*3d8817e4Smiod #define ARM_AEXT_V6ZK (ARM_AEXT_V6 | ARM_EXT_V6K | ARM_EXT_V6Z) 87*3d8817e4Smiod #define ARM_AEXT_V6T2 (ARM_AEXT_V6 | ARM_EXT_V6T2 | ARM_EXT_V6_NOTM) 88*3d8817e4Smiod #define ARM_AEXT_V6KT2 (ARM_AEXT_V6T2 | ARM_EXT_V6K) 89*3d8817e4Smiod #define ARM_AEXT_V6ZT2 (ARM_AEXT_V6T2 | ARM_EXT_V6Z) 90*3d8817e4Smiod #define ARM_AEXT_V6ZKT2 (ARM_AEXT_V6T2 | ARM_EXT_V6K | ARM_EXT_V6Z) 91*3d8817e4Smiod #define ARM_AEXT_V7_ARM (ARM_AEXT_V6ZKT2 | ARM_EXT_V7) 92*3d8817e4Smiod #define ARM_AEXT_V7A (ARM_AEXT_V7_ARM | ARM_EXT_V7A) 93*3d8817e4Smiod #define ARM_AEXT_V7R (ARM_AEXT_V7_ARM | ARM_EXT_V7R | ARM_EXT_DIV) 94*3d8817e4Smiod #define ARM_AEXT_NOTM \ 95*3d8817e4Smiod (ARM_AEXT_V4 | ARM_EXT_V5ExP | ARM_EXT_V5J | ARM_EXT_V6_NOTM) 96*3d8817e4Smiod #define ARM_AEXT_V7M \ 97*3d8817e4Smiod ((ARM_AEXT_V7_ARM | ARM_EXT_V7M | ARM_EXT_DIV) & ~(ARM_AEXT_NOTM)) 98*3d8817e4Smiod #define ARM_AEXT_V7 (ARM_AEXT_V7A & ARM_AEXT_V7R & ARM_AEXT_V7M) 99*3d8817e4Smiod 100*3d8817e4Smiod /* Processors with specific extensions in the co-processor space. */ 101*3d8817e4Smiod #define ARM_ARCH_XSCALE ARM_FEATURE (ARM_AEXT_V5TE, ARM_CEXT_XSCALE) 102*3d8817e4Smiod #define ARM_ARCH_IWMMXT \ 103*3d8817e4Smiod ARM_FEATURE (ARM_AEXT_V5TE, ARM_CEXT_XSCALE | ARM_CEXT_IWMMXT) 104*3d8817e4Smiod 105*3d8817e4Smiod #define FPU_VFP_V1xD (FPU_VFP_EXT_V1xD | FPU_ENDIAN_PURE) 106*3d8817e4Smiod #define FPU_VFP_V1 (FPU_VFP_V1xD | FPU_VFP_EXT_V1) 107*3d8817e4Smiod #define FPU_VFP_V2 (FPU_VFP_V1 | FPU_VFP_EXT_V2) 108*3d8817e4Smiod #define FPU_VFP_HARD (FPU_VFP_EXT_V1xD | FPU_VFP_EXT_V1 | FPU_VFP_EXT_V2) 109*3d8817e4Smiod #define FPU_FPA (FPU_FPA_EXT_V1 | FPU_FPA_EXT_V2) 110*3d8817e4Smiod 111*3d8817e4Smiod /* Deprecated */ 112*3d8817e4Smiod #define FPU_ARCH_VFP ARM_FEATURE (0, FPU_ENDIAN_PURE) 113*3d8817e4Smiod 114*3d8817e4Smiod #define FPU_ARCH_FPE ARM_FEATURE (0, FPU_FPA_EXT_V1) 115*3d8817e4Smiod #define FPU_ARCH_FPA ARM_FEATURE (0, FPU_FPA) 116*3d8817e4Smiod 117*3d8817e4Smiod #define FPU_ARCH_VFP_V1xD ARM_FEATURE (0, FPU_VFP_V1xD) 118*3d8817e4Smiod #define FPU_ARCH_VFP_V1 ARM_FEATURE (0, FPU_VFP_V1) 119*3d8817e4Smiod #define FPU_ARCH_VFP_V2 ARM_FEATURE (0, FPU_VFP_V2) 120*3d8817e4Smiod #define FPU_ARCH_VFP_HARD ARM_FEATURE (0, FPU_VFP_HARD) 121*3d8817e4Smiod 122*3d8817e4Smiod #define FPU_ARCH_ENDIAN_PURE ARM_FEATURE (0, FPU_ENDIAN_PURE) 123*3d8817e4Smiod 124*3d8817e4Smiod #define FPU_ARCH_MAVERICK ARM_FEATURE (0, FPU_MAVERICK) 125*3d8817e4Smiod 126*3d8817e4Smiod #define ARM_ARCH_V1 ARM_FEATURE (ARM_AEXT_V1, 0) 127*3d8817e4Smiod #define ARM_ARCH_V2 ARM_FEATURE (ARM_AEXT_V2, 0) 128*3d8817e4Smiod #define ARM_ARCH_V2S ARM_FEATURE (ARM_AEXT_V2S, 0) 129*3d8817e4Smiod #define ARM_ARCH_V3 ARM_FEATURE (ARM_AEXT_V3, 0) 130*3d8817e4Smiod #define ARM_ARCH_V3M ARM_FEATURE (ARM_AEXT_V3M, 0) 131*3d8817e4Smiod #define ARM_ARCH_V4xM ARM_FEATURE (ARM_AEXT_V4xM, 0) 132*3d8817e4Smiod #define ARM_ARCH_V4 ARM_FEATURE (ARM_AEXT_V4, 0) 133*3d8817e4Smiod #define ARM_ARCH_V4TxM ARM_FEATURE (ARM_AEXT_V4TxM, 0) 134*3d8817e4Smiod #define ARM_ARCH_V4T ARM_FEATURE (ARM_AEXT_V4T, 0) 135*3d8817e4Smiod #define ARM_ARCH_V5xM ARM_FEATURE (ARM_AEXT_V5xM, 0) 136*3d8817e4Smiod #define ARM_ARCH_V5 ARM_FEATURE (ARM_AEXT_V5, 0) 137*3d8817e4Smiod #define ARM_ARCH_V5TxM ARM_FEATURE (ARM_AEXT_V5TxM, 0) 138*3d8817e4Smiod #define ARM_ARCH_V5T ARM_FEATURE (ARM_AEXT_V5T, 0) 139*3d8817e4Smiod #define ARM_ARCH_V5TExP ARM_FEATURE (ARM_AEXT_V5TExP, 0) 140*3d8817e4Smiod #define ARM_ARCH_V5TE ARM_FEATURE (ARM_AEXT_V5TE, 0) 141*3d8817e4Smiod #define ARM_ARCH_V5TEJ ARM_FEATURE (ARM_AEXT_V5TEJ, 0) 142*3d8817e4Smiod #define ARM_ARCH_V6 ARM_FEATURE (ARM_AEXT_V6, 0) 143*3d8817e4Smiod #define ARM_ARCH_V6K ARM_FEATURE (ARM_AEXT_V6K, 0) 144*3d8817e4Smiod #define ARM_ARCH_V6Z ARM_FEATURE (ARM_AEXT_V6Z, 0) 145*3d8817e4Smiod #define ARM_ARCH_V6ZK ARM_FEATURE (ARM_AEXT_V6ZK, 0) 146*3d8817e4Smiod #define ARM_ARCH_V6T2 ARM_FEATURE (ARM_AEXT_V6T2, 0) 147*3d8817e4Smiod #define ARM_ARCH_V6KT2 ARM_FEATURE (ARM_AEXT_V6KT2, 0) 148*3d8817e4Smiod #define ARM_ARCH_V6ZT2 ARM_FEATURE (ARM_AEXT_V6ZT2, 0) 149*3d8817e4Smiod #define ARM_ARCH_V6ZKT2 ARM_FEATURE (ARM_AEXT_V6ZKT2, 0) 150*3d8817e4Smiod #define ARM_ARCH_V7 ARM_FEATURE (ARM_AEXT_V7, 0) 151*3d8817e4Smiod #define ARM_ARCH_V7A ARM_FEATURE (ARM_AEXT_V7A, 0) 152*3d8817e4Smiod #define ARM_ARCH_V7R ARM_FEATURE (ARM_AEXT_V7R, 0) 153*3d8817e4Smiod #define ARM_ARCH_V7M ARM_FEATURE (ARM_AEXT_V7M, 0) 154*3d8817e4Smiod 155*3d8817e4Smiod /* Some useful combinations: */ 156*3d8817e4Smiod #define ARM_ARCH_NONE ARM_FEATURE (0, 0) 157*3d8817e4Smiod #define FPU_NONE ARM_FEATURE (0, 0) 158*3d8817e4Smiod #define ARM_ANY ARM_FEATURE (-1, 0) /* Any basic core. */ 159*3d8817e4Smiod #define FPU_ANY_HARD ARM_FEATURE (0, FPU_FPA | FPU_VFP_HARD | FPU_MAVERICK) 160*3d8817e4Smiod #define ARM_ARCH_THUMB2 ARM_FEATURE (ARM_EXT_V6T2 | ARM_EXT_V7 | ARM_EXT_V7A | ARM_EXT_V7R | ARM_EXT_V7M | ARM_EXT_DIV, 0) 161*3d8817e4Smiod 162*3d8817e4Smiod /* There are too many feature bits to fit in a single word, so use a 163*3d8817e4Smiod structure. For simplicity we put all core features in one word and 164*3d8817e4Smiod everything else in the other. */ 165*3d8817e4Smiod typedef struct 166*3d8817e4Smiod { 167*3d8817e4Smiod unsigned long core; 168*3d8817e4Smiod unsigned long coproc; 169*3d8817e4Smiod } arm_feature_set; 170*3d8817e4Smiod 171*3d8817e4Smiod #define ARM_CPU_HAS_FEATURE(CPU,FEAT) \ 172*3d8817e4Smiod (((CPU).core & (FEAT).core) != 0 || ((CPU).coproc & (FEAT).coproc) != 0) 173*3d8817e4Smiod 174*3d8817e4Smiod #define ARM_MERGE_FEATURE_SETS(TARG,F1,F2) \ 175*3d8817e4Smiod do { \ 176*3d8817e4Smiod (TARG).core = (F1).core | (F2).core; \ 177*3d8817e4Smiod (TARG).coproc = (F1).coproc | (F2).coproc; \ 178*3d8817e4Smiod } while (0) 179*3d8817e4Smiod 180*3d8817e4Smiod #define ARM_CLEAR_FEATURE(TARG,F1,F2) \ 181*3d8817e4Smiod do { \ 182*3d8817e4Smiod (TARG).core = (F1).core &~ (F2).core; \ 183*3d8817e4Smiod (TARG).coproc = (F1).coproc &~ (F2).coproc; \ 184*3d8817e4Smiod } while (0) 185*3d8817e4Smiod 186*3d8817e4Smiod #define ARM_FEATURE(core, coproc) {(core), (coproc)} 187