1 /* tc-sparc.c -- Assemble for the SPARC 2 Copyright 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 3 1999, 2000, 2001, 2002, 2003, 2004, 2005 4 Free Software Foundation, Inc. 5 This file is part of GAS, the GNU Assembler. 6 7 GAS is free software; you can redistribute it and/or modify 8 it under the terms of the GNU General Public License as published by 9 the Free Software Foundation; either version 2, or (at your option) 10 any later version. 11 12 GAS is distributed in the hope that it will be useful, 13 but WITHOUT ANY WARRANTY; without even the implied warranty of 14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 GNU General Public License for more details. 16 17 You should have received a copy of the GNU General Public 18 License along with GAS; see the file COPYING. If not, write 19 to the Free Software Foundation, 51 Franklin Street - Fifth Floor, 20 Boston, MA 02110-1301, USA. */ 21 22 #include <stdio.h> 23 24 #include "as.h" 25 #include "safe-ctype.h" 26 #include "subsegs.h" 27 28 #include "opcode/sparc.h" 29 #include "dw2gencfi.h" 30 31 #ifdef OBJ_ELF 32 #include "elf/sparc.h" 33 #include "dwarf2dbg.h" 34 #endif 35 36 /* Some ancient Sun C compilers would not take such hex constants as 37 unsigned, and would end up sign-extending them to form an offsetT, 38 so use these constants instead. */ 39 #define U0xffffffff ((((unsigned long) 1 << 16) << 16) - 1) 40 #define U0x80000000 ((((unsigned long) 1 << 16) << 15)) 41 42 static struct sparc_arch *lookup_arch PARAMS ((char *)); 43 static void init_default_arch PARAMS ((void)); 44 static int sparc_ip PARAMS ((char *, const struct sparc_opcode **)); 45 static int in_signed_range PARAMS ((bfd_signed_vma, bfd_signed_vma)); 46 static int in_unsigned_range PARAMS ((bfd_vma, bfd_vma)); 47 static int in_bitfield_range PARAMS ((bfd_signed_vma, bfd_signed_vma)); 48 static int sparc_ffs PARAMS ((unsigned int)); 49 static void synthetize_setuw PARAMS ((const struct sparc_opcode *)); 50 static void synthetize_setsw PARAMS ((const struct sparc_opcode *)); 51 static void synthetize_setx PARAMS ((const struct sparc_opcode *)); 52 static bfd_vma BSR PARAMS ((bfd_vma, int)); 53 static int cmp_reg_entry PARAMS ((const PTR, const PTR)); 54 static int parse_keyword_arg PARAMS ((int (*) (const char *), char **, int *)); 55 static int parse_const_expr_arg PARAMS ((char **, int *)); 56 static int get_expression PARAMS ((char *str)); 57 58 /* Default architecture. */ 59 /* ??? The default value should be V8, but sparclite support was added 60 by making it the default. GCC now passes -Asparclite, so maybe sometime in 61 the future we can set this to V8. */ 62 #ifndef DEFAULT_ARCH 63 #define DEFAULT_ARCH "sparclite" 64 #endif 65 static char *default_arch = DEFAULT_ARCH; 66 67 /* Non-zero if the initial values of `max_architecture' and `sparc_arch_size' 68 have been set. */ 69 static int default_init_p; 70 71 /* Current architecture. We don't bump up unless necessary. */ 72 static enum sparc_opcode_arch_val current_architecture = SPARC_OPCODE_ARCH_V6; 73 74 /* The maximum architecture level we can bump up to. 75 In a 32 bit environment, don't allow bumping up to v9 by default. 76 The native assembler works this way. The user is required to pass 77 an explicit argument before we'll create v9 object files. However, if 78 we don't see any v9 insns, a v8plus object file is not created. */ 79 static enum sparc_opcode_arch_val max_architecture; 80 81 /* Either 32 or 64, selects file format. */ 82 static int sparc_arch_size; 83 /* Initial (default) value, recorded separately in case a user option 84 changes the value before md_show_usage is called. */ 85 static int default_arch_size; 86 87 #ifdef OBJ_ELF 88 /* The currently selected v9 memory model. Currently only used for 89 ELF. */ 90 static enum { MM_TSO, MM_PSO, MM_RMO } sparc_memory_model = MM_RMO; 91 #endif 92 93 static int architecture_requested; 94 static int warn_on_bump; 95 96 /* If warn_on_bump and the needed architecture is higher than this 97 architecture, issue a warning. */ 98 static enum sparc_opcode_arch_val warn_after_architecture; 99 100 /* Non-zero if as should generate error if an undeclared g[23] register 101 has been used in -64. */ 102 static int no_undeclared_regs; 103 104 /* Non-zero if we should try to relax jumps and calls. */ 105 static int sparc_relax; 106 107 /* Non-zero if we are generating PIC code. */ 108 int sparc_pic_code; 109 110 /* Non-zero if we should give an error when misaligned data is seen. */ 111 static int enforce_aligned_data; 112 113 extern int target_big_endian; 114 115 static int target_little_endian_data; 116 117 /* Symbols for global registers on v9. */ 118 static symbolS *globals[8]; 119 120 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */ 121 int sparc_cie_data_alignment; 122 123 /* V9 and 86x have big and little endian data, but instructions are always big 124 endian. The sparclet has bi-endian support but both data and insns have 125 the same endianness. Global `target_big_endian' is used for data. 126 The following macro is used for instructions. */ 127 #ifndef INSN_BIG_ENDIAN 128 #define INSN_BIG_ENDIAN (target_big_endian \ 129 || default_arch_type == sparc86x \ 130 || SPARC_OPCODE_ARCH_V9_P (max_architecture)) 131 #endif 132 133 /* Handle of the OPCODE hash table. */ 134 static struct hash_control *op_hash; 135 136 static int mylog2 PARAMS ((int)); 137 static void s_data1 PARAMS ((void)); 138 static void s_seg PARAMS ((int)); 139 static void s_proc PARAMS ((int)); 140 static void s_reserve PARAMS ((int)); 141 static void s_common PARAMS ((int)); 142 static void s_empty PARAMS ((int)); 143 static void s_uacons PARAMS ((int)); 144 static void s_ncons PARAMS ((int)); 145 #ifdef OBJ_ELF 146 static void s_register PARAMS ((int)); 147 #endif 148 149 const pseudo_typeS md_pseudo_table[] = 150 { 151 {"align", s_align_bytes, 0}, /* Defaulting is invalid (0). */ 152 {"common", s_common, 0}, 153 {"empty", s_empty, 0}, 154 {"global", s_globl, 0}, 155 {"half", cons, 2}, 156 {"nword", s_ncons, 0}, 157 {"optim", s_ignore, 0}, 158 {"proc", s_proc, 0}, 159 {"reserve", s_reserve, 0}, 160 {"seg", s_seg, 0}, 161 {"skip", s_space, 0}, 162 {"word", cons, 4}, 163 {"xword", cons, 8}, 164 {"uahalf", s_uacons, 2}, 165 {"uaword", s_uacons, 4}, 166 {"uaxword", s_uacons, 8}, 167 #ifdef OBJ_ELF 168 /* These are specific to sparc/svr4. */ 169 {"2byte", s_uacons, 2}, 170 {"4byte", s_uacons, 4}, 171 {"8byte", s_uacons, 8}, 172 {"register", s_register, 0}, 173 #endif 174 {NULL, 0, 0}, 175 }; 176 177 /* This array holds the chars that always start a comment. If the 178 pre-processor is disabled, these aren't very useful. */ 179 const char comment_chars[] = "!"; /* JF removed '|' from 180 comment_chars. */ 181 182 /* This array holds the chars that only start a comment at the beginning of 183 a line. If the line seems to have the form '# 123 filename' 184 .line and .file directives will appear in the pre-processed output. */ 185 /* Note that input_file.c hand checks for '#' at the beginning of the 186 first line of the input file. This is because the compiler outputs 187 #NO_APP at the beginning of its output. */ 188 /* Also note that comments started like this one will always 189 work if '/' isn't otherwise defined. */ 190 const char line_comment_chars[] = "#"; 191 192 const char line_separator_chars[] = ";"; 193 194 /* Chars that can be used to separate mant from exp in floating point 195 nums. */ 196 const char EXP_CHARS[] = "eE"; 197 198 /* Chars that mean this number is a floating point constant. 199 As in 0f12.456 200 or 0d1.2345e12 */ 201 const char FLT_CHARS[] = "rRsSfFdDxXpP"; 202 203 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be 204 changed in read.c. Ideally it shouldn't have to know about it at all, 205 but nothing is ideal around here. */ 206 207 #define isoctal(c) ((unsigned) ((c) - '0') < 8) 208 209 struct sparc_it 210 { 211 char *error; 212 unsigned long opcode; 213 struct nlist *nlistp; 214 expressionS exp; 215 expressionS exp2; 216 int pcrel; 217 bfd_reloc_code_real_type reloc; 218 }; 219 220 struct sparc_it the_insn, set_insn; 221 222 static void output_insn 223 PARAMS ((const struct sparc_opcode *, struct sparc_it *)); 224 225 /* Table of arguments to -A. 226 The sparc_opcode_arch table in sparc-opc.c is insufficient and incorrect 227 for this use. That table is for opcodes only. This table is for opcodes 228 and file formats. */ 229 230 enum sparc_arch_types {v6, v7, v8, sparclet, sparclite, sparc86x, v8plus, 231 v8plusa, v9, v9a, v9b, v9_64}; 232 233 static struct sparc_arch { 234 char *name; 235 char *opcode_arch; 236 enum sparc_arch_types arch_type; 237 /* Default word size, as specified during configuration. 238 A value of zero means can't be used to specify default architecture. */ 239 int default_arch_size; 240 /* Allowable arg to -A? */ 241 int user_option_p; 242 } sparc_arch_table[] = { 243 { "v6", "v6", v6, 0, 1 }, 244 { "v7", "v7", v7, 0, 1 }, 245 { "v8", "v8", v8, 32, 1 }, 246 { "sparclet", "sparclet", sparclet, 32, 1 }, 247 { "sparclite", "sparclite", sparclite, 32, 1 }, 248 { "sparc86x", "sparclite", sparc86x, 32, 1 }, 249 { "v8plus", "v9", v9, 0, 1 }, 250 { "v8plusa", "v9a", v9, 0, 1 }, 251 { "v8plusb", "v9b", v9, 0, 1 }, 252 { "v9", "v9", v9, 0, 1 }, 253 { "v9a", "v9a", v9, 0, 1 }, 254 { "v9b", "v9b", v9, 0, 1 }, 255 /* This exists to allow configure.in/Makefile.in to pass one 256 value to specify both the default machine and default word size. */ 257 { "v9-64", "v9", v9, 64, 0 }, 258 { NULL, NULL, v8, 0, 0 } 259 }; 260 261 /* Variant of default_arch */ 262 static enum sparc_arch_types default_arch_type; 263 264 static struct sparc_arch * 265 lookup_arch (name) 266 char *name; 267 { 268 struct sparc_arch *sa; 269 270 for (sa = &sparc_arch_table[0]; sa->name != NULL; sa++) 271 if (strcmp (sa->name, name) == 0) 272 break; 273 if (sa->name == NULL) 274 return NULL; 275 return sa; 276 } 277 278 /* Initialize the default opcode arch and word size from the default 279 architecture name. */ 280 281 static void 282 init_default_arch () 283 { 284 struct sparc_arch *sa = lookup_arch (default_arch); 285 286 if (sa == NULL 287 || sa->default_arch_size == 0) 288 as_fatal (_("Invalid default architecture, broken assembler.")); 289 290 max_architecture = sparc_opcode_lookup_arch (sa->opcode_arch); 291 if (max_architecture == SPARC_OPCODE_ARCH_BAD) 292 as_fatal (_("Bad opcode table, broken assembler.")); 293 default_arch_size = sparc_arch_size = sa->default_arch_size; 294 default_init_p = 1; 295 default_arch_type = sa->arch_type; 296 } 297 298 /* Called by TARGET_FORMAT. */ 299 300 const char * 301 sparc_target_format () 302 { 303 /* We don't get a chance to initialize anything before we're called, 304 so handle that now. */ 305 if (! default_init_p) 306 init_default_arch (); 307 308 #ifdef OBJ_AOUT 309 #if defined(TE_NetBSD) || defined(TE_OpenBSD) 310 return "a.out-sparc-netbsd"; 311 #else 312 #ifdef TE_SPARCAOUT 313 if (target_big_endian) 314 return "a.out-sunos-big"; 315 else if (default_arch_type == sparc86x && target_little_endian_data) 316 return "a.out-sunos-big"; 317 else 318 return "a.out-sparc-little"; 319 #else 320 return "a.out-sunos-big"; 321 #endif 322 #endif 323 #endif 324 325 #ifdef OBJ_BOUT 326 return "b.out.big"; 327 #endif 328 329 #ifdef OBJ_COFF 330 #ifdef TE_LYNX 331 return "coff-sparc-lynx"; 332 #else 333 return "coff-sparc"; 334 #endif 335 #endif 336 337 #ifdef TE_VXWORKS 338 return "elf32-sparc-vxworks"; 339 #endif 340 341 #ifdef OBJ_ELF 342 return sparc_arch_size == 64 ? "elf64-sparc" : "elf32-sparc"; 343 #endif 344 345 abort (); 346 } 347 348 /* md_parse_option 349 * Invocation line includes a switch not recognized by the base assembler. 350 * See if it's a processor-specific option. These are: 351 * 352 * -bump 353 * Warn on architecture bumps. See also -A. 354 * 355 * -Av6, -Av7, -Av8, -Asparclite, -Asparclet 356 * Standard 32 bit architectures. 357 * -Av9, -Av9a, -Av9b 358 * Sparc64 in either a 32 or 64 bit world (-32/-64 says which). 359 * This used to only mean 64 bits, but properly specifying it 360 * complicated gcc's ASM_SPECs, so now opcode selection is 361 * specified orthogonally to word size (except when specifying 362 * the default, but that is an internal implementation detail). 363 * -Av8plus, -Av8plusa, -Av8plusb 364 * Same as -Av9{,a,b}. 365 * -xarch=v8plus, -xarch=v8plusa, -xarch=v8plusb 366 * Same as -Av8plus{,a,b} -32, for compatibility with Sun's 367 * assembler. 368 * -xarch=v9, -xarch=v9a, -xarch=v9b 369 * Same as -Av9{,a,b} -64, for compatibility with Sun's 370 * assembler. 371 * 372 * Select the architecture and possibly the file format. 373 * Instructions or features not supported by the selected 374 * architecture cause fatal errors. 375 * 376 * The default is to start at v6, and bump the architecture up 377 * whenever an instruction is seen at a higher level. In 32 bit 378 * environments, v9 is not bumped up to, the user must pass 379 * -Av8plus{,a,b}. 380 * 381 * If -bump is specified, a warning is printing when bumping to 382 * higher levels. 383 * 384 * If an architecture is specified, all instructions must match 385 * that architecture. Any higher level instructions are flagged 386 * as errors. Note that in the 32 bit environment specifying 387 * -Av8plus does not automatically create a v8plus object file, a 388 * v9 insn must be seen. 389 * 390 * If both an architecture and -bump are specified, the 391 * architecture starts at the specified level, but bumps are 392 * warnings. Note that we can't set `current_architecture' to 393 * the requested level in this case: in the 32 bit environment, 394 * we still must avoid creating v8plus object files unless v9 395 * insns are seen. 396 * 397 * Note: 398 * Bumping between incompatible architectures is always an 399 * error. For example, from sparclite to v9. 400 */ 401 402 #ifdef OBJ_ELF 403 const char *md_shortopts = "A:K:VQ:sq"; 404 #else 405 #ifdef OBJ_AOUT 406 const char *md_shortopts = "A:k"; 407 #else 408 const char *md_shortopts = "A:"; 409 #endif 410 #endif 411 struct option md_longopts[] = { 412 #define OPTION_BUMP (OPTION_MD_BASE) 413 {"bump", no_argument, NULL, OPTION_BUMP}, 414 #define OPTION_SPARC (OPTION_MD_BASE + 1) 415 {"sparc", no_argument, NULL, OPTION_SPARC}, 416 #define OPTION_XARCH (OPTION_MD_BASE + 2) 417 {"xarch", required_argument, NULL, OPTION_XARCH}, 418 #ifdef OBJ_ELF 419 #define OPTION_32 (OPTION_MD_BASE + 3) 420 {"32", no_argument, NULL, OPTION_32}, 421 #define OPTION_64 (OPTION_MD_BASE + 4) 422 {"64", no_argument, NULL, OPTION_64}, 423 #define OPTION_TSO (OPTION_MD_BASE + 5) 424 {"TSO", no_argument, NULL, OPTION_TSO}, 425 #define OPTION_PSO (OPTION_MD_BASE + 6) 426 {"PSO", no_argument, NULL, OPTION_PSO}, 427 #define OPTION_RMO (OPTION_MD_BASE + 7) 428 {"RMO", no_argument, NULL, OPTION_RMO}, 429 #endif 430 #ifdef SPARC_BIENDIAN 431 #define OPTION_LITTLE_ENDIAN (OPTION_MD_BASE + 8) 432 {"EL", no_argument, NULL, OPTION_LITTLE_ENDIAN}, 433 #define OPTION_BIG_ENDIAN (OPTION_MD_BASE + 9) 434 {"EB", no_argument, NULL, OPTION_BIG_ENDIAN}, 435 #endif 436 #define OPTION_ENFORCE_ALIGNED_DATA (OPTION_MD_BASE + 10) 437 {"enforce-aligned-data", no_argument, NULL, OPTION_ENFORCE_ALIGNED_DATA}, 438 #define OPTION_LITTLE_ENDIAN_DATA (OPTION_MD_BASE + 11) 439 {"little-endian-data", no_argument, NULL, OPTION_LITTLE_ENDIAN_DATA}, 440 #ifdef OBJ_ELF 441 #define OPTION_NO_UNDECLARED_REGS (OPTION_MD_BASE + 12) 442 {"no-undeclared-regs", no_argument, NULL, OPTION_NO_UNDECLARED_REGS}, 443 #define OPTION_UNDECLARED_REGS (OPTION_MD_BASE + 13) 444 {"undeclared-regs", no_argument, NULL, OPTION_UNDECLARED_REGS}, 445 #endif 446 #define OPTION_RELAX (OPTION_MD_BASE + 14) 447 {"relax", no_argument, NULL, OPTION_RELAX}, 448 #define OPTION_NO_RELAX (OPTION_MD_BASE + 15) 449 {"no-relax", no_argument, NULL, OPTION_NO_RELAX}, 450 {NULL, no_argument, NULL, 0} 451 }; 452 453 size_t md_longopts_size = sizeof (md_longopts); 454 455 int 456 md_parse_option (c, arg) 457 int c; 458 char *arg; 459 { 460 /* We don't get a chance to initialize anything before we're called, 461 so handle that now. */ 462 if (! default_init_p) 463 init_default_arch (); 464 465 switch (c) 466 { 467 case OPTION_BUMP: 468 warn_on_bump = 1; 469 warn_after_architecture = SPARC_OPCODE_ARCH_V6; 470 break; 471 472 case OPTION_XARCH: 473 #ifdef OBJ_ELF 474 if (strncmp (arg, "v9", 2) != 0) 475 md_parse_option (OPTION_32, NULL); 476 else 477 md_parse_option (OPTION_64, NULL); 478 #endif 479 /* Fall through. */ 480 481 case 'A': 482 { 483 struct sparc_arch *sa; 484 enum sparc_opcode_arch_val opcode_arch; 485 486 sa = lookup_arch (arg); 487 if (sa == NULL 488 || ! sa->user_option_p) 489 { 490 if (c == OPTION_XARCH) 491 as_bad (_("invalid architecture -xarch=%s"), arg); 492 else 493 as_bad (_("invalid architecture -A%s"), arg); 494 return 0; 495 } 496 497 opcode_arch = sparc_opcode_lookup_arch (sa->opcode_arch); 498 if (opcode_arch == SPARC_OPCODE_ARCH_BAD) 499 as_fatal (_("Bad opcode table, broken assembler.")); 500 501 max_architecture = opcode_arch; 502 architecture_requested = 1; 503 } 504 break; 505 506 case OPTION_SPARC: 507 /* Ignore -sparc, used by SunOS make default .s.o rule. */ 508 break; 509 510 case OPTION_ENFORCE_ALIGNED_DATA: 511 enforce_aligned_data = 1; 512 break; 513 514 #ifdef SPARC_BIENDIAN 515 case OPTION_LITTLE_ENDIAN: 516 target_big_endian = 0; 517 if (default_arch_type != sparclet) 518 as_fatal ("This target does not support -EL"); 519 break; 520 case OPTION_LITTLE_ENDIAN_DATA: 521 target_little_endian_data = 1; 522 target_big_endian = 0; 523 if (default_arch_type != sparc86x 524 && default_arch_type != v9) 525 as_fatal ("This target does not support --little-endian-data"); 526 break; 527 case OPTION_BIG_ENDIAN: 528 target_big_endian = 1; 529 break; 530 #endif 531 532 #ifdef OBJ_AOUT 533 case 'k': 534 sparc_pic_code = 1; 535 break; 536 #endif 537 538 #ifdef OBJ_ELF 539 case OPTION_32: 540 case OPTION_64: 541 { 542 const char **list, **l; 543 544 sparc_arch_size = c == OPTION_32 ? 32 : 64; 545 list = bfd_target_list (); 546 for (l = list; *l != NULL; l++) 547 { 548 if (sparc_arch_size == 32) 549 { 550 if (strcmp (*l, "elf32-sparc") == 0) 551 break; 552 } 553 else 554 { 555 if (strcmp (*l, "elf64-sparc") == 0) 556 break; 557 } 558 } 559 if (*l == NULL) 560 as_fatal (_("No compiled in support for %d bit object file format"), 561 sparc_arch_size); 562 free (list); 563 } 564 break; 565 566 case OPTION_TSO: 567 sparc_memory_model = MM_TSO; 568 break; 569 570 case OPTION_PSO: 571 sparc_memory_model = MM_PSO; 572 break; 573 574 case OPTION_RMO: 575 sparc_memory_model = MM_RMO; 576 break; 577 578 case 'V': 579 print_version_id (); 580 break; 581 582 case 'Q': 583 /* Qy - do emit .comment 584 Qn - do not emit .comment. */ 585 break; 586 587 case 's': 588 /* Use .stab instead of .stab.excl. */ 589 break; 590 591 case 'q': 592 /* quick -- Native assembler does fewer checks. */ 593 break; 594 595 case 'K': 596 if (strcmp (arg, "PIC") != 0) 597 as_warn (_("Unrecognized option following -K")); 598 else 599 sparc_pic_code = 1; 600 break; 601 602 case OPTION_NO_UNDECLARED_REGS: 603 no_undeclared_regs = 1; 604 break; 605 606 case OPTION_UNDECLARED_REGS: 607 no_undeclared_regs = 0; 608 break; 609 #endif 610 611 case OPTION_RELAX: 612 sparc_relax = 1; 613 break; 614 615 case OPTION_NO_RELAX: 616 sparc_relax = 0; 617 break; 618 619 default: 620 return 0; 621 } 622 623 return 1; 624 } 625 626 void 627 md_show_usage (stream) 628 FILE *stream; 629 { 630 const struct sparc_arch *arch; 631 int column; 632 633 /* We don't get a chance to initialize anything before we're called, 634 so handle that now. */ 635 if (! default_init_p) 636 init_default_arch (); 637 638 fprintf (stream, _("SPARC options:\n")); 639 column = 0; 640 for (arch = &sparc_arch_table[0]; arch->name; arch++) 641 { 642 if (!arch->user_option_p) 643 continue; 644 if (arch != &sparc_arch_table[0]) 645 fprintf (stream, " | "); 646 if (column + strlen (arch->name) > 70) 647 { 648 column = 0; 649 fputc ('\n', stream); 650 } 651 column += 5 + 2 + strlen (arch->name); 652 fprintf (stream, "-A%s", arch->name); 653 } 654 for (arch = &sparc_arch_table[0]; arch->name; arch++) 655 { 656 if (!arch->user_option_p) 657 continue; 658 fprintf (stream, " | "); 659 if (column + strlen (arch->name) > 65) 660 { 661 column = 0; 662 fputc ('\n', stream); 663 } 664 column += 5 + 7 + strlen (arch->name); 665 fprintf (stream, "-xarch=%s", arch->name); 666 } 667 fprintf (stream, _("\n\ 668 specify variant of SPARC architecture\n\ 669 -bump warn when assembler switches architectures\n\ 670 -sparc ignored\n\ 671 --enforce-aligned-data force .long, etc., to be aligned correctly\n\ 672 -relax relax jumps and branches (default)\n\ 673 -no-relax avoid changing any jumps and branches\n")); 674 #ifdef OBJ_AOUT 675 fprintf (stream, _("\ 676 -k generate PIC\n")); 677 #endif 678 #ifdef OBJ_ELF 679 fprintf (stream, _("\ 680 -32 create 32 bit object file\n\ 681 -64 create 64 bit object file\n")); 682 fprintf (stream, _("\ 683 [default is %d]\n"), default_arch_size); 684 fprintf (stream, _("\ 685 -TSO use Total Store Ordering\n\ 686 -PSO use Partial Store Ordering\n\ 687 -RMO use Relaxed Memory Ordering\n")); 688 fprintf (stream, _("\ 689 [default is %s]\n"), (default_arch_size == 64) ? "RMO" : "TSO"); 690 fprintf (stream, _("\ 691 -KPIC generate PIC\n\ 692 -V print assembler version number\n\ 693 -undeclared-regs ignore application global register usage without\n\ 694 appropriate .register directive (default)\n\ 695 -no-undeclared-regs force error on application global register usage\n\ 696 without appropriate .register directive\n\ 697 -q ignored\n\ 698 -Qy, -Qn ignored\n\ 699 -s ignored\n")); 700 #endif 701 #ifdef SPARC_BIENDIAN 702 fprintf (stream, _("\ 703 -EL generate code for a little endian machine\n\ 704 -EB generate code for a big endian machine\n\ 705 --little-endian-data generate code for a machine having big endian\n\ 706 instructions and little endian data.\n")); 707 #endif 708 } 709 710 /* Native operand size opcode translation. */ 711 struct 712 { 713 char *name; 714 char *name32; 715 char *name64; 716 } native_op_table[] = 717 { 718 {"ldn", "ld", "ldx"}, 719 {"ldna", "lda", "ldxa"}, 720 {"stn", "st", "stx"}, 721 {"stna", "sta", "stxa"}, 722 {"slln", "sll", "sllx"}, 723 {"srln", "srl", "srlx"}, 724 {"sran", "sra", "srax"}, 725 {"casn", "cas", "casx"}, 726 {"casna", "casa", "casxa"}, 727 {"clrn", "clr", "clrx"}, 728 {NULL, NULL, NULL}, 729 }; 730 731 /* sparc64 privileged and hyperprivileged registers. */ 732 733 struct priv_reg_entry 734 { 735 char *name; 736 int regnum; 737 }; 738 739 struct priv_reg_entry priv_reg_table[] = 740 { 741 {"tpc", 0}, 742 {"tnpc", 1}, 743 {"tstate", 2}, 744 {"tt", 3}, 745 {"tick", 4}, 746 {"tba", 5}, 747 {"pstate", 6}, 748 {"tl", 7}, 749 {"pil", 8}, 750 {"cwp", 9}, 751 {"cansave", 10}, 752 {"canrestore", 11}, 753 {"cleanwin", 12}, 754 {"otherwin", 13}, 755 {"wstate", 14}, 756 {"fq", 15}, 757 {"gl", 16}, 758 {"ver", 31}, 759 {"", -1}, /* End marker. */ 760 }; 761 762 struct priv_reg_entry hpriv_reg_table[] = 763 { 764 {"hpstate", 0}, 765 {"htstate", 1}, 766 {"hintp", 3}, 767 {"htba", 5}, 768 {"hver", 6}, 769 {"hstick_cmpr", 31}, 770 {"", -1}, /* End marker. */ 771 }; 772 773 /* v9a specific asrs. */ 774 775 struct priv_reg_entry v9a_asr_table[] = 776 { 777 {"tick_cmpr", 23}, 778 {"sys_tick_cmpr", 25}, 779 {"sys_tick", 24}, 780 {"softint", 22}, 781 {"set_softint", 20}, 782 {"pic", 17}, 783 {"pcr", 16}, 784 {"gsr", 19}, 785 {"dcr", 18}, 786 {"clear_softint", 21}, 787 {"", -1}, /* End marker. */ 788 }; 789 790 static int 791 cmp_reg_entry (parg, qarg) 792 const PTR parg; 793 const PTR qarg; 794 { 795 const struct priv_reg_entry *p = (const struct priv_reg_entry *) parg; 796 const struct priv_reg_entry *q = (const struct priv_reg_entry *) qarg; 797 798 return strcmp (q->name, p->name); 799 } 800 801 /* This function is called once, at assembler startup time. It should 802 set up all the tables, etc. that the MD part of the assembler will 803 need. */ 804 805 void 806 md_begin () 807 { 808 register const char *retval = NULL; 809 int lose = 0; 810 register unsigned int i = 0; 811 812 /* We don't get a chance to initialize anything before md_parse_option 813 is called, and it may not be called, so handle default initialization 814 now if not already done. */ 815 if (! default_init_p) 816 init_default_arch (); 817 818 sparc_cie_data_alignment = sparc_arch_size == 64 ? -8 : -4; 819 op_hash = hash_new (); 820 821 while (i < (unsigned int) sparc_num_opcodes) 822 { 823 const char *name = sparc_opcodes[i].name; 824 retval = hash_insert (op_hash, name, (PTR) &sparc_opcodes[i]); 825 if (retval != NULL) 826 { 827 as_bad (_("Internal error: can't hash `%s': %s\n"), 828 sparc_opcodes[i].name, retval); 829 lose = 1; 830 } 831 do 832 { 833 if (sparc_opcodes[i].match & sparc_opcodes[i].lose) 834 { 835 as_bad (_("Internal error: losing opcode: `%s' \"%s\"\n"), 836 sparc_opcodes[i].name, sparc_opcodes[i].args); 837 lose = 1; 838 } 839 ++i; 840 } 841 while (i < (unsigned int) sparc_num_opcodes 842 && !strcmp (sparc_opcodes[i].name, name)); 843 } 844 845 for (i = 0; native_op_table[i].name; i++) 846 { 847 const struct sparc_opcode *insn; 848 char *name = ((sparc_arch_size == 32) 849 ? native_op_table[i].name32 850 : native_op_table[i].name64); 851 insn = (struct sparc_opcode *) hash_find (op_hash, name); 852 if (insn == NULL) 853 { 854 as_bad (_("Internal error: can't find opcode `%s' for `%s'\n"), 855 name, native_op_table[i].name); 856 lose = 1; 857 } 858 else 859 { 860 retval = hash_insert (op_hash, native_op_table[i].name, (PTR) insn); 861 if (retval != NULL) 862 { 863 as_bad (_("Internal error: can't hash `%s': %s\n"), 864 sparc_opcodes[i].name, retval); 865 lose = 1; 866 } 867 } 868 } 869 870 if (lose) 871 as_fatal (_("Broken assembler. No assembly attempted.")); 872 873 qsort (priv_reg_table, sizeof (priv_reg_table) / sizeof (priv_reg_table[0]), 874 sizeof (priv_reg_table[0]), cmp_reg_entry); 875 876 /* If -bump, record the architecture level at which we start issuing 877 warnings. The behaviour is different depending upon whether an 878 architecture was explicitly specified. If it wasn't, we issue warnings 879 for all upwards bumps. If it was, we don't start issuing warnings until 880 we need to bump beyond the requested architecture or when we bump between 881 conflicting architectures. */ 882 883 if (warn_on_bump 884 && architecture_requested) 885 { 886 /* `max_architecture' records the requested architecture. 887 Issue warnings if we go above it. */ 888 warn_after_architecture = max_architecture; 889 890 /* Find the highest architecture level that doesn't conflict with 891 the requested one. */ 892 for (max_architecture = SPARC_OPCODE_ARCH_MAX; 893 max_architecture > warn_after_architecture; 894 --max_architecture) 895 if (! SPARC_OPCODE_CONFLICT_P (max_architecture, 896 warn_after_architecture)) 897 break; 898 } 899 } 900 901 /* Called after all assembly has been done. */ 902 903 void 904 sparc_md_end () 905 { 906 unsigned long mach = bfd_mach_sparc; 907 908 if (sparc_arch_size == 64) 909 switch (current_architecture) 910 { 911 case SPARC_OPCODE_ARCH_V9A: mach = bfd_mach_sparc_v9a; break; 912 case SPARC_OPCODE_ARCH_V9B: mach = bfd_mach_sparc_v9b; break; 913 default: mach = bfd_mach_sparc_v9; break; 914 } 915 else 916 switch (current_architecture) 917 { 918 case SPARC_OPCODE_ARCH_SPARCLET: mach = bfd_mach_sparc_sparclet; break; 919 case SPARC_OPCODE_ARCH_V9: mach = bfd_mach_sparc_v8plus; break; 920 case SPARC_OPCODE_ARCH_V9A: mach = bfd_mach_sparc_v8plusa; break; 921 case SPARC_OPCODE_ARCH_V9B: mach = bfd_mach_sparc_v8plusb; break; 922 /* The sparclite is treated like a normal sparc. Perhaps it shouldn't 923 be but for now it is (since that's the way it's always been 924 treated). */ 925 default: break; 926 } 927 bfd_set_arch_mach (stdoutput, bfd_arch_sparc, mach); 928 } 929 930 /* Return non-zero if VAL is in the range -(MAX+1) to MAX. */ 931 932 static INLINE int 933 in_signed_range (val, max) 934 bfd_signed_vma val, max; 935 { 936 if (max <= 0) 937 abort (); 938 /* Sign-extend the value from the architecture word size, so that 939 0xffffffff is always considered -1 on sparc32. */ 940 if (sparc_arch_size == 32) 941 { 942 bfd_signed_vma sign = (bfd_signed_vma) 1 << 31; 943 val = ((val & U0xffffffff) ^ sign) - sign; 944 } 945 if (val > max) 946 return 0; 947 if (val < ~max) 948 return 0; 949 return 1; 950 } 951 952 /* Return non-zero if VAL is in the range 0 to MAX. */ 953 954 static INLINE int 955 in_unsigned_range (val, max) 956 bfd_vma val, max; 957 { 958 if (val > max) 959 return 0; 960 return 1; 961 } 962 963 /* Return non-zero if VAL is in the range -(MAX/2+1) to MAX. 964 (e.g. -15 to +31). */ 965 966 static INLINE int 967 in_bitfield_range (val, max) 968 bfd_signed_vma val, max; 969 { 970 if (max <= 0) 971 abort (); 972 if (val > max) 973 return 0; 974 if (val < ~(max >> 1)) 975 return 0; 976 return 1; 977 } 978 979 static int 980 sparc_ffs (mask) 981 unsigned int mask; 982 { 983 int i; 984 985 if (mask == 0) 986 return -1; 987 988 for (i = 0; (mask & 1) == 0; ++i) 989 mask >>= 1; 990 return i; 991 } 992 993 /* Implement big shift right. */ 994 static bfd_vma 995 BSR (val, amount) 996 bfd_vma val; 997 int amount; 998 { 999 if (sizeof (bfd_vma) <= 4 && amount >= 32) 1000 as_fatal (_("Support for 64-bit arithmetic not compiled in.")); 1001 return val >> amount; 1002 } 1003 1004 /* For communication between sparc_ip and get_expression. */ 1005 static char *expr_end; 1006 1007 /* Values for `special_case'. 1008 Instructions that require wierd handling because they're longer than 1009 4 bytes. */ 1010 #define SPECIAL_CASE_NONE 0 1011 #define SPECIAL_CASE_SET 1 1012 #define SPECIAL_CASE_SETSW 2 1013 #define SPECIAL_CASE_SETX 3 1014 /* FIXME: sparc-opc.c doesn't have necessary "S" trigger to enable this. */ 1015 #define SPECIAL_CASE_FDIV 4 1016 1017 /* Bit masks of various insns. */ 1018 #define NOP_INSN 0x01000000 1019 #define OR_INSN 0x80100000 1020 #define XOR_INSN 0x80180000 1021 #define FMOVS_INSN 0x81A00020 1022 #define SETHI_INSN 0x01000000 1023 #define SLLX_INSN 0x81281000 1024 #define SRA_INSN 0x81380000 1025 1026 /* The last instruction to be assembled. */ 1027 static const struct sparc_opcode *last_insn; 1028 /* The assembled opcode of `last_insn'. */ 1029 static unsigned long last_opcode; 1030 1031 /* Handle the set and setuw synthetic instructions. */ 1032 1033 static void 1034 synthetize_setuw (insn) 1035 const struct sparc_opcode *insn; 1036 { 1037 int need_hi22_p = 0; 1038 int rd = (the_insn.opcode & RD (~0)) >> 25; 1039 1040 if (the_insn.exp.X_op == O_constant) 1041 { 1042 if (SPARC_OPCODE_ARCH_V9_P (max_architecture)) 1043 { 1044 if (sizeof (offsetT) > 4 1045 && (the_insn.exp.X_add_number < 0 1046 || the_insn.exp.X_add_number > (offsetT) U0xffffffff)) 1047 as_warn (_("set: number not in 0..4294967295 range")); 1048 } 1049 else 1050 { 1051 if (sizeof (offsetT) > 4 1052 && (the_insn.exp.X_add_number < -(offsetT) U0x80000000 1053 || the_insn.exp.X_add_number > (offsetT) U0xffffffff)) 1054 as_warn (_("set: number not in -2147483648..4294967295 range")); 1055 the_insn.exp.X_add_number = (int) the_insn.exp.X_add_number; 1056 } 1057 } 1058 1059 /* See if operand is absolute and small; skip sethi if so. */ 1060 if (the_insn.exp.X_op != O_constant 1061 || the_insn.exp.X_add_number >= (1 << 12) 1062 || the_insn.exp.X_add_number < -(1 << 12)) 1063 { 1064 the_insn.opcode = (SETHI_INSN | RD (rd) 1065 | ((the_insn.exp.X_add_number >> 10) 1066 & (the_insn.exp.X_op == O_constant 1067 ? 0x3fffff : 0))); 1068 the_insn.reloc = (the_insn.exp.X_op != O_constant 1069 ? BFD_RELOC_HI22 : BFD_RELOC_NONE); 1070 output_insn (insn, &the_insn); 1071 need_hi22_p = 1; 1072 } 1073 1074 /* See if operand has no low-order bits; skip OR if so. */ 1075 if (the_insn.exp.X_op != O_constant 1076 || (need_hi22_p && (the_insn.exp.X_add_number & 0x3FF) != 0) 1077 || ! need_hi22_p) 1078 { 1079 the_insn.opcode = (OR_INSN | (need_hi22_p ? RS1 (rd) : 0) 1080 | RD (rd) | IMMED 1081 | (the_insn.exp.X_add_number 1082 & (the_insn.exp.X_op != O_constant 1083 ? 0 : need_hi22_p ? 0x3ff : 0x1fff))); 1084 the_insn.reloc = (the_insn.exp.X_op != O_constant 1085 ? BFD_RELOC_LO10 : BFD_RELOC_NONE); 1086 output_insn (insn, &the_insn); 1087 } 1088 } 1089 1090 /* Handle the setsw synthetic instruction. */ 1091 1092 static void 1093 synthetize_setsw (insn) 1094 const struct sparc_opcode *insn; 1095 { 1096 int low32, rd, opc; 1097 1098 rd = (the_insn.opcode & RD (~0)) >> 25; 1099 1100 if (the_insn.exp.X_op != O_constant) 1101 { 1102 synthetize_setuw (insn); 1103 1104 /* Need to sign extend it. */ 1105 the_insn.opcode = (SRA_INSN | RS1 (rd) | RD (rd)); 1106 the_insn.reloc = BFD_RELOC_NONE; 1107 output_insn (insn, &the_insn); 1108 return; 1109 } 1110 1111 if (sizeof (offsetT) > 4 1112 && (the_insn.exp.X_add_number < -(offsetT) U0x80000000 1113 || the_insn.exp.X_add_number > (offsetT) U0xffffffff)) 1114 as_warn (_("setsw: number not in -2147483648..4294967295 range")); 1115 1116 low32 = the_insn.exp.X_add_number; 1117 1118 if (low32 >= 0) 1119 { 1120 synthetize_setuw (insn); 1121 return; 1122 } 1123 1124 opc = OR_INSN; 1125 1126 the_insn.reloc = BFD_RELOC_NONE; 1127 /* See if operand is absolute and small; skip sethi if so. */ 1128 if (low32 < -(1 << 12)) 1129 { 1130 the_insn.opcode = (SETHI_INSN | RD (rd) 1131 | (((~the_insn.exp.X_add_number) >> 10) & 0x3fffff)); 1132 output_insn (insn, &the_insn); 1133 low32 = 0x1c00 | (low32 & 0x3ff); 1134 opc = RS1 (rd) | XOR_INSN; 1135 } 1136 1137 the_insn.opcode = (opc | RD (rd) | IMMED 1138 | (low32 & 0x1fff)); 1139 output_insn (insn, &the_insn); 1140 } 1141 1142 /* Handle the setsw synthetic instruction. */ 1143 1144 static void 1145 synthetize_setx (insn) 1146 const struct sparc_opcode *insn; 1147 { 1148 int upper32, lower32; 1149 int tmpreg = (the_insn.opcode & RS1 (~0)) >> 14; 1150 int dstreg = (the_insn.opcode & RD (~0)) >> 25; 1151 int upper_dstreg; 1152 int need_hh22_p = 0, need_hm10_p = 0, need_hi22_p = 0, need_lo10_p = 0; 1153 int need_xor10_p = 0; 1154 1155 #define SIGNEXT32(x) ((((x) & U0xffffffff) ^ U0x80000000) - U0x80000000) 1156 lower32 = SIGNEXT32 (the_insn.exp.X_add_number); 1157 upper32 = SIGNEXT32 (BSR (the_insn.exp.X_add_number, 32)); 1158 #undef SIGNEXT32 1159 1160 upper_dstreg = tmpreg; 1161 /* The tmp reg should not be the dst reg. */ 1162 if (tmpreg == dstreg) 1163 as_warn (_("setx: temporary register same as destination register")); 1164 1165 /* ??? Obviously there are other optimizations we can do 1166 (e.g. sethi+shift for 0x1f0000000) and perhaps we shouldn't be 1167 doing some of these. Later. If you do change things, try to 1168 change all of this to be table driven as well. */ 1169 /* What to output depends on the number if it's constant. 1170 Compute that first, then output what we've decided upon. */ 1171 if (the_insn.exp.X_op != O_constant) 1172 { 1173 if (sparc_arch_size == 32) 1174 { 1175 /* When arch size is 32, we want setx to be equivalent 1176 to setuw for anything but constants. */ 1177 the_insn.exp.X_add_number &= 0xffffffff; 1178 synthetize_setuw (insn); 1179 return; 1180 } 1181 need_hh22_p = need_hm10_p = need_hi22_p = need_lo10_p = 1; 1182 lower32 = 0; 1183 upper32 = 0; 1184 } 1185 else 1186 { 1187 /* Reset X_add_number, we've extracted it as upper32/lower32. 1188 Otherwise fixup_segment will complain about not being able to 1189 write an 8 byte number in a 4 byte field. */ 1190 the_insn.exp.X_add_number = 0; 1191 1192 /* Only need hh22 if `or' insn can't handle constant. */ 1193 if (upper32 < -(1 << 12) || upper32 >= (1 << 12)) 1194 need_hh22_p = 1; 1195 1196 /* Does bottom part (after sethi) have bits? */ 1197 if ((need_hh22_p && (upper32 & 0x3ff) != 0) 1198 /* No hh22, but does upper32 still have bits we can't set 1199 from lower32? */ 1200 || (! need_hh22_p && upper32 != 0 && upper32 != -1)) 1201 need_hm10_p = 1; 1202 1203 /* If the lower half is all zero, we build the upper half directly 1204 into the dst reg. */ 1205 if (lower32 != 0 1206 /* Need lower half if number is zero or 0xffffffff00000000. */ 1207 || (! need_hh22_p && ! need_hm10_p)) 1208 { 1209 /* No need for sethi if `or' insn can handle constant. */ 1210 if (lower32 < -(1 << 12) || lower32 >= (1 << 12) 1211 /* Note that we can't use a negative constant in the `or' 1212 insn unless the upper 32 bits are all ones. */ 1213 || (lower32 < 0 && upper32 != -1) 1214 || (lower32 >= 0 && upper32 == -1)) 1215 need_hi22_p = 1; 1216 1217 if (need_hi22_p && upper32 == -1) 1218 need_xor10_p = 1; 1219 1220 /* Does bottom part (after sethi) have bits? */ 1221 else if ((need_hi22_p && (lower32 & 0x3ff) != 0) 1222 /* No sethi. */ 1223 || (! need_hi22_p && (lower32 & 0x1fff) != 0) 1224 /* Need `or' if we didn't set anything else. */ 1225 || (! need_hi22_p && ! need_hh22_p && ! need_hm10_p)) 1226 need_lo10_p = 1; 1227 } 1228 else 1229 /* Output directly to dst reg if lower 32 bits are all zero. */ 1230 upper_dstreg = dstreg; 1231 } 1232 1233 if (!upper_dstreg && dstreg) 1234 as_warn (_("setx: illegal temporary register g0")); 1235 1236 if (need_hh22_p) 1237 { 1238 the_insn.opcode = (SETHI_INSN | RD (upper_dstreg) 1239 | ((upper32 >> 10) & 0x3fffff)); 1240 the_insn.reloc = (the_insn.exp.X_op != O_constant 1241 ? BFD_RELOC_SPARC_HH22 : BFD_RELOC_NONE); 1242 output_insn (insn, &the_insn); 1243 } 1244 1245 if (need_hi22_p) 1246 { 1247 the_insn.opcode = (SETHI_INSN | RD (dstreg) 1248 | (((need_xor10_p ? ~lower32 : lower32) 1249 >> 10) & 0x3fffff)); 1250 the_insn.reloc = (the_insn.exp.X_op != O_constant 1251 ? BFD_RELOC_SPARC_LM22 : BFD_RELOC_NONE); 1252 output_insn (insn, &the_insn); 1253 } 1254 1255 if (need_hm10_p) 1256 { 1257 the_insn.opcode = (OR_INSN 1258 | (need_hh22_p ? RS1 (upper_dstreg) : 0) 1259 | RD (upper_dstreg) 1260 | IMMED 1261 | (upper32 & (need_hh22_p ? 0x3ff : 0x1fff))); 1262 the_insn.reloc = (the_insn.exp.X_op != O_constant 1263 ? BFD_RELOC_SPARC_HM10 : BFD_RELOC_NONE); 1264 output_insn (insn, &the_insn); 1265 } 1266 1267 if (need_lo10_p) 1268 { 1269 /* FIXME: One nice optimization to do here is to OR the low part 1270 with the highpart if hi22 isn't needed and the low part is 1271 positive. */ 1272 the_insn.opcode = (OR_INSN | (need_hi22_p ? RS1 (dstreg) : 0) 1273 | RD (dstreg) 1274 | IMMED 1275 | (lower32 & (need_hi22_p ? 0x3ff : 0x1fff))); 1276 the_insn.reloc = (the_insn.exp.X_op != O_constant 1277 ? BFD_RELOC_LO10 : BFD_RELOC_NONE); 1278 output_insn (insn, &the_insn); 1279 } 1280 1281 /* If we needed to build the upper part, shift it into place. */ 1282 if (need_hh22_p || need_hm10_p) 1283 { 1284 the_insn.opcode = (SLLX_INSN | RS1 (upper_dstreg) | RD (upper_dstreg) 1285 | IMMED | 32); 1286 the_insn.reloc = BFD_RELOC_NONE; 1287 output_insn (insn, &the_insn); 1288 } 1289 1290 /* To get -1 in upper32, we do sethi %hi(~x), r; xor r, -0x400 | x, r. */ 1291 if (need_xor10_p) 1292 { 1293 the_insn.opcode = (XOR_INSN | RS1 (dstreg) | RD (dstreg) | IMMED 1294 | 0x1c00 | (lower32 & 0x3ff)); 1295 the_insn.reloc = BFD_RELOC_NONE; 1296 output_insn (insn, &the_insn); 1297 } 1298 1299 /* If we needed to build both upper and lower parts, OR them together. */ 1300 else if ((need_hh22_p || need_hm10_p) && (need_hi22_p || need_lo10_p)) 1301 { 1302 the_insn.opcode = (OR_INSN | RS1 (dstreg) | RS2 (upper_dstreg) 1303 | RD (dstreg)); 1304 the_insn.reloc = BFD_RELOC_NONE; 1305 output_insn (insn, &the_insn); 1306 } 1307 } 1308 1309 /* Main entry point to assemble one instruction. */ 1310 1311 void 1312 md_assemble (str) 1313 char *str; 1314 { 1315 const struct sparc_opcode *insn; 1316 int special_case; 1317 1318 know (str); 1319 special_case = sparc_ip (str, &insn); 1320 if (insn == NULL) 1321 return; 1322 1323 /* We warn about attempts to put a floating point branch in a delay slot, 1324 unless the delay slot has been annulled. */ 1325 if (last_insn != NULL 1326 && (insn->flags & F_FBR) != 0 1327 && (last_insn->flags & F_DELAYED) != 0 1328 /* ??? This test isn't completely accurate. We assume anything with 1329 F_{UNBR,CONDBR,FBR} set is annullable. */ 1330 && ((last_insn->flags & (F_UNBR | F_CONDBR | F_FBR)) == 0 1331 || (last_opcode & ANNUL) == 0)) 1332 as_warn (_("FP branch in delay slot")); 1333 1334 /* SPARC before v9 requires a nop instruction between a floating 1335 point instruction and a floating point branch. We insert one 1336 automatically, with a warning. */ 1337 if (max_architecture < SPARC_OPCODE_ARCH_V9 1338 && last_insn != NULL 1339 && (insn->flags & F_FBR) != 0 1340 && (last_insn->flags & F_FLOAT) != 0) 1341 { 1342 struct sparc_it nop_insn; 1343 1344 nop_insn.opcode = NOP_INSN; 1345 nop_insn.reloc = BFD_RELOC_NONE; 1346 output_insn (insn, &nop_insn); 1347 as_warn (_("FP branch preceded by FP instruction; NOP inserted")); 1348 } 1349 1350 switch (special_case) 1351 { 1352 case SPECIAL_CASE_NONE: 1353 /* Normal insn. */ 1354 output_insn (insn, &the_insn); 1355 break; 1356 1357 case SPECIAL_CASE_SETSW: 1358 synthetize_setsw (insn); 1359 break; 1360 1361 case SPECIAL_CASE_SET: 1362 synthetize_setuw (insn); 1363 break; 1364 1365 case SPECIAL_CASE_SETX: 1366 synthetize_setx (insn); 1367 break; 1368 1369 case SPECIAL_CASE_FDIV: 1370 { 1371 int rd = (the_insn.opcode >> 25) & 0x1f; 1372 1373 output_insn (insn, &the_insn); 1374 1375 /* According to information leaked from Sun, the "fdiv" instructions 1376 on early SPARC machines would produce incorrect results sometimes. 1377 The workaround is to add an fmovs of the destination register to 1378 itself just after the instruction. This was true on machines 1379 with Weitek 1165 float chips, such as the Sun-4/260 and /280. */ 1380 assert (the_insn.reloc == BFD_RELOC_NONE); 1381 the_insn.opcode = FMOVS_INSN | rd | RD (rd); 1382 output_insn (insn, &the_insn); 1383 return; 1384 } 1385 1386 default: 1387 as_fatal (_("failed special case insn sanity check")); 1388 } 1389 } 1390 1391 /* Subroutine of md_assemble to do the actual parsing. */ 1392 1393 static int 1394 sparc_ip (str, pinsn) 1395 char *str; 1396 const struct sparc_opcode **pinsn; 1397 { 1398 char *error_message = ""; 1399 char *s; 1400 const char *args; 1401 char c; 1402 const struct sparc_opcode *insn; 1403 char *argsStart; 1404 unsigned long opcode; 1405 unsigned int mask = 0; 1406 int match = 0; 1407 int comma = 0; 1408 int v9_arg_p; 1409 int special_case = SPECIAL_CASE_NONE; 1410 1411 s = str; 1412 if (ISLOWER (*s)) 1413 { 1414 do 1415 ++s; 1416 while (ISLOWER (*s) || ISDIGIT (*s)); 1417 } 1418 1419 switch (*s) 1420 { 1421 case '\0': 1422 break; 1423 1424 case ',': 1425 comma = 1; 1426 /* Fall through. */ 1427 1428 case ' ': 1429 *s++ = '\0'; 1430 break; 1431 1432 default: 1433 as_bad (_("Unknown opcode: `%s'"), str); 1434 *pinsn = NULL; 1435 return special_case; 1436 } 1437 insn = (struct sparc_opcode *) hash_find (op_hash, str); 1438 *pinsn = insn; 1439 if (insn == NULL) 1440 { 1441 as_bad (_("Unknown opcode: `%s'"), str); 1442 return special_case; 1443 } 1444 if (comma) 1445 { 1446 *--s = ','; 1447 } 1448 1449 argsStart = s; 1450 for (;;) 1451 { 1452 opcode = insn->match; 1453 memset (&the_insn, '\0', sizeof (the_insn)); 1454 the_insn.reloc = BFD_RELOC_NONE; 1455 v9_arg_p = 0; 1456 1457 /* Build the opcode, checking as we go to make sure that the 1458 operands match. */ 1459 for (args = insn->args;; ++args) 1460 { 1461 switch (*args) 1462 { 1463 case 'K': 1464 { 1465 int kmask = 0; 1466 1467 /* Parse a series of masks. */ 1468 if (*s == '#') 1469 { 1470 while (*s == '#') 1471 { 1472 int mask; 1473 1474 if (! parse_keyword_arg (sparc_encode_membar, &s, 1475 &mask)) 1476 { 1477 error_message = _(": invalid membar mask name"); 1478 goto error; 1479 } 1480 kmask |= mask; 1481 while (*s == ' ') 1482 ++s; 1483 if (*s == '|' || *s == '+') 1484 ++s; 1485 while (*s == ' ') 1486 ++s; 1487 } 1488 } 1489 else 1490 { 1491 if (! parse_const_expr_arg (&s, &kmask)) 1492 { 1493 error_message = _(": invalid membar mask expression"); 1494 goto error; 1495 } 1496 if (kmask < 0 || kmask > 127) 1497 { 1498 error_message = _(": invalid membar mask number"); 1499 goto error; 1500 } 1501 } 1502 1503 opcode |= MEMBAR (kmask); 1504 continue; 1505 } 1506 1507 case '3': 1508 { 1509 int smask = 0; 1510 1511 if (! parse_const_expr_arg (&s, &smask)) 1512 { 1513 error_message = _(": invalid siam mode expression"); 1514 goto error; 1515 } 1516 if (smask < 0 || smask > 7) 1517 { 1518 error_message = _(": invalid siam mode number"); 1519 goto error; 1520 } 1521 opcode |= smask; 1522 continue; 1523 } 1524 1525 case '*': 1526 { 1527 int fcn = 0; 1528 1529 /* Parse a prefetch function. */ 1530 if (*s == '#') 1531 { 1532 if (! parse_keyword_arg (sparc_encode_prefetch, &s, &fcn)) 1533 { 1534 error_message = _(": invalid prefetch function name"); 1535 goto error; 1536 } 1537 } 1538 else 1539 { 1540 if (! parse_const_expr_arg (&s, &fcn)) 1541 { 1542 error_message = _(": invalid prefetch function expression"); 1543 goto error; 1544 } 1545 if (fcn < 0 || fcn > 31) 1546 { 1547 error_message = _(": invalid prefetch function number"); 1548 goto error; 1549 } 1550 } 1551 opcode |= RD (fcn); 1552 continue; 1553 } 1554 1555 case '!': 1556 case '?': 1557 /* Parse a sparc64 privileged register. */ 1558 if (*s == '%') 1559 { 1560 struct priv_reg_entry *p = priv_reg_table; 1561 unsigned int len = 9999999; /* Init to make gcc happy. */ 1562 1563 s += 1; 1564 while (p->name[0] > s[0]) 1565 p++; 1566 while (p->name[0] == s[0]) 1567 { 1568 len = strlen (p->name); 1569 if (strncmp (p->name, s, len) == 0) 1570 break; 1571 p++; 1572 } 1573 if (p->name[0] != s[0]) 1574 { 1575 error_message = _(": unrecognizable privileged register"); 1576 goto error; 1577 } 1578 if (*args == '?') 1579 opcode |= (p->regnum << 14); 1580 else 1581 opcode |= (p->regnum << 25); 1582 s += len; 1583 continue; 1584 } 1585 else 1586 { 1587 error_message = _(": unrecognizable privileged register"); 1588 goto error; 1589 } 1590 1591 case '$': 1592 case '%': 1593 /* Parse a sparc64 hyperprivileged register. */ 1594 if (*s == '%') 1595 { 1596 struct priv_reg_entry *p = hpriv_reg_table; 1597 unsigned int len = 9999999; /* Init to make gcc happy. */ 1598 1599 s += 1; 1600 while (p->name[0] > s[0]) 1601 p++; 1602 while (p->name[0] == s[0]) 1603 { 1604 len = strlen (p->name); 1605 if (strncmp (p->name, s, len) == 0) 1606 break; 1607 p++; 1608 } 1609 if (p->name[0] != s[0]) 1610 { 1611 error_message = _(": unrecognizable hyperprivileged register"); 1612 goto error; 1613 } 1614 if (*args == '$') 1615 opcode |= (p->regnum << 14); 1616 else 1617 opcode |= (p->regnum << 25); 1618 s += len; 1619 continue; 1620 } 1621 else 1622 { 1623 error_message = _(": unrecognizable hyperprivileged register"); 1624 goto error; 1625 } 1626 1627 case '_': 1628 case '/': 1629 /* Parse a v9a/v9b ancillary state register. */ 1630 if (*s == '%') 1631 { 1632 struct priv_reg_entry *p = v9a_asr_table; 1633 unsigned int len = 9999999; /* Init to make gcc happy. */ 1634 1635 s += 1; 1636 while (p->name[0] > s[0]) 1637 p++; 1638 while (p->name[0] == s[0]) 1639 { 1640 len = strlen (p->name); 1641 if (strncmp (p->name, s, len) == 0) 1642 break; 1643 p++; 1644 } 1645 if (p->name[0] != s[0]) 1646 { 1647 error_message = _(": unrecognizable v9a or v9b ancillary state register"); 1648 goto error; 1649 } 1650 if (*args == '/' && (p->regnum == 20 || p->regnum == 21)) 1651 { 1652 error_message = _(": rd on write only ancillary state register"); 1653 goto error; 1654 } 1655 if (p->regnum >= 24 1656 && (insn->architecture 1657 & SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9A))) 1658 { 1659 /* %sys_tick and %sys_tick_cmpr are v9bnotv9a */ 1660 error_message = _(": unrecognizable v9a ancillary state register"); 1661 goto error; 1662 } 1663 if (*args == '/') 1664 opcode |= (p->regnum << 14); 1665 else 1666 opcode |= (p->regnum << 25); 1667 s += len; 1668 continue; 1669 } 1670 else 1671 { 1672 error_message = _(": unrecognizable v9a or v9b ancillary state register"); 1673 goto error; 1674 } 1675 1676 case 'M': 1677 case 'm': 1678 if (strncmp (s, "%asr", 4) == 0) 1679 { 1680 s += 4; 1681 1682 if (ISDIGIT (*s)) 1683 { 1684 long num = 0; 1685 1686 while (ISDIGIT (*s)) 1687 { 1688 num = num * 10 + *s - '0'; 1689 ++s; 1690 } 1691 1692 if (current_architecture >= SPARC_OPCODE_ARCH_V9) 1693 { 1694 if (num < 16 || 31 < num) 1695 { 1696 error_message = _(": asr number must be between 16 and 31"); 1697 goto error; 1698 } 1699 } 1700 else 1701 { 1702 if (num < 0 || 31 < num) 1703 { 1704 error_message = _(": asr number must be between 0 and 31"); 1705 goto error; 1706 } 1707 } 1708 1709 opcode |= (*args == 'M' ? RS1 (num) : RD (num)); 1710 continue; 1711 } 1712 else 1713 { 1714 error_message = _(": expecting %asrN"); 1715 goto error; 1716 } 1717 } /* if %asr */ 1718 break; 1719 1720 case 'I': 1721 the_insn.reloc = BFD_RELOC_SPARC_11; 1722 goto immediate; 1723 1724 case 'j': 1725 the_insn.reloc = BFD_RELOC_SPARC_10; 1726 goto immediate; 1727 1728 case 'X': 1729 /* V8 systems don't understand BFD_RELOC_SPARC_5. */ 1730 if (SPARC_OPCODE_ARCH_V9_P (max_architecture)) 1731 the_insn.reloc = BFD_RELOC_SPARC_5; 1732 else 1733 the_insn.reloc = BFD_RELOC_SPARC13; 1734 /* These fields are unsigned, but for upward compatibility, 1735 allow negative values as well. */ 1736 goto immediate; 1737 1738 case 'Y': 1739 /* V8 systems don't understand BFD_RELOC_SPARC_6. */ 1740 if (SPARC_OPCODE_ARCH_V9_P (max_architecture)) 1741 the_insn.reloc = BFD_RELOC_SPARC_6; 1742 else 1743 the_insn.reloc = BFD_RELOC_SPARC13; 1744 /* These fields are unsigned, but for upward compatibility, 1745 allow negative values as well. */ 1746 goto immediate; 1747 1748 case 'k': 1749 the_insn.reloc = /* RELOC_WDISP2_14 */ BFD_RELOC_SPARC_WDISP16; 1750 the_insn.pcrel = 1; 1751 goto immediate; 1752 1753 case 'G': 1754 the_insn.reloc = BFD_RELOC_SPARC_WDISP19; 1755 the_insn.pcrel = 1; 1756 goto immediate; 1757 1758 case 'N': 1759 if (*s == 'p' && s[1] == 'n') 1760 { 1761 s += 2; 1762 continue; 1763 } 1764 break; 1765 1766 case 'T': 1767 if (*s == 'p' && s[1] == 't') 1768 { 1769 s += 2; 1770 continue; 1771 } 1772 break; 1773 1774 case 'z': 1775 if (*s == ' ') 1776 { 1777 ++s; 1778 } 1779 if (strncmp (s, "%icc", 4) == 0) 1780 { 1781 s += 4; 1782 continue; 1783 } 1784 break; 1785 1786 case 'Z': 1787 if (*s == ' ') 1788 { 1789 ++s; 1790 } 1791 if (strncmp (s, "%xcc", 4) == 0) 1792 { 1793 s += 4; 1794 continue; 1795 } 1796 break; 1797 1798 case '6': 1799 if (*s == ' ') 1800 { 1801 ++s; 1802 } 1803 if (strncmp (s, "%fcc0", 5) == 0) 1804 { 1805 s += 5; 1806 continue; 1807 } 1808 break; 1809 1810 case '7': 1811 if (*s == ' ') 1812 { 1813 ++s; 1814 } 1815 if (strncmp (s, "%fcc1", 5) == 0) 1816 { 1817 s += 5; 1818 continue; 1819 } 1820 break; 1821 1822 case '8': 1823 if (*s == ' ') 1824 { 1825 ++s; 1826 } 1827 if (strncmp (s, "%fcc2", 5) == 0) 1828 { 1829 s += 5; 1830 continue; 1831 } 1832 break; 1833 1834 case '9': 1835 if (*s == ' ') 1836 { 1837 ++s; 1838 } 1839 if (strncmp (s, "%fcc3", 5) == 0) 1840 { 1841 s += 5; 1842 continue; 1843 } 1844 break; 1845 1846 case 'P': 1847 if (strncmp (s, "%pc", 3) == 0) 1848 { 1849 s += 3; 1850 continue; 1851 } 1852 break; 1853 1854 case 'W': 1855 if (strncmp (s, "%tick", 5) == 0) 1856 { 1857 s += 5; 1858 continue; 1859 } 1860 break; 1861 1862 case '\0': /* End of args. */ 1863 if (s[0] == ',' && s[1] == '%') 1864 { 1865 static const struct tls_ops { 1866 /* The name as it appears in assembler. */ 1867 char *name; 1868 /* strlen (name), precomputed for speed */ 1869 int len; 1870 /* The reloc this pseudo-op translates to. */ 1871 int reloc; 1872 /* 1 if call. */ 1873 int call; 1874 } tls_ops[] = { 1875 { "tgd_add", 7, BFD_RELOC_SPARC_TLS_GD_ADD, 0 }, 1876 { "tgd_call", 8, BFD_RELOC_SPARC_TLS_GD_CALL, 1 }, 1877 { "tldm_add", 8, BFD_RELOC_SPARC_TLS_LDM_ADD, 0 }, 1878 { "tldm_call", 9, BFD_RELOC_SPARC_TLS_LDM_CALL, 1 }, 1879 { "tldo_add", 8, BFD_RELOC_SPARC_TLS_LDO_ADD, 0 }, 1880 { "tie_ldx", 7, BFD_RELOC_SPARC_TLS_IE_LDX, 0 }, 1881 { "tie_ld", 6, BFD_RELOC_SPARC_TLS_IE_LD, 0 }, 1882 { "tie_add", 7, BFD_RELOC_SPARC_TLS_IE_ADD, 0 } 1883 }; 1884 const struct tls_ops *o; 1885 char *s1; 1886 int npar = 0; 1887 1888 for (o = tls_ops; o->name; o++) 1889 if (strncmp (s + 2, o->name, o->len) == 0) 1890 break; 1891 if (o->name == NULL) 1892 break; 1893 1894 if (s[o->len + 2] != '(') 1895 { 1896 as_bad (_("Illegal operands: %%%s requires arguments in ()"), o->name); 1897 return special_case; 1898 } 1899 1900 if (! o->call && the_insn.reloc != BFD_RELOC_NONE) 1901 { 1902 as_bad (_("Illegal operands: %%%s cannot be used together with other relocs in the insn ()"), 1903 o->name); 1904 return special_case; 1905 } 1906 1907 if (o->call 1908 && (the_insn.reloc != BFD_RELOC_32_PCREL_S2 1909 || the_insn.exp.X_add_number != 0 1910 || the_insn.exp.X_add_symbol 1911 != symbol_find_or_make ("__tls_get_addr"))) 1912 { 1913 as_bad (_("Illegal operands: %%%s can be only used with call __tls_get_addr"), 1914 o->name); 1915 return special_case; 1916 } 1917 1918 the_insn.reloc = o->reloc; 1919 memset (&the_insn.exp, 0, sizeof (the_insn.exp)); 1920 s += o->len + 3; 1921 1922 for (s1 = s; *s1 && *s1 != ',' && *s1 != ']'; s1++) 1923 if (*s1 == '(') 1924 npar++; 1925 else if (*s1 == ')') 1926 { 1927 if (!npar) 1928 break; 1929 npar--; 1930 } 1931 1932 if (*s1 != ')') 1933 { 1934 as_bad (_("Illegal operands: %%%s requires arguments in ()"), o->name); 1935 return special_case; 1936 } 1937 1938 *s1 = '\0'; 1939 (void) get_expression (s); 1940 *s1 = ')'; 1941 s = s1 + 1; 1942 } 1943 if (*s == '\0') 1944 match = 1; 1945 break; 1946 1947 case '+': 1948 if (*s == '+') 1949 { 1950 ++s; 1951 continue; 1952 } 1953 if (*s == '-') 1954 { 1955 continue; 1956 } 1957 break; 1958 1959 case '[': /* These must match exactly. */ 1960 case ']': 1961 case ',': 1962 case ' ': 1963 if (*s++ == *args) 1964 continue; 1965 break; 1966 1967 case '#': /* Must be at least one digit. */ 1968 if (ISDIGIT (*s++)) 1969 { 1970 while (ISDIGIT (*s)) 1971 { 1972 ++s; 1973 } 1974 continue; 1975 } 1976 break; 1977 1978 case 'C': /* Coprocessor state register. */ 1979 if (strncmp (s, "%csr", 4) == 0) 1980 { 1981 s += 4; 1982 continue; 1983 } 1984 break; 1985 1986 case 'b': /* Next operand is a coprocessor register. */ 1987 case 'c': 1988 case 'D': 1989 if (*s++ == '%' && *s++ == 'c' && ISDIGIT (*s)) 1990 { 1991 mask = *s++; 1992 if (ISDIGIT (*s)) 1993 { 1994 mask = 10 * (mask - '0') + (*s++ - '0'); 1995 if (mask >= 32) 1996 { 1997 break; 1998 } 1999 } 2000 else 2001 { 2002 mask -= '0'; 2003 } 2004 switch (*args) 2005 { 2006 2007 case 'b': 2008 opcode |= mask << 14; 2009 continue; 2010 2011 case 'c': 2012 opcode |= mask; 2013 continue; 2014 2015 case 'D': 2016 opcode |= mask << 25; 2017 continue; 2018 } 2019 } 2020 break; 2021 2022 case 'r': /* next operand must be a register */ 2023 case 'O': 2024 case '1': 2025 case '2': 2026 case 'd': 2027 if (*s++ == '%') 2028 { 2029 switch (c = *s++) 2030 { 2031 2032 case 'f': /* frame pointer */ 2033 if (*s++ == 'p') 2034 { 2035 mask = 0x1e; 2036 break; 2037 } 2038 goto error; 2039 2040 case 'g': /* global register */ 2041 c = *s++; 2042 if (isoctal (c)) 2043 { 2044 mask = c - '0'; 2045 break; 2046 } 2047 goto error; 2048 2049 case 'i': /* in register */ 2050 c = *s++; 2051 if (isoctal (c)) 2052 { 2053 mask = c - '0' + 24; 2054 break; 2055 } 2056 goto error; 2057 2058 case 'l': /* local register */ 2059 c = *s++; 2060 if (isoctal (c)) 2061 { 2062 mask = (c - '0' + 16); 2063 break; 2064 } 2065 goto error; 2066 2067 case 'o': /* out register */ 2068 c = *s++; 2069 if (isoctal (c)) 2070 { 2071 mask = (c - '0' + 8); 2072 break; 2073 } 2074 goto error; 2075 2076 case 's': /* stack pointer */ 2077 if (*s++ == 'p') 2078 { 2079 mask = 0xe; 2080 break; 2081 } 2082 goto error; 2083 2084 case 'r': /* any register */ 2085 if (!ISDIGIT ((c = *s++))) 2086 { 2087 goto error; 2088 } 2089 /* FALLTHROUGH */ 2090 case '0': 2091 case '1': 2092 case '2': 2093 case '3': 2094 case '4': 2095 case '5': 2096 case '6': 2097 case '7': 2098 case '8': 2099 case '9': 2100 if (ISDIGIT (*s)) 2101 { 2102 if ((c = 10 * (c - '0') + (*s++ - '0')) >= 32) 2103 { 2104 goto error; 2105 } 2106 } 2107 else 2108 { 2109 c -= '0'; 2110 } 2111 mask = c; 2112 break; 2113 2114 default: 2115 goto error; 2116 } 2117 2118 if ((mask & ~1) == 2 && sparc_arch_size == 64 2119 && no_undeclared_regs && ! globals[mask]) 2120 as_bad (_("detected global register use not covered by .register pseudo-op")); 2121 2122 /* Got the register, now figure out where 2123 it goes in the opcode. */ 2124 switch (*args) 2125 { 2126 case '1': 2127 opcode |= mask << 14; 2128 continue; 2129 2130 case '2': 2131 opcode |= mask; 2132 continue; 2133 2134 case 'd': 2135 opcode |= mask << 25; 2136 continue; 2137 2138 case 'r': 2139 opcode |= (mask << 25) | (mask << 14); 2140 continue; 2141 2142 case 'O': 2143 opcode |= (mask << 25) | (mask << 0); 2144 continue; 2145 } 2146 } 2147 break; 2148 2149 case 'e': /* next operand is a floating point register */ 2150 case 'v': 2151 case 'V': 2152 2153 case 'f': 2154 case 'B': 2155 case 'R': 2156 2157 case 'g': 2158 case 'H': 2159 case 'J': 2160 { 2161 char format; 2162 2163 if (*s++ == '%' 2164 && ((format = *s) == 'f') 2165 && ISDIGIT (*++s)) 2166 { 2167 for (mask = 0; ISDIGIT (*s); ++s) 2168 { 2169 mask = 10 * mask + (*s - '0'); 2170 } /* read the number */ 2171 2172 if ((*args == 'v' 2173 || *args == 'B' 2174 || *args == 'H') 2175 && (mask & 1)) 2176 { 2177 break; 2178 } /* register must be even numbered */ 2179 2180 if ((*args == 'V' 2181 || *args == 'R' 2182 || *args == 'J') 2183 && (mask & 3)) 2184 { 2185 break; 2186 } /* register must be multiple of 4 */ 2187 2188 if (mask >= 64) 2189 { 2190 if (SPARC_OPCODE_ARCH_V9_P (max_architecture)) 2191 error_message = _(": There are only 64 f registers; [0-63]"); 2192 else 2193 error_message = _(": There are only 32 f registers; [0-31]"); 2194 goto error; 2195 } /* on error */ 2196 else if (mask >= 32) 2197 { 2198 if (SPARC_OPCODE_ARCH_V9_P (max_architecture)) 2199 { 2200 #if !defined(TE_OpenBSD) 2201 if (*args == 'e' || *args == 'f' || *args == 'g') 2202 { 2203 error_message 2204 = _(": There are only 32 single precision f registers; [0-31]"); 2205 goto error; 2206 } 2207 #endif 2208 v9_arg_p = 1; 2209 mask -= 31; /* wrap high bit */ 2210 } 2211 else 2212 { 2213 error_message = _(": There are only 32 f registers; [0-31]"); 2214 goto error; 2215 } 2216 } 2217 } 2218 else 2219 { 2220 break; 2221 } /* if not an 'f' register. */ 2222 2223 switch (*args) 2224 { 2225 case 'v': 2226 case 'V': 2227 case 'e': 2228 opcode |= RS1 (mask); 2229 continue; 2230 2231 case 'f': 2232 case 'B': 2233 case 'R': 2234 opcode |= RS2 (mask); 2235 continue; 2236 2237 case 'g': 2238 case 'H': 2239 case 'J': 2240 opcode |= RD (mask); 2241 continue; 2242 } /* Pack it in. */ 2243 2244 know (0); 2245 break; 2246 } /* float arg */ 2247 2248 case 'F': 2249 if (strncmp (s, "%fsr", 4) == 0) 2250 { 2251 s += 4; 2252 continue; 2253 } 2254 break; 2255 2256 case '0': /* 64 bit immediate (set, setsw, setx insn) */ 2257 the_insn.reloc = BFD_RELOC_NONE; /* reloc handled elsewhere */ 2258 goto immediate; 2259 2260 case 'l': /* 22 bit PC relative immediate */ 2261 the_insn.reloc = BFD_RELOC_SPARC_WDISP22; 2262 the_insn.pcrel = 1; 2263 goto immediate; 2264 2265 case 'L': /* 30 bit immediate */ 2266 the_insn.reloc = BFD_RELOC_32_PCREL_S2; 2267 the_insn.pcrel = 1; 2268 goto immediate; 2269 2270 case 'h': 2271 case 'n': /* 22 bit immediate */ 2272 the_insn.reloc = BFD_RELOC_SPARC22; 2273 goto immediate; 2274 2275 case 'i': /* 13 bit immediate */ 2276 the_insn.reloc = BFD_RELOC_SPARC13; 2277 2278 /* fallthrough */ 2279 2280 immediate: 2281 if (*s == ' ') 2282 s++; 2283 2284 { 2285 char *s1; 2286 char *op_arg = NULL; 2287 static expressionS op_exp; 2288 bfd_reloc_code_real_type old_reloc = the_insn.reloc; 2289 2290 /* Check for %hi, etc. */ 2291 if (*s == '%') 2292 { 2293 static const struct ops { 2294 /* The name as it appears in assembler. */ 2295 char *name; 2296 /* strlen (name), precomputed for speed */ 2297 int len; 2298 /* The reloc this pseudo-op translates to. */ 2299 int reloc; 2300 /* Non-zero if for v9 only. */ 2301 int v9_p; 2302 /* Non-zero if can be used in pc-relative contexts. */ 2303 int pcrel_p;/*FIXME:wip*/ 2304 } ops[] = { 2305 /* hix/lox must appear before hi/lo so %hix won't be 2306 mistaken for %hi. */ 2307 { "hix", 3, BFD_RELOC_SPARC_HIX22, 1, 0 }, 2308 { "lox", 3, BFD_RELOC_SPARC_LOX10, 1, 0 }, 2309 { "hi", 2, BFD_RELOC_HI22, 0, 1 }, 2310 { "lo", 2, BFD_RELOC_LO10, 0, 1 }, 2311 { "hh", 2, BFD_RELOC_SPARC_HH22, 1, 1 }, 2312 { "hm", 2, BFD_RELOC_SPARC_HM10, 1, 1 }, 2313 { "lm", 2, BFD_RELOC_SPARC_LM22, 1, 1 }, 2314 { "h44", 3, BFD_RELOC_SPARC_H44, 1, 0 }, 2315 { "m44", 3, BFD_RELOC_SPARC_M44, 1, 0 }, 2316 { "l44", 3, BFD_RELOC_SPARC_L44, 1, 0 }, 2317 { "uhi", 3, BFD_RELOC_SPARC_HH22, 1, 0 }, 2318 { "ulo", 3, BFD_RELOC_SPARC_HM10, 1, 0 }, 2319 { "tgd_hi22", 8, BFD_RELOC_SPARC_TLS_GD_HI22, 0, 0 }, 2320 { "tgd_lo10", 8, BFD_RELOC_SPARC_TLS_GD_LO10, 0, 0 }, 2321 { "tldm_hi22", 9, BFD_RELOC_SPARC_TLS_LDM_HI22, 0, 0 }, 2322 { "tldm_lo10", 9, BFD_RELOC_SPARC_TLS_LDM_LO10, 0, 0 }, 2323 { "tldo_hix22", 10, BFD_RELOC_SPARC_TLS_LDO_HIX22, 0, 2324 0 }, 2325 { "tldo_lox10", 10, BFD_RELOC_SPARC_TLS_LDO_LOX10, 0, 2326 0 }, 2327 { "tie_hi22", 8, BFD_RELOC_SPARC_TLS_IE_HI22, 0, 0 }, 2328 { "tie_lo10", 8, BFD_RELOC_SPARC_TLS_IE_LO10, 0, 0 }, 2329 { "tle_hix22", 9, BFD_RELOC_SPARC_TLS_LE_HIX22, 0, 0 }, 2330 { "tle_lox10", 9, BFD_RELOC_SPARC_TLS_LE_LOX10, 0, 0 }, 2331 { NULL, 0, 0, 0, 0 } 2332 }; 2333 const struct ops *o; 2334 2335 for (o = ops; o->name; o++) 2336 if (strncmp (s + 1, o->name, o->len) == 0) 2337 break; 2338 if (o->name == NULL) 2339 break; 2340 2341 if (s[o->len + 1] != '(') 2342 { 2343 as_bad (_("Illegal operands: %%%s requires arguments in ()"), o->name); 2344 return special_case; 2345 } 2346 2347 op_arg = o->name; 2348 the_insn.reloc = o->reloc; 2349 s += o->len + 2; 2350 v9_arg_p = o->v9_p; 2351 } 2352 2353 /* Note that if the get_expression() fails, we will still 2354 have created U entries in the symbol table for the 2355 'symbols' in the input string. Try not to create U 2356 symbols for registers, etc. */ 2357 2358 /* This stuff checks to see if the expression ends in 2359 +%reg. If it does, it removes the register from 2360 the expression, and re-sets 's' to point to the 2361 right place. */ 2362 2363 if (op_arg) 2364 { 2365 int npar = 0; 2366 2367 for (s1 = s; *s1 && *s1 != ',' && *s1 != ']'; s1++) 2368 if (*s1 == '(') 2369 npar++; 2370 else if (*s1 == ')') 2371 { 2372 if (!npar) 2373 break; 2374 npar--; 2375 } 2376 2377 if (*s1 != ')') 2378 { 2379 as_bad (_("Illegal operands: %%%s requires arguments in ()"), op_arg); 2380 return special_case; 2381 } 2382 2383 *s1 = '\0'; 2384 (void) get_expression (s); 2385 *s1 = ')'; 2386 s = s1 + 1; 2387 if (*s == ',' || *s == ']' || !*s) 2388 continue; 2389 if (*s != '+' && *s != '-') 2390 { 2391 as_bad (_("Illegal operands: Can't do arithmetics other than + and - involving %%%s()"), op_arg); 2392 return special_case; 2393 } 2394 *s1 = '0'; 2395 s = s1; 2396 op_exp = the_insn.exp; 2397 memset (&the_insn.exp, 0, sizeof (the_insn.exp)); 2398 } 2399 2400 for (s1 = s; *s1 && *s1 != ',' && *s1 != ']'; s1++) 2401 ; 2402 2403 if (s1 != s && ISDIGIT (s1[-1])) 2404 { 2405 if (s1[-2] == '%' && s1[-3] == '+') 2406 s1 -= 3; 2407 else if (strchr ("goli0123456789", s1[-2]) && s1[-3] == '%' && s1[-4] == '+') 2408 s1 -= 4; 2409 else 2410 s1 = NULL; 2411 if (s1) 2412 { 2413 *s1 = '\0'; 2414 if (op_arg && s1 == s + 1) 2415 the_insn.exp.X_op = O_absent; 2416 else 2417 (void) get_expression (s); 2418 *s1 = '+'; 2419 if (op_arg) 2420 *s = ')'; 2421 s = s1; 2422 } 2423 } 2424 else 2425 s1 = NULL; 2426 2427 if (!s1) 2428 { 2429 (void) get_expression (s); 2430 if (op_arg) 2431 *s = ')'; 2432 s = expr_end; 2433 } 2434 2435 if (op_arg) 2436 { 2437 the_insn.exp2 = the_insn.exp; 2438 the_insn.exp = op_exp; 2439 if (the_insn.exp2.X_op == O_absent) 2440 the_insn.exp2.X_op = O_illegal; 2441 else if (the_insn.exp.X_op == O_absent) 2442 { 2443 the_insn.exp = the_insn.exp2; 2444 the_insn.exp2.X_op = O_illegal; 2445 } 2446 else if (the_insn.exp.X_op == O_constant) 2447 { 2448 valueT val = the_insn.exp.X_add_number; 2449 switch (the_insn.reloc) 2450 { 2451 default: 2452 break; 2453 2454 case BFD_RELOC_SPARC_HH22: 2455 val = BSR (val, 32); 2456 /* Fall through. */ 2457 2458 case BFD_RELOC_SPARC_LM22: 2459 case BFD_RELOC_HI22: 2460 val = (val >> 10) & 0x3fffff; 2461 break; 2462 2463 case BFD_RELOC_SPARC_HM10: 2464 val = BSR (val, 32); 2465 /* Fall through. */ 2466 2467 case BFD_RELOC_LO10: 2468 val &= 0x3ff; 2469 break; 2470 2471 case BFD_RELOC_SPARC_H44: 2472 val >>= 22; 2473 val &= 0x3fffff; 2474 break; 2475 2476 case BFD_RELOC_SPARC_M44: 2477 val >>= 12; 2478 val &= 0x3ff; 2479 break; 2480 2481 case BFD_RELOC_SPARC_L44: 2482 val &= 0xfff; 2483 break; 2484 2485 case BFD_RELOC_SPARC_HIX22: 2486 val = ~val; 2487 val = (val >> 10) & 0x3fffff; 2488 break; 2489 2490 case BFD_RELOC_SPARC_LOX10: 2491 val = (val & 0x3ff) | 0x1c00; 2492 break; 2493 } 2494 the_insn.exp = the_insn.exp2; 2495 the_insn.exp.X_add_number += val; 2496 the_insn.exp2.X_op = O_illegal; 2497 the_insn.reloc = old_reloc; 2498 } 2499 else if (the_insn.exp2.X_op != O_constant) 2500 { 2501 as_bad (_("Illegal operands: Can't add non-constant expression to %%%s()"), op_arg); 2502 return special_case; 2503 } 2504 else 2505 { 2506 if (old_reloc != BFD_RELOC_SPARC13 2507 || the_insn.reloc != BFD_RELOC_LO10 2508 || sparc_arch_size != 64 2509 || sparc_pic_code) 2510 { 2511 as_bad (_("Illegal operands: Can't do arithmetics involving %%%s() of a relocatable symbol"), op_arg); 2512 return special_case; 2513 } 2514 the_insn.reloc = BFD_RELOC_SPARC_OLO10; 2515 } 2516 } 2517 } 2518 /* Check for constants that don't require emitting a reloc. */ 2519 if (the_insn.exp.X_op == O_constant 2520 && the_insn.exp.X_add_symbol == 0 2521 && the_insn.exp.X_op_symbol == 0) 2522 { 2523 /* For pc-relative call instructions, we reject 2524 constants to get better code. */ 2525 if (the_insn.pcrel 2526 && the_insn.reloc == BFD_RELOC_32_PCREL_S2 2527 && in_signed_range (the_insn.exp.X_add_number, 0x3fff)) 2528 { 2529 error_message = _(": PC-relative operand can't be a constant"); 2530 goto error; 2531 } 2532 2533 if (the_insn.reloc >= BFD_RELOC_SPARC_TLS_GD_HI22 2534 && the_insn.reloc <= BFD_RELOC_SPARC_TLS_TPOFF64) 2535 { 2536 error_message = _(": TLS operand can't be a constant"); 2537 goto error; 2538 } 2539 2540 /* Constants that won't fit are checked in md_apply_fix 2541 and bfd_install_relocation. 2542 ??? It would be preferable to install the constants 2543 into the insn here and save having to create a fixS 2544 for each one. There already exists code to handle 2545 all the various cases (e.g. in md_apply_fix and 2546 bfd_install_relocation) so duplicating all that code 2547 here isn't right. */ 2548 } 2549 2550 continue; 2551 2552 case 'a': 2553 if (*s++ == 'a') 2554 { 2555 opcode |= ANNUL; 2556 continue; 2557 } 2558 break; 2559 2560 case 'A': 2561 { 2562 int asi = 0; 2563 2564 /* Parse an asi. */ 2565 if (*s == '#') 2566 { 2567 if (! parse_keyword_arg (sparc_encode_asi, &s, &asi)) 2568 { 2569 error_message = _(": invalid ASI name"); 2570 goto error; 2571 } 2572 } 2573 else 2574 { 2575 if (! parse_const_expr_arg (&s, &asi)) 2576 { 2577 error_message = _(": invalid ASI expression"); 2578 goto error; 2579 } 2580 if (asi < 0 || asi > 255) 2581 { 2582 error_message = _(": invalid ASI number"); 2583 goto error; 2584 } 2585 } 2586 opcode |= ASI (asi); 2587 continue; 2588 } /* Alternate space. */ 2589 2590 case 'p': 2591 if (strncmp (s, "%psr", 4) == 0) 2592 { 2593 s += 4; 2594 continue; 2595 } 2596 break; 2597 2598 case 'q': /* Floating point queue. */ 2599 if (strncmp (s, "%fq", 3) == 0) 2600 { 2601 s += 3; 2602 continue; 2603 } 2604 break; 2605 2606 case 'Q': /* Coprocessor queue. */ 2607 if (strncmp (s, "%cq", 3) == 0) 2608 { 2609 s += 3; 2610 continue; 2611 } 2612 break; 2613 2614 case 'S': 2615 if (strcmp (str, "set") == 0 2616 || strcmp (str, "setuw") == 0) 2617 { 2618 special_case = SPECIAL_CASE_SET; 2619 continue; 2620 } 2621 else if (strcmp (str, "setsw") == 0) 2622 { 2623 special_case = SPECIAL_CASE_SETSW; 2624 continue; 2625 } 2626 else if (strcmp (str, "setx") == 0) 2627 { 2628 special_case = SPECIAL_CASE_SETX; 2629 continue; 2630 } 2631 else if (strncmp (str, "fdiv", 4) == 0) 2632 { 2633 special_case = SPECIAL_CASE_FDIV; 2634 continue; 2635 } 2636 break; 2637 2638 case 'o': 2639 if (strncmp (s, "%asi", 4) != 0) 2640 break; 2641 s += 4; 2642 continue; 2643 2644 case 's': 2645 if (strncmp (s, "%fprs", 5) != 0) 2646 break; 2647 s += 5; 2648 continue; 2649 2650 case 'E': 2651 if (strncmp (s, "%ccr", 4) != 0) 2652 break; 2653 s += 4; 2654 continue; 2655 2656 case 't': 2657 if (strncmp (s, "%tbr", 4) != 0) 2658 break; 2659 s += 4; 2660 continue; 2661 2662 case 'w': 2663 if (strncmp (s, "%wim", 4) != 0) 2664 break; 2665 s += 4; 2666 continue; 2667 2668 case 'x': 2669 { 2670 char *push = input_line_pointer; 2671 expressionS e; 2672 2673 input_line_pointer = s; 2674 expression (&e); 2675 if (e.X_op == O_constant) 2676 { 2677 int n = e.X_add_number; 2678 if (n != e.X_add_number || (n & ~0x1ff) != 0) 2679 as_bad (_("OPF immediate operand out of range (0-0x1ff)")); 2680 else 2681 opcode |= e.X_add_number << 5; 2682 } 2683 else 2684 as_bad (_("non-immediate OPF operand, ignored")); 2685 s = input_line_pointer; 2686 input_line_pointer = push; 2687 continue; 2688 } 2689 2690 case 'y': 2691 if (strncmp (s, "%y", 2) != 0) 2692 break; 2693 s += 2; 2694 continue; 2695 2696 case 'u': 2697 case 'U': 2698 { 2699 /* Parse a sparclet cpreg. */ 2700 int cpreg; 2701 if (! parse_keyword_arg (sparc_encode_sparclet_cpreg, &s, &cpreg)) 2702 { 2703 error_message = _(": invalid cpreg name"); 2704 goto error; 2705 } 2706 opcode |= (*args == 'U' ? RS1 (cpreg) : RD (cpreg)); 2707 continue; 2708 } 2709 2710 default: 2711 as_fatal (_("failed sanity check.")); 2712 } /* switch on arg code. */ 2713 2714 /* Break out of for() loop. */ 2715 break; 2716 } /* For each arg that we expect. */ 2717 2718 error: 2719 if (match == 0) 2720 { 2721 /* Args don't match. */ 2722 if (&insn[1] - sparc_opcodes < sparc_num_opcodes 2723 && (insn->name == insn[1].name 2724 || !strcmp (insn->name, insn[1].name))) 2725 { 2726 ++insn; 2727 s = argsStart; 2728 continue; 2729 } 2730 else 2731 { 2732 as_bad (_("Illegal operands%s"), error_message); 2733 return special_case; 2734 } 2735 } 2736 else 2737 { 2738 /* We have a match. Now see if the architecture is OK. */ 2739 int needed_arch_mask = insn->architecture; 2740 2741 if (v9_arg_p) 2742 { 2743 needed_arch_mask &= 2744 ~(SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9) - 1); 2745 if (! needed_arch_mask) 2746 needed_arch_mask = 2747 SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9); 2748 } 2749 2750 if (needed_arch_mask 2751 & SPARC_OPCODE_SUPPORTED (current_architecture)) 2752 /* OK. */ 2753 ; 2754 /* Can we bump up the architecture? */ 2755 else if (needed_arch_mask 2756 & SPARC_OPCODE_SUPPORTED (max_architecture)) 2757 { 2758 enum sparc_opcode_arch_val needed_architecture = 2759 sparc_ffs (SPARC_OPCODE_SUPPORTED (max_architecture) 2760 & needed_arch_mask); 2761 2762 assert (needed_architecture <= SPARC_OPCODE_ARCH_MAX); 2763 if (warn_on_bump 2764 && needed_architecture > warn_after_architecture) 2765 { 2766 as_warn (_("architecture bumped from \"%s\" to \"%s\" on \"%s\""), 2767 sparc_opcode_archs[current_architecture].name, 2768 sparc_opcode_archs[needed_architecture].name, 2769 str); 2770 warn_after_architecture = needed_architecture; 2771 } 2772 current_architecture = needed_architecture; 2773 } 2774 /* Conflict. */ 2775 /* ??? This seems to be a bit fragile. What if the next entry in 2776 the opcode table is the one we want and it is supported? 2777 It is possible to arrange the table today so that this can't 2778 happen but what about tomorrow? */ 2779 else 2780 { 2781 int arch, printed_one_p = 0; 2782 char *p; 2783 char required_archs[SPARC_OPCODE_ARCH_MAX * 16]; 2784 2785 /* Create a list of the architectures that support the insn. */ 2786 needed_arch_mask &= ~SPARC_OPCODE_SUPPORTED (max_architecture); 2787 p = required_archs; 2788 arch = sparc_ffs (needed_arch_mask); 2789 while ((1 << arch) <= needed_arch_mask) 2790 { 2791 if ((1 << arch) & needed_arch_mask) 2792 { 2793 if (printed_one_p) 2794 *p++ = '|'; 2795 strcpy (p, sparc_opcode_archs[arch].name); 2796 p += strlen (p); 2797 printed_one_p = 1; 2798 } 2799 ++arch; 2800 } 2801 2802 as_bad (_("Architecture mismatch on \"%s\"."), str); 2803 as_tsktsk (_(" (Requires %s; requested architecture is %s.)"), 2804 required_archs, 2805 sparc_opcode_archs[max_architecture].name); 2806 return special_case; 2807 } 2808 } /* If no match. */ 2809 2810 break; 2811 } /* Forever looking for a match. */ 2812 2813 the_insn.opcode = opcode; 2814 return special_case; 2815 } 2816 2817 /* Parse an argument that can be expressed as a keyword. 2818 (eg: #StoreStore or %ccfr). 2819 The result is a boolean indicating success. 2820 If successful, INPUT_POINTER is updated. */ 2821 2822 static int 2823 parse_keyword_arg (lookup_fn, input_pointerP, valueP) 2824 int (*lookup_fn) PARAMS ((const char *)); 2825 char **input_pointerP; 2826 int *valueP; 2827 { 2828 int value; 2829 char c, *p, *q; 2830 2831 p = *input_pointerP; 2832 for (q = p + (*p == '#' || *p == '%'); 2833 ISALNUM (*q) || *q == '_'; 2834 ++q) 2835 continue; 2836 c = *q; 2837 *q = 0; 2838 value = (*lookup_fn) (p); 2839 *q = c; 2840 if (value == -1) 2841 return 0; 2842 *valueP = value; 2843 *input_pointerP = q; 2844 return 1; 2845 } 2846 2847 /* Parse an argument that is a constant expression. 2848 The result is a boolean indicating success. */ 2849 2850 static int 2851 parse_const_expr_arg (input_pointerP, valueP) 2852 char **input_pointerP; 2853 int *valueP; 2854 { 2855 char *save = input_line_pointer; 2856 expressionS exp; 2857 2858 input_line_pointer = *input_pointerP; 2859 /* The next expression may be something other than a constant 2860 (say if we're not processing the right variant of the insn). 2861 Don't call expression unless we're sure it will succeed as it will 2862 signal an error (which we want to defer until later). */ 2863 /* FIXME: It might be better to define md_operand and have it recognize 2864 things like %asi, etc. but continuing that route through to the end 2865 is a lot of work. */ 2866 if (*input_line_pointer == '%') 2867 { 2868 input_line_pointer = save; 2869 return 0; 2870 } 2871 expression (&exp); 2872 *input_pointerP = input_line_pointer; 2873 input_line_pointer = save; 2874 if (exp.X_op != O_constant) 2875 return 0; 2876 *valueP = exp.X_add_number; 2877 return 1; 2878 } 2879 2880 /* Subroutine of sparc_ip to parse an expression. */ 2881 2882 static int 2883 get_expression (str) 2884 char *str; 2885 { 2886 char *save_in; 2887 segT seg; 2888 2889 save_in = input_line_pointer; 2890 input_line_pointer = str; 2891 seg = expression (&the_insn.exp); 2892 if (seg != absolute_section 2893 && seg != text_section 2894 && seg != data_section 2895 && seg != bss_section 2896 && seg != undefined_section) 2897 { 2898 the_insn.error = _("bad segment"); 2899 expr_end = input_line_pointer; 2900 input_line_pointer = save_in; 2901 return 1; 2902 } 2903 expr_end = input_line_pointer; 2904 input_line_pointer = save_in; 2905 return 0; 2906 } 2907 2908 /* Subroutine of md_assemble to output one insn. */ 2909 2910 static void 2911 output_insn (insn, the_insn) 2912 const struct sparc_opcode *insn; 2913 struct sparc_it *the_insn; 2914 { 2915 char *toP = frag_more (4); 2916 2917 /* Put out the opcode. */ 2918 if (INSN_BIG_ENDIAN) 2919 number_to_chars_bigendian (toP, (valueT) the_insn->opcode, 4); 2920 else 2921 number_to_chars_littleendian (toP, (valueT) the_insn->opcode, 4); 2922 2923 /* Put out the symbol-dependent stuff. */ 2924 if (the_insn->reloc != BFD_RELOC_NONE) 2925 { 2926 fixS *fixP = fix_new_exp (frag_now, /* Which frag. */ 2927 (toP - frag_now->fr_literal), /* Where. */ 2928 4, /* Size. */ 2929 &the_insn->exp, 2930 the_insn->pcrel, 2931 the_insn->reloc); 2932 /* Turn off overflow checking in fixup_segment. We'll do our 2933 own overflow checking in md_apply_fix. This is necessary because 2934 the insn size is 4 and fixup_segment will signal an overflow for 2935 large 8 byte quantities. */ 2936 fixP->fx_no_overflow = 1; 2937 if (the_insn->reloc == BFD_RELOC_SPARC_OLO10) 2938 fixP->tc_fix_data = the_insn->exp2.X_add_number; 2939 } 2940 2941 last_insn = insn; 2942 last_opcode = the_insn->opcode; 2943 2944 #ifdef OBJ_ELF 2945 dwarf2_emit_insn (4); 2946 #endif 2947 } 2948 2949 /* This is identical to the md_atof in m68k.c. I think this is right, 2950 but I'm not sure. 2951 2952 Turn a string in input_line_pointer into a floating point constant 2953 of type TYPE, and store the appropriate bytes in *LITP. The number 2954 of LITTLENUMS emitted is stored in *SIZEP. An error message is 2955 returned, or NULL on OK. */ 2956 2957 /* Equal to MAX_PRECISION in atof-ieee.c. */ 2958 #define MAX_LITTLENUMS 6 2959 2960 char * 2961 md_atof (type, litP, sizeP) 2962 char type; 2963 char *litP; 2964 int *sizeP; 2965 { 2966 int i, prec; 2967 LITTLENUM_TYPE words[MAX_LITTLENUMS]; 2968 char *t; 2969 2970 switch (type) 2971 { 2972 case 'f': 2973 case 'F': 2974 case 's': 2975 case 'S': 2976 prec = 2; 2977 break; 2978 2979 case 'd': 2980 case 'D': 2981 case 'r': 2982 case 'R': 2983 prec = 4; 2984 break; 2985 2986 case 'x': 2987 case 'X': 2988 prec = 6; 2989 break; 2990 2991 case 'p': 2992 case 'P': 2993 prec = 6; 2994 break; 2995 2996 default: 2997 *sizeP = 0; 2998 return _("Bad call to MD_ATOF()"); 2999 } 3000 3001 t = atof_ieee (input_line_pointer, type, words); 3002 if (t) 3003 input_line_pointer = t; 3004 *sizeP = prec * sizeof (LITTLENUM_TYPE); 3005 3006 if (target_big_endian) 3007 { 3008 for (i = 0; i < prec; i++) 3009 { 3010 md_number_to_chars (litP, (valueT) words[i], 3011 sizeof (LITTLENUM_TYPE)); 3012 litP += sizeof (LITTLENUM_TYPE); 3013 } 3014 } 3015 else 3016 { 3017 for (i = prec - 1; i >= 0; i--) 3018 { 3019 md_number_to_chars (litP, (valueT) words[i], 3020 sizeof (LITTLENUM_TYPE)); 3021 litP += sizeof (LITTLENUM_TYPE); 3022 } 3023 } 3024 3025 return 0; 3026 } 3027 3028 /* Write a value out to the object file, using the appropriate 3029 endianness. */ 3030 3031 void 3032 md_number_to_chars (buf, val, n) 3033 char *buf; 3034 valueT val; 3035 int n; 3036 { 3037 if (target_big_endian) 3038 number_to_chars_bigendian (buf, val, n); 3039 else if (target_little_endian_data 3040 && ((n == 4 || n == 2) && ~now_seg->flags & SEC_ALLOC)) 3041 /* Output debug words, which are not in allocated sections, as big 3042 endian. */ 3043 number_to_chars_bigendian (buf, val, n); 3044 else if (target_little_endian_data || ! target_big_endian) 3045 number_to_chars_littleendian (buf, val, n); 3046 } 3047 3048 /* Apply a fixS to the frags, now that we know the value it ought to 3049 hold. */ 3050 3051 void 3052 md_apply_fix (fixP, valP, segment) 3053 fixS *fixP; 3054 valueT *valP; 3055 segT segment ATTRIBUTE_UNUSED; 3056 { 3057 char *buf = fixP->fx_where + fixP->fx_frag->fr_literal; 3058 offsetT val = * (offsetT *) valP; 3059 long insn; 3060 3061 assert (fixP->fx_r_type < BFD_RELOC_UNUSED); 3062 3063 fixP->fx_addnumber = val; /* Remember value for emit_reloc. */ 3064 3065 #ifdef OBJ_ELF 3066 /* SPARC ELF relocations don't use an addend in the data field. */ 3067 if (fixP->fx_addsy != NULL) 3068 { 3069 switch (fixP->fx_r_type) 3070 { 3071 case BFD_RELOC_SPARC_TLS_GD_HI22: 3072 case BFD_RELOC_SPARC_TLS_GD_LO10: 3073 case BFD_RELOC_SPARC_TLS_GD_ADD: 3074 case BFD_RELOC_SPARC_TLS_GD_CALL: 3075 case BFD_RELOC_SPARC_TLS_LDM_HI22: 3076 case BFD_RELOC_SPARC_TLS_LDM_LO10: 3077 case BFD_RELOC_SPARC_TLS_LDM_ADD: 3078 case BFD_RELOC_SPARC_TLS_LDM_CALL: 3079 case BFD_RELOC_SPARC_TLS_LDO_HIX22: 3080 case BFD_RELOC_SPARC_TLS_LDO_LOX10: 3081 case BFD_RELOC_SPARC_TLS_LDO_ADD: 3082 case BFD_RELOC_SPARC_TLS_IE_HI22: 3083 case BFD_RELOC_SPARC_TLS_IE_LO10: 3084 case BFD_RELOC_SPARC_TLS_IE_LD: 3085 case BFD_RELOC_SPARC_TLS_IE_LDX: 3086 case BFD_RELOC_SPARC_TLS_IE_ADD: 3087 case BFD_RELOC_SPARC_TLS_LE_HIX22: 3088 case BFD_RELOC_SPARC_TLS_LE_LOX10: 3089 case BFD_RELOC_SPARC_TLS_DTPMOD32: 3090 case BFD_RELOC_SPARC_TLS_DTPMOD64: 3091 case BFD_RELOC_SPARC_TLS_DTPOFF32: 3092 case BFD_RELOC_SPARC_TLS_DTPOFF64: 3093 case BFD_RELOC_SPARC_TLS_TPOFF32: 3094 case BFD_RELOC_SPARC_TLS_TPOFF64: 3095 S_SET_THREAD_LOCAL (fixP->fx_addsy); 3096 3097 default: 3098 break; 3099 } 3100 3101 return; 3102 } 3103 #endif 3104 3105 /* This is a hack. There should be a better way to 3106 handle this. Probably in terms of howto fields, once 3107 we can look at these fixups in terms of howtos. */ 3108 if (fixP->fx_r_type == BFD_RELOC_32_PCREL_S2 && fixP->fx_addsy) 3109 val += fixP->fx_where + fixP->fx_frag->fr_address; 3110 3111 #ifdef OBJ_AOUT 3112 /* FIXME: More ridiculous gas reloc hacking. If we are going to 3113 generate a reloc, then we just want to let the reloc addend set 3114 the value. We do not want to also stuff the addend into the 3115 object file. Including the addend in the object file works when 3116 doing a static link, because the linker will ignore the object 3117 file contents. However, the dynamic linker does not ignore the 3118 object file contents. */ 3119 if (fixP->fx_addsy != NULL 3120 && fixP->fx_r_type != BFD_RELOC_32_PCREL_S2) 3121 val = 0; 3122 3123 /* When generating PIC code, we do not want an addend for a reloc 3124 against a local symbol. We adjust fx_addnumber to cancel out the 3125 value already included in val, and to also cancel out the 3126 adjustment which bfd_install_relocation will create. */ 3127 if (sparc_pic_code 3128 && fixP->fx_r_type != BFD_RELOC_32_PCREL_S2 3129 && fixP->fx_addsy != NULL 3130 && ! S_IS_COMMON (fixP->fx_addsy) 3131 && symbol_section_p (fixP->fx_addsy)) 3132 fixP->fx_addnumber -= 2 * S_GET_VALUE (fixP->fx_addsy); 3133 3134 /* When generating PIC code, we need to fiddle to get 3135 bfd_install_relocation to do the right thing for a PC relative 3136 reloc against a local symbol which we are going to keep. */ 3137 if (sparc_pic_code 3138 && fixP->fx_r_type == BFD_RELOC_32_PCREL_S2 3139 && fixP->fx_addsy != NULL 3140 && (S_IS_EXTERNAL (fixP->fx_addsy) 3141 || S_IS_WEAK (fixP->fx_addsy)) 3142 && S_IS_DEFINED (fixP->fx_addsy) 3143 && ! S_IS_COMMON (fixP->fx_addsy)) 3144 { 3145 val = 0; 3146 fixP->fx_addnumber -= 2 * S_GET_VALUE (fixP->fx_addsy); 3147 } 3148 #endif 3149 3150 /* If this is a data relocation, just output VAL. */ 3151 3152 if (fixP->fx_r_type == BFD_RELOC_16 3153 || fixP->fx_r_type == BFD_RELOC_SPARC_UA16) 3154 { 3155 md_number_to_chars (buf, val, 2); 3156 } 3157 else if (fixP->fx_r_type == BFD_RELOC_32 3158 || fixP->fx_r_type == BFD_RELOC_SPARC_UA32 3159 || fixP->fx_r_type == BFD_RELOC_SPARC_REV32) 3160 { 3161 md_number_to_chars (buf, val, 4); 3162 } 3163 else if (fixP->fx_r_type == BFD_RELOC_64 3164 || fixP->fx_r_type == BFD_RELOC_SPARC_UA64) 3165 { 3166 md_number_to_chars (buf, val, 8); 3167 } 3168 else if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT 3169 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY) 3170 { 3171 fixP->fx_done = 0; 3172 return; 3173 } 3174 else 3175 { 3176 /* It's a relocation against an instruction. */ 3177 3178 if (INSN_BIG_ENDIAN) 3179 insn = bfd_getb32 ((unsigned char *) buf); 3180 else 3181 insn = bfd_getl32 ((unsigned char *) buf); 3182 3183 switch (fixP->fx_r_type) 3184 { 3185 case BFD_RELOC_32_PCREL_S2: 3186 val = val >> 2; 3187 /* FIXME: This increment-by-one deserves a comment of why it's 3188 being done! */ 3189 if (! sparc_pic_code 3190 || fixP->fx_addsy == NULL 3191 || symbol_section_p (fixP->fx_addsy)) 3192 ++val; 3193 3194 insn |= val & 0x3fffffff; 3195 3196 /* See if we have a delay slot. */ 3197 if (sparc_relax && fixP->fx_where + 8 <= fixP->fx_frag->fr_fix) 3198 { 3199 #define G0 0 3200 #define O7 15 3201 #define XCC (2 << 20) 3202 #define COND(x) (((x)&0xf)<<25) 3203 #define CONDA COND(0x8) 3204 #define INSN_BPA (F2(0,1) | CONDA | BPRED | XCC) 3205 #define INSN_BA (F2(0,2) | CONDA) 3206 #define INSN_OR F3(2, 0x2, 0) 3207 #define INSN_NOP F2(0,4) 3208 3209 long delay; 3210 3211 /* If the instruction is a call with either: 3212 restore 3213 arithmetic instruction with rd == %o7 3214 where rs1 != %o7 and rs2 if it is register != %o7 3215 then we can optimize if the call destination is near 3216 by changing the call into a branch always. */ 3217 if (INSN_BIG_ENDIAN) 3218 delay = bfd_getb32 ((unsigned char *) buf + 4); 3219 else 3220 delay = bfd_getl32 ((unsigned char *) buf + 4); 3221 if ((insn & OP (~0)) != OP (1) || (delay & OP (~0)) != OP (2)) 3222 break; 3223 if ((delay & OP3 (~0)) != OP3 (0x3d) /* Restore. */ 3224 && ((delay & OP3 (0x28)) != 0 /* Arithmetic. */ 3225 || ((delay & RD (~0)) != RD (O7)))) 3226 break; 3227 if ((delay & RS1 (~0)) == RS1 (O7) 3228 || ((delay & F3I (~0)) == 0 3229 && (delay & RS2 (~0)) == RS2 (O7))) 3230 break; 3231 /* Ensure the branch will fit into simm22. */ 3232 if ((val & 0x3fe00000) 3233 && (val & 0x3fe00000) != 0x3fe00000) 3234 break; 3235 /* Check if the arch is v9 and branch will fit 3236 into simm19. */ 3237 if (((val & 0x3c0000) == 0 3238 || (val & 0x3c0000) == 0x3c0000) 3239 && (sparc_arch_size == 64 3240 || current_architecture >= SPARC_OPCODE_ARCH_V9)) 3241 /* ba,pt %xcc */ 3242 insn = INSN_BPA | (val & 0x7ffff); 3243 else 3244 /* ba */ 3245 insn = INSN_BA | (val & 0x3fffff); 3246 if (fixP->fx_where >= 4 3247 && ((delay & (0xffffffff ^ RS1 (~0))) 3248 == (INSN_OR | RD (O7) | RS2 (G0)))) 3249 { 3250 long setter; 3251 int reg; 3252 3253 if (INSN_BIG_ENDIAN) 3254 setter = bfd_getb32 ((unsigned char *) buf - 4); 3255 else 3256 setter = bfd_getl32 ((unsigned char *) buf - 4); 3257 if ((setter & (0xffffffff ^ RD (~0))) 3258 != (INSN_OR | RS1 (O7) | RS2 (G0))) 3259 break; 3260 /* The sequence was 3261 or %o7, %g0, %rN 3262 call foo 3263 or %rN, %g0, %o7 3264 3265 If call foo was replaced with ba, replace 3266 or %rN, %g0, %o7 with nop. */ 3267 reg = (delay & RS1 (~0)) >> 14; 3268 if (reg != ((setter & RD (~0)) >> 25) 3269 || reg == G0 || reg == O7) 3270 break; 3271 3272 if (INSN_BIG_ENDIAN) 3273 bfd_putb32 (INSN_NOP, (unsigned char *) buf + 4); 3274 else 3275 bfd_putl32 (INSN_NOP, (unsigned char *) buf + 4); 3276 } 3277 } 3278 break; 3279 3280 case BFD_RELOC_SPARC_11: 3281 if (! in_signed_range (val, 0x7ff)) 3282 as_bad_where (fixP->fx_file, fixP->fx_line, 3283 _("relocation overflow")); 3284 insn |= val & 0x7ff; 3285 break; 3286 3287 case BFD_RELOC_SPARC_10: 3288 if (! in_signed_range (val, 0x3ff)) 3289 as_bad_where (fixP->fx_file, fixP->fx_line, 3290 _("relocation overflow")); 3291 insn |= val & 0x3ff; 3292 break; 3293 3294 case BFD_RELOC_SPARC_7: 3295 if (! in_bitfield_range (val, 0x7f)) 3296 as_bad_where (fixP->fx_file, fixP->fx_line, 3297 _("relocation overflow")); 3298 insn |= val & 0x7f; 3299 break; 3300 3301 case BFD_RELOC_SPARC_6: 3302 if (! in_bitfield_range (val, 0x3f)) 3303 as_bad_where (fixP->fx_file, fixP->fx_line, 3304 _("relocation overflow")); 3305 insn |= val & 0x3f; 3306 break; 3307 3308 case BFD_RELOC_SPARC_5: 3309 if (! in_bitfield_range (val, 0x1f)) 3310 as_bad_where (fixP->fx_file, fixP->fx_line, 3311 _("relocation overflow")); 3312 insn |= val & 0x1f; 3313 break; 3314 3315 case BFD_RELOC_SPARC_WDISP16: 3316 /* FIXME: simplify. */ 3317 if (((val > 0) && (val & ~0x3fffc)) 3318 || ((val < 0) && (~(val - 1) & ~0x3fffc))) 3319 as_bad_where (fixP->fx_file, fixP->fx_line, 3320 _("relocation overflow")); 3321 /* FIXME: The +1 deserves a comment. */ 3322 val = (val >> 2) + 1; 3323 insn |= ((val & 0xc000) << 6) | (val & 0x3fff); 3324 break; 3325 3326 case BFD_RELOC_SPARC_WDISP19: 3327 /* FIXME: simplify. */ 3328 if (((val > 0) && (val & ~0x1ffffc)) 3329 || ((val < 0) && (~(val - 1) & ~0x1ffffc))) 3330 as_bad_where (fixP->fx_file, fixP->fx_line, 3331 _("relocation overflow")); 3332 /* FIXME: The +1 deserves a comment. */ 3333 val = (val >> 2) + 1; 3334 insn |= val & 0x7ffff; 3335 break; 3336 3337 case BFD_RELOC_SPARC_HH22: 3338 val = BSR (val, 32); 3339 /* Fall through. */ 3340 3341 case BFD_RELOC_SPARC_LM22: 3342 case BFD_RELOC_HI22: 3343 if (!fixP->fx_addsy) 3344 insn |= (val >> 10) & 0x3fffff; 3345 else 3346 /* FIXME: Need comment explaining why we do this. */ 3347 insn &= ~0xffff; 3348 break; 3349 3350 case BFD_RELOC_SPARC22: 3351 if (val & ~0x003fffff) 3352 as_bad_where (fixP->fx_file, fixP->fx_line, 3353 _("relocation overflow")); 3354 insn |= (val & 0x3fffff); 3355 break; 3356 3357 case BFD_RELOC_SPARC_HM10: 3358 val = BSR (val, 32); 3359 /* Fall through. */ 3360 3361 case BFD_RELOC_LO10: 3362 if (!fixP->fx_addsy) 3363 insn |= val & 0x3ff; 3364 else 3365 /* FIXME: Need comment explaining why we do this. */ 3366 insn &= ~0xff; 3367 break; 3368 3369 case BFD_RELOC_SPARC_OLO10: 3370 val &= 0x3ff; 3371 val += fixP->tc_fix_data; 3372 /* Fall through. */ 3373 3374 case BFD_RELOC_SPARC13: 3375 if (! in_signed_range (val, 0x1fff)) 3376 as_bad_where (fixP->fx_file, fixP->fx_line, 3377 _("relocation overflow")); 3378 insn |= val & 0x1fff; 3379 break; 3380 3381 case BFD_RELOC_SPARC_WDISP22: 3382 val = (val >> 2) + 1; 3383 /* Fall through. */ 3384 case BFD_RELOC_SPARC_BASE22: 3385 insn |= val & 0x3fffff; 3386 break; 3387 3388 case BFD_RELOC_SPARC_H44: 3389 if (!fixP->fx_addsy) 3390 { 3391 bfd_vma tval = val; 3392 tval >>= 22; 3393 insn |= tval & 0x3fffff; 3394 } 3395 break; 3396 3397 case BFD_RELOC_SPARC_M44: 3398 if (!fixP->fx_addsy) 3399 insn |= (val >> 12) & 0x3ff; 3400 break; 3401 3402 case BFD_RELOC_SPARC_L44: 3403 if (!fixP->fx_addsy) 3404 insn |= val & 0xfff; 3405 break; 3406 3407 case BFD_RELOC_SPARC_HIX22: 3408 if (!fixP->fx_addsy) 3409 { 3410 val ^= ~(offsetT) 0; 3411 insn |= (val >> 10) & 0x3fffff; 3412 } 3413 break; 3414 3415 case BFD_RELOC_SPARC_LOX10: 3416 if (!fixP->fx_addsy) 3417 insn |= 0x1c00 | (val & 0x3ff); 3418 break; 3419 3420 case BFD_RELOC_NONE: 3421 default: 3422 as_bad_where (fixP->fx_file, fixP->fx_line, 3423 _("bad or unhandled relocation type: 0x%02x"), 3424 fixP->fx_r_type); 3425 break; 3426 } 3427 3428 if (INSN_BIG_ENDIAN) 3429 bfd_putb32 (insn, (unsigned char *) buf); 3430 else 3431 bfd_putl32 (insn, (unsigned char *) buf); 3432 } 3433 3434 /* Are we finished with this relocation now? */ 3435 if (fixP->fx_addsy == 0 && !fixP->fx_pcrel) 3436 fixP->fx_done = 1; 3437 } 3438 3439 /* Translate internal representation of relocation info to BFD target 3440 format. */ 3441 3442 arelent ** 3443 tc_gen_reloc (section, fixp) 3444 asection *section ATTRIBUTE_UNUSED; 3445 fixS *fixp; 3446 { 3447 static arelent *relocs[3]; 3448 arelent *reloc; 3449 bfd_reloc_code_real_type code; 3450 3451 relocs[0] = reloc = (arelent *) xmalloc (sizeof (arelent)); 3452 relocs[1] = NULL; 3453 3454 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); 3455 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); 3456 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; 3457 3458 switch (fixp->fx_r_type) 3459 { 3460 case BFD_RELOC_16: 3461 case BFD_RELOC_32: 3462 case BFD_RELOC_HI22: 3463 case BFD_RELOC_LO10: 3464 case BFD_RELOC_32_PCREL_S2: 3465 case BFD_RELOC_SPARC13: 3466 case BFD_RELOC_SPARC22: 3467 case BFD_RELOC_SPARC_BASE13: 3468 case BFD_RELOC_SPARC_WDISP16: 3469 case BFD_RELOC_SPARC_WDISP19: 3470 case BFD_RELOC_SPARC_WDISP22: 3471 case BFD_RELOC_64: 3472 case BFD_RELOC_SPARC_5: 3473 case BFD_RELOC_SPARC_6: 3474 case BFD_RELOC_SPARC_7: 3475 case BFD_RELOC_SPARC_10: 3476 case BFD_RELOC_SPARC_11: 3477 case BFD_RELOC_SPARC_HH22: 3478 case BFD_RELOC_SPARC_HM10: 3479 case BFD_RELOC_SPARC_LM22: 3480 case BFD_RELOC_SPARC_PC_HH22: 3481 case BFD_RELOC_SPARC_PC_HM10: 3482 case BFD_RELOC_SPARC_PC_LM22: 3483 case BFD_RELOC_SPARC_H44: 3484 case BFD_RELOC_SPARC_M44: 3485 case BFD_RELOC_SPARC_L44: 3486 case BFD_RELOC_SPARC_HIX22: 3487 case BFD_RELOC_SPARC_LOX10: 3488 case BFD_RELOC_SPARC_REV32: 3489 case BFD_RELOC_SPARC_OLO10: 3490 case BFD_RELOC_SPARC_UA16: 3491 case BFD_RELOC_SPARC_UA32: 3492 case BFD_RELOC_SPARC_UA64: 3493 case BFD_RELOC_8_PCREL: 3494 case BFD_RELOC_16_PCREL: 3495 case BFD_RELOC_32_PCREL: 3496 case BFD_RELOC_64_PCREL: 3497 case BFD_RELOC_SPARC_PLT32: 3498 case BFD_RELOC_SPARC_PLT64: 3499 case BFD_RELOC_VTABLE_ENTRY: 3500 case BFD_RELOC_VTABLE_INHERIT: 3501 case BFD_RELOC_SPARC_TLS_GD_HI22: 3502 case BFD_RELOC_SPARC_TLS_GD_LO10: 3503 case BFD_RELOC_SPARC_TLS_GD_ADD: 3504 case BFD_RELOC_SPARC_TLS_GD_CALL: 3505 case BFD_RELOC_SPARC_TLS_LDM_HI22: 3506 case BFD_RELOC_SPARC_TLS_LDM_LO10: 3507 case BFD_RELOC_SPARC_TLS_LDM_ADD: 3508 case BFD_RELOC_SPARC_TLS_LDM_CALL: 3509 case BFD_RELOC_SPARC_TLS_LDO_HIX22: 3510 case BFD_RELOC_SPARC_TLS_LDO_LOX10: 3511 case BFD_RELOC_SPARC_TLS_LDO_ADD: 3512 case BFD_RELOC_SPARC_TLS_IE_HI22: 3513 case BFD_RELOC_SPARC_TLS_IE_LO10: 3514 case BFD_RELOC_SPARC_TLS_IE_LD: 3515 case BFD_RELOC_SPARC_TLS_IE_LDX: 3516 case BFD_RELOC_SPARC_TLS_IE_ADD: 3517 case BFD_RELOC_SPARC_TLS_LE_HIX22: 3518 case BFD_RELOC_SPARC_TLS_LE_LOX10: 3519 case BFD_RELOC_SPARC_TLS_DTPOFF32: 3520 case BFD_RELOC_SPARC_TLS_DTPOFF64: 3521 code = fixp->fx_r_type; 3522 break; 3523 default: 3524 abort (); 3525 return NULL; 3526 } 3527 3528 #if defined (OBJ_ELF) || defined (OBJ_AOUT) 3529 /* If we are generating PIC code, we need to generate a different 3530 set of relocs. */ 3531 3532 #ifdef OBJ_ELF 3533 #define GOT_NAME "_GLOBAL_OFFSET_TABLE_" 3534 #else 3535 #define GOT_NAME "__GLOBAL_OFFSET_TABLE_" 3536 #endif 3537 #ifdef TE_VXWORKS 3538 #define GOTT_BASE "__GOTT_BASE__" 3539 #define GOTT_INDEX "__GOTT_INDEX__" 3540 #endif 3541 3542 /* This code must be parallel to the OBJ_ELF tc_fix_adjustable. */ 3543 3544 if (sparc_pic_code) 3545 { 3546 switch (code) 3547 { 3548 case BFD_RELOC_32_PCREL_S2: 3549 if (generic_force_reloc (fixp)) 3550 code = BFD_RELOC_SPARC_WPLT30; 3551 break; 3552 case BFD_RELOC_HI22: 3553 code = BFD_RELOC_SPARC_GOT22; 3554 if (fixp->fx_addsy != NULL) 3555 { 3556 if (strcmp (S_GET_NAME (fixp->fx_addsy), GOT_NAME) == 0) 3557 code = BFD_RELOC_SPARC_PC22; 3558 #ifdef TE_VXWORKS 3559 if (strcmp (S_GET_NAME (fixp->fx_addsy), GOTT_BASE) == 0 3560 || strcmp (S_GET_NAME (fixp->fx_addsy), GOTT_INDEX) == 0) 3561 code = BFD_RELOC_HI22; /* Unchanged. */ 3562 #endif 3563 } 3564 break; 3565 case BFD_RELOC_LO10: 3566 code = BFD_RELOC_SPARC_GOT10; 3567 if (fixp->fx_addsy != NULL) 3568 { 3569 if (strcmp (S_GET_NAME (fixp->fx_addsy), GOT_NAME) == 0) 3570 code = BFD_RELOC_SPARC_PC10; 3571 #ifdef TE_VXWORKS 3572 if (strcmp (S_GET_NAME (fixp->fx_addsy), GOTT_BASE) == 0 3573 || strcmp (S_GET_NAME (fixp->fx_addsy), GOTT_INDEX) == 0) 3574 code = BFD_RELOC_LO10; /* Unchanged. */ 3575 #endif 3576 } 3577 break; 3578 case BFD_RELOC_SPARC13: 3579 code = BFD_RELOC_SPARC_GOT13; 3580 break; 3581 default: 3582 break; 3583 } 3584 } 3585 #endif /* defined (OBJ_ELF) || defined (OBJ_AOUT) */ 3586 3587 if (code == BFD_RELOC_SPARC_OLO10) 3588 reloc->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_LO10); 3589 else 3590 reloc->howto = bfd_reloc_type_lookup (stdoutput, code); 3591 if (reloc->howto == 0) 3592 { 3593 as_bad_where (fixp->fx_file, fixp->fx_line, 3594 _("internal error: can't export reloc type %d (`%s')"), 3595 fixp->fx_r_type, bfd_get_reloc_code_name (code)); 3596 xfree (reloc); 3597 relocs[0] = NULL; 3598 return relocs; 3599 } 3600 3601 /* @@ Why fx_addnumber sometimes and fx_offset other times? */ 3602 #ifdef OBJ_AOUT 3603 3604 if (reloc->howto->pc_relative == 0 3605 || code == BFD_RELOC_SPARC_PC10 3606 || code == BFD_RELOC_SPARC_PC22) 3607 reloc->addend = fixp->fx_addnumber; 3608 else if (sparc_pic_code 3609 && fixp->fx_r_type == BFD_RELOC_32_PCREL_S2 3610 && fixp->fx_addsy != NULL 3611 && (S_IS_EXTERNAL (fixp->fx_addsy) 3612 || S_IS_WEAK (fixp->fx_addsy)) 3613 && S_IS_DEFINED (fixp->fx_addsy) 3614 && ! S_IS_COMMON (fixp->fx_addsy)) 3615 reloc->addend = fixp->fx_addnumber; 3616 else 3617 reloc->addend = fixp->fx_offset - reloc->address; 3618 3619 #else /* elf or coff */ 3620 3621 if (code != BFD_RELOC_32_PCREL_S2 3622 && code != BFD_RELOC_SPARC_WDISP22 3623 && code != BFD_RELOC_SPARC_WDISP16 3624 && code != BFD_RELOC_SPARC_WDISP19 3625 && code != BFD_RELOC_SPARC_WPLT30 3626 && code != BFD_RELOC_SPARC_TLS_GD_CALL 3627 && code != BFD_RELOC_SPARC_TLS_LDM_CALL) 3628 reloc->addend = fixp->fx_addnumber; 3629 else if (symbol_section_p (fixp->fx_addsy)) 3630 reloc->addend = (section->vma 3631 + fixp->fx_addnumber 3632 + md_pcrel_from (fixp)); 3633 else 3634 reloc->addend = fixp->fx_offset; 3635 #endif 3636 3637 /* We expand R_SPARC_OLO10 to R_SPARC_LO10 and R_SPARC_13 3638 on the same location. */ 3639 if (code == BFD_RELOC_SPARC_OLO10) 3640 { 3641 relocs[1] = reloc = (arelent *) xmalloc (sizeof (arelent)); 3642 relocs[2] = NULL; 3643 3644 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); 3645 *reloc->sym_ptr_ptr 3646 = symbol_get_bfdsym (section_symbol (absolute_section)); 3647 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; 3648 reloc->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_SPARC13); 3649 reloc->addend = fixp->tc_fix_data; 3650 } 3651 3652 return relocs; 3653 } 3654 3655 /* We have no need to default values of symbols. */ 3656 3657 symbolS * 3658 md_undefined_symbol (name) 3659 char *name ATTRIBUTE_UNUSED; 3660 { 3661 return 0; 3662 } 3663 3664 /* Round up a section size to the appropriate boundary. */ 3665 3666 valueT 3667 md_section_align (segment, size) 3668 segT segment ATTRIBUTE_UNUSED; 3669 valueT size; 3670 { 3671 #ifndef OBJ_ELF 3672 /* This is not right for ELF; a.out wants it, and COFF will force 3673 the alignment anyways. */ 3674 valueT align = ((valueT) 1 3675 << (valueT) bfd_get_section_alignment (stdoutput, segment)); 3676 valueT newsize; 3677 3678 /* Turn alignment value into a mask. */ 3679 align--; 3680 newsize = (size + align) & ~align; 3681 return newsize; 3682 #else 3683 return size; 3684 #endif 3685 } 3686 3687 /* Exactly what point is a PC-relative offset relative TO? 3688 On the sparc, they're relative to the address of the offset, plus 3689 its size. This gets us to the following instruction. 3690 (??? Is this right? FIXME-SOON) */ 3691 long 3692 md_pcrel_from (fixP) 3693 fixS *fixP; 3694 { 3695 long ret; 3696 3697 ret = fixP->fx_where + fixP->fx_frag->fr_address; 3698 if (! sparc_pic_code 3699 || fixP->fx_addsy == NULL 3700 || symbol_section_p (fixP->fx_addsy)) 3701 ret += fixP->fx_size; 3702 return ret; 3703 } 3704 3705 /* Return log2 (VALUE), or -1 if VALUE is not an exact positive power 3706 of two. */ 3707 3708 static int 3709 mylog2 (value) 3710 int value; 3711 { 3712 int shift; 3713 3714 if (value <= 0) 3715 return -1; 3716 3717 for (shift = 0; (value & 1) == 0; value >>= 1) 3718 ++shift; 3719 3720 return (value == 1) ? shift : -1; 3721 } 3722 3723 /* Sort of like s_lcomm. */ 3724 3725 #ifndef OBJ_ELF 3726 static int max_alignment = 15; 3727 #endif 3728 3729 static void 3730 s_reserve (ignore) 3731 int ignore ATTRIBUTE_UNUSED; 3732 { 3733 char *name; 3734 char *p; 3735 char c; 3736 int align; 3737 int size; 3738 int temp; 3739 symbolS *symbolP; 3740 3741 name = input_line_pointer; 3742 c = get_symbol_end (); 3743 p = input_line_pointer; 3744 *p = c; 3745 SKIP_WHITESPACE (); 3746 3747 if (*input_line_pointer != ',') 3748 { 3749 as_bad (_("Expected comma after name")); 3750 ignore_rest_of_line (); 3751 return; 3752 } 3753 3754 ++input_line_pointer; 3755 3756 if ((size = get_absolute_expression ()) < 0) 3757 { 3758 as_bad (_("BSS length (%d.) <0! Ignored."), size); 3759 ignore_rest_of_line (); 3760 return; 3761 } /* Bad length. */ 3762 3763 *p = 0; 3764 symbolP = symbol_find_or_make (name); 3765 *p = c; 3766 3767 if (strncmp (input_line_pointer, ",\"bss\"", 6) != 0 3768 && strncmp (input_line_pointer, ",\".bss\"", 7) != 0) 3769 { 3770 as_bad (_("bad .reserve segment -- expected BSS segment")); 3771 return; 3772 } 3773 3774 if (input_line_pointer[2] == '.') 3775 input_line_pointer += 7; 3776 else 3777 input_line_pointer += 6; 3778 SKIP_WHITESPACE (); 3779 3780 if (*input_line_pointer == ',') 3781 { 3782 ++input_line_pointer; 3783 3784 SKIP_WHITESPACE (); 3785 if (*input_line_pointer == '\n') 3786 { 3787 as_bad (_("missing alignment")); 3788 ignore_rest_of_line (); 3789 return; 3790 } 3791 3792 align = (int) get_absolute_expression (); 3793 3794 #ifndef OBJ_ELF 3795 if (align > max_alignment) 3796 { 3797 align = max_alignment; 3798 as_warn (_("alignment too large; assuming %d"), align); 3799 } 3800 #endif 3801 3802 if (align < 0) 3803 { 3804 as_bad (_("negative alignment")); 3805 ignore_rest_of_line (); 3806 return; 3807 } 3808 3809 if (align != 0) 3810 { 3811 temp = mylog2 (align); 3812 if (temp < 0) 3813 { 3814 as_bad (_("alignment not a power of 2")); 3815 ignore_rest_of_line (); 3816 return; 3817 } 3818 3819 align = temp; 3820 } 3821 3822 record_alignment (bss_section, align); 3823 } 3824 else 3825 align = 0; 3826 3827 if (!S_IS_DEFINED (symbolP) 3828 #ifdef OBJ_AOUT 3829 && S_GET_OTHER (symbolP) == 0 3830 && S_GET_DESC (symbolP) == 0 3831 #endif 3832 ) 3833 { 3834 if (! need_pass_2) 3835 { 3836 char *pfrag; 3837 segT current_seg = now_seg; 3838 subsegT current_subseg = now_subseg; 3839 3840 /* Switch to bss. */ 3841 subseg_set (bss_section, 1); 3842 3843 if (align) 3844 /* Do alignment. */ 3845 frag_align (align, 0, 0); 3846 3847 /* Detach from old frag. */ 3848 if (S_GET_SEGMENT (symbolP) == bss_section) 3849 symbol_get_frag (symbolP)->fr_symbol = NULL; 3850 3851 symbol_set_frag (symbolP, frag_now); 3852 pfrag = frag_var (rs_org, 1, 1, (relax_substateT) 0, symbolP, 3853 (offsetT) size, (char *) 0); 3854 *pfrag = 0; 3855 3856 S_SET_SEGMENT (symbolP, bss_section); 3857 3858 subseg_set (current_seg, current_subseg); 3859 3860 #ifdef OBJ_ELF 3861 S_SET_SIZE (symbolP, size); 3862 #endif 3863 } 3864 } 3865 else 3866 { 3867 as_warn ("Ignoring attempt to re-define symbol %s", 3868 S_GET_NAME (symbolP)); 3869 } /* if not redefining. */ 3870 3871 demand_empty_rest_of_line (); 3872 } 3873 3874 static void 3875 s_common (ignore) 3876 int ignore ATTRIBUTE_UNUSED; 3877 { 3878 char *name; 3879 char c; 3880 char *p; 3881 offsetT temp, size; 3882 symbolS *symbolP; 3883 3884 name = input_line_pointer; 3885 c = get_symbol_end (); 3886 /* Just after name is now '\0'. */ 3887 p = input_line_pointer; 3888 *p = c; 3889 SKIP_WHITESPACE (); 3890 if (*input_line_pointer != ',') 3891 { 3892 as_bad (_("Expected comma after symbol-name")); 3893 ignore_rest_of_line (); 3894 return; 3895 } 3896 3897 /* Skip ','. */ 3898 input_line_pointer++; 3899 3900 if ((temp = get_absolute_expression ()) < 0) 3901 { 3902 as_bad (_(".COMMon length (%lu) out of range ignored"), 3903 (unsigned long) temp); 3904 ignore_rest_of_line (); 3905 return; 3906 } 3907 size = temp; 3908 *p = 0; 3909 symbolP = symbol_find_or_make (name); 3910 *p = c; 3911 if (S_IS_DEFINED (symbolP) && ! S_IS_COMMON (symbolP)) 3912 { 3913 as_bad (_("Ignoring attempt to re-define symbol")); 3914 ignore_rest_of_line (); 3915 return; 3916 } 3917 if (S_GET_VALUE (symbolP) != 0) 3918 { 3919 if (S_GET_VALUE (symbolP) != (valueT) size) 3920 { 3921 as_warn (_("Length of .comm \"%s\" is already %ld. Not changed to %ld."), 3922 S_GET_NAME (symbolP), (long) S_GET_VALUE (symbolP), (long) size); 3923 } 3924 } 3925 else 3926 { 3927 #ifndef OBJ_ELF 3928 S_SET_VALUE (symbolP, (valueT) size); 3929 S_SET_EXTERNAL (symbolP); 3930 #endif 3931 } 3932 know (symbol_get_frag (symbolP) == &zero_address_frag); 3933 if (*input_line_pointer != ',') 3934 { 3935 as_bad (_("Expected comma after common length")); 3936 ignore_rest_of_line (); 3937 return; 3938 } 3939 input_line_pointer++; 3940 SKIP_WHITESPACE (); 3941 if (*input_line_pointer != '"') 3942 { 3943 temp = get_absolute_expression (); 3944 3945 #ifndef OBJ_ELF 3946 if (temp > max_alignment) 3947 { 3948 temp = max_alignment; 3949 as_warn (_("alignment too large; assuming %ld"), (long) temp); 3950 } 3951 #endif 3952 3953 if (temp < 0) 3954 { 3955 as_bad (_("negative alignment")); 3956 ignore_rest_of_line (); 3957 return; 3958 } 3959 3960 #ifdef OBJ_ELF 3961 if (symbol_get_obj (symbolP)->local) 3962 { 3963 segT old_sec; 3964 int old_subsec; 3965 char *p; 3966 int align; 3967 3968 old_sec = now_seg; 3969 old_subsec = now_subseg; 3970 3971 if (temp == 0) 3972 align = 0; 3973 else 3974 align = mylog2 (temp); 3975 3976 if (align < 0) 3977 { 3978 as_bad (_("alignment not a power of 2")); 3979 ignore_rest_of_line (); 3980 return; 3981 } 3982 3983 record_alignment (bss_section, align); 3984 subseg_set (bss_section, 0); 3985 if (align) 3986 frag_align (align, 0, 0); 3987 if (S_GET_SEGMENT (symbolP) == bss_section) 3988 symbol_get_frag (symbolP)->fr_symbol = 0; 3989 symbol_set_frag (symbolP, frag_now); 3990 p = frag_var (rs_org, 1, 1, (relax_substateT) 0, symbolP, 3991 (offsetT) size, (char *) 0); 3992 *p = 0; 3993 S_SET_SEGMENT (symbolP, bss_section); 3994 S_CLEAR_EXTERNAL (symbolP); 3995 S_SET_SIZE (symbolP, size); 3996 subseg_set (old_sec, old_subsec); 3997 } 3998 else 3999 #endif /* OBJ_ELF */ 4000 { 4001 allocate_common: 4002 S_SET_VALUE (symbolP, (valueT) size); 4003 #ifdef OBJ_ELF 4004 S_SET_ALIGN (symbolP, temp); 4005 S_SET_SIZE (symbolP, size); 4006 #endif 4007 S_SET_EXTERNAL (symbolP); 4008 S_SET_SEGMENT (symbolP, bfd_com_section_ptr); 4009 } 4010 } 4011 else 4012 { 4013 input_line_pointer++; 4014 /* @@ Some use the dot, some don't. Can we get some consistency?? */ 4015 if (*input_line_pointer == '.') 4016 input_line_pointer++; 4017 /* @@ Some say data, some say bss. */ 4018 if (strncmp (input_line_pointer, "bss\"", 4) 4019 && strncmp (input_line_pointer, "data\"", 5)) 4020 { 4021 while (*--input_line_pointer != '"') 4022 ; 4023 input_line_pointer--; 4024 goto bad_common_segment; 4025 } 4026 while (*input_line_pointer++ != '"') 4027 ; 4028 goto allocate_common; 4029 } 4030 4031 symbol_get_bfdsym (symbolP)->flags |= BSF_OBJECT; 4032 4033 demand_empty_rest_of_line (); 4034 return; 4035 4036 { 4037 bad_common_segment: 4038 p = input_line_pointer; 4039 while (*p && *p != '\n') 4040 p++; 4041 c = *p; 4042 *p = '\0'; 4043 as_bad (_("bad .common segment %s"), input_line_pointer + 1); 4044 *p = c; 4045 input_line_pointer = p; 4046 ignore_rest_of_line (); 4047 return; 4048 } 4049 } 4050 4051 /* Handle the .empty pseudo-op. This suppresses the warnings about 4052 invalid delay slot usage. */ 4053 4054 static void 4055 s_empty (ignore) 4056 int ignore ATTRIBUTE_UNUSED; 4057 { 4058 /* The easy way to implement is to just forget about the last 4059 instruction. */ 4060 last_insn = NULL; 4061 } 4062 4063 static void 4064 s_seg (ignore) 4065 int ignore ATTRIBUTE_UNUSED; 4066 { 4067 4068 if (strncmp (input_line_pointer, "\"text\"", 6) == 0) 4069 { 4070 input_line_pointer += 6; 4071 s_text (0); 4072 return; 4073 } 4074 if (strncmp (input_line_pointer, "\"data\"", 6) == 0) 4075 { 4076 input_line_pointer += 6; 4077 s_data (0); 4078 return; 4079 } 4080 if (strncmp (input_line_pointer, "\"data1\"", 7) == 0) 4081 { 4082 input_line_pointer += 7; 4083 s_data1 (); 4084 return; 4085 } 4086 if (strncmp (input_line_pointer, "\"bss\"", 5) == 0) 4087 { 4088 input_line_pointer += 5; 4089 /* We only support 2 segments -- text and data -- for now, so 4090 things in the "bss segment" will have to go into data for now. 4091 You can still allocate SEG_BSS stuff with .lcomm or .reserve. */ 4092 subseg_set (data_section, 255); /* FIXME-SOMEDAY. */ 4093 return; 4094 } 4095 as_bad (_("Unknown segment type")); 4096 demand_empty_rest_of_line (); 4097 } 4098 4099 static void 4100 s_data1 () 4101 { 4102 subseg_set (data_section, 1); 4103 demand_empty_rest_of_line (); 4104 } 4105 4106 static void 4107 s_proc (ignore) 4108 int ignore ATTRIBUTE_UNUSED; 4109 { 4110 while (!is_end_of_line[(unsigned char) *input_line_pointer]) 4111 { 4112 ++input_line_pointer; 4113 } 4114 ++input_line_pointer; 4115 } 4116 4117 /* This static variable is set by s_uacons to tell sparc_cons_align 4118 that the expression does not need to be aligned. */ 4119 4120 static int sparc_no_align_cons = 0; 4121 4122 /* This static variable is set by sparc_cons to emit requested types 4123 of relocations in cons_fix_new_sparc. */ 4124 4125 static const char *sparc_cons_special_reloc; 4126 4127 /* This handles the unaligned space allocation pseudo-ops, such as 4128 .uaword. .uaword is just like .word, but the value does not need 4129 to be aligned. */ 4130 4131 static void 4132 s_uacons (bytes) 4133 int bytes; 4134 { 4135 /* Tell sparc_cons_align not to align this value. */ 4136 sparc_no_align_cons = 1; 4137 cons (bytes); 4138 sparc_no_align_cons = 0; 4139 } 4140 4141 /* This handles the native word allocation pseudo-op .nword. 4142 For sparc_arch_size 32 it is equivalent to .word, for 4143 sparc_arch_size 64 it is equivalent to .xword. */ 4144 4145 static void 4146 s_ncons (bytes) 4147 int bytes ATTRIBUTE_UNUSED; 4148 { 4149 cons (sparc_arch_size == 32 ? 4 : 8); 4150 } 4151 4152 #ifdef OBJ_ELF 4153 /* Handle the SPARC ELF .register pseudo-op. This sets the binding of a 4154 global register. 4155 The syntax is: 4156 4157 .register %g[2367],{#scratch|symbolname|#ignore} 4158 */ 4159 4160 static void 4161 s_register (ignore) 4162 int ignore ATTRIBUTE_UNUSED; 4163 { 4164 char c; 4165 int reg; 4166 int flags; 4167 const char *regname; 4168 4169 if (input_line_pointer[0] != '%' 4170 || input_line_pointer[1] != 'g' 4171 || ((input_line_pointer[2] & ~1) != '2' 4172 && (input_line_pointer[2] & ~1) != '6') 4173 || input_line_pointer[3] != ',') 4174 as_bad (_("register syntax is .register %%g[2367],{#scratch|symbolname|#ignore}")); 4175 reg = input_line_pointer[2] - '0'; 4176 input_line_pointer += 4; 4177 4178 if (*input_line_pointer == '#') 4179 { 4180 ++input_line_pointer; 4181 regname = input_line_pointer; 4182 c = get_symbol_end (); 4183 if (strcmp (regname, "scratch") && strcmp (regname, "ignore")) 4184 as_bad (_("register syntax is .register %%g[2367],{#scratch|symbolname|#ignore}")); 4185 if (regname[0] == 'i') 4186 regname = NULL; 4187 else 4188 regname = ""; 4189 } 4190 else 4191 { 4192 regname = input_line_pointer; 4193 c = get_symbol_end (); 4194 } 4195 if (sparc_arch_size == 64) 4196 { 4197 if (globals[reg]) 4198 { 4199 if ((regname && globals[reg] != (symbolS *) 1 4200 && strcmp (S_GET_NAME (globals[reg]), regname)) 4201 || ((regname != NULL) ^ (globals[reg] != (symbolS *) 1))) 4202 as_bad (_("redefinition of global register")); 4203 } 4204 else 4205 { 4206 if (regname == NULL) 4207 globals[reg] = (symbolS *) 1; 4208 else 4209 { 4210 if (*regname) 4211 { 4212 if (symbol_find (regname)) 4213 as_bad (_("Register symbol %s already defined."), 4214 regname); 4215 } 4216 globals[reg] = symbol_make (regname); 4217 flags = symbol_get_bfdsym (globals[reg])->flags; 4218 if (! *regname) 4219 flags = flags & ~(BSF_GLOBAL|BSF_LOCAL|BSF_WEAK); 4220 if (! (flags & (BSF_GLOBAL|BSF_LOCAL|BSF_WEAK))) 4221 flags |= BSF_GLOBAL; 4222 symbol_get_bfdsym (globals[reg])->flags = flags; 4223 S_SET_VALUE (globals[reg], (valueT) reg); 4224 S_SET_ALIGN (globals[reg], reg); 4225 S_SET_SIZE (globals[reg], 0); 4226 /* Although we actually want undefined_section here, 4227 we have to use absolute_section, because otherwise 4228 generic as code will make it a COM section. 4229 We fix this up in sparc_adjust_symtab. */ 4230 S_SET_SEGMENT (globals[reg], absolute_section); 4231 S_SET_OTHER (globals[reg], 0); 4232 elf_symbol (symbol_get_bfdsym (globals[reg])) 4233 ->internal_elf_sym.st_info = 4234 ELF_ST_INFO(STB_GLOBAL, STT_REGISTER); 4235 elf_symbol (symbol_get_bfdsym (globals[reg])) 4236 ->internal_elf_sym.st_shndx = SHN_UNDEF; 4237 } 4238 } 4239 } 4240 4241 *input_line_pointer = c; 4242 4243 demand_empty_rest_of_line (); 4244 } 4245 4246 /* Adjust the symbol table. We set undefined sections for STT_REGISTER 4247 symbols which need it. */ 4248 4249 void 4250 sparc_adjust_symtab () 4251 { 4252 symbolS *sym; 4253 4254 for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym)) 4255 { 4256 if (ELF_ST_TYPE (elf_symbol (symbol_get_bfdsym (sym)) 4257 ->internal_elf_sym.st_info) != STT_REGISTER) 4258 continue; 4259 4260 if (ELF_ST_TYPE (elf_symbol (symbol_get_bfdsym (sym)) 4261 ->internal_elf_sym.st_shndx != SHN_UNDEF)) 4262 continue; 4263 4264 S_SET_SEGMENT (sym, undefined_section); 4265 } 4266 } 4267 #endif 4268 4269 /* If the --enforce-aligned-data option is used, we require .word, 4270 et. al., to be aligned correctly. We do it by setting up an 4271 rs_align_code frag, and checking in HANDLE_ALIGN to make sure that 4272 no unexpected alignment was introduced. 4273 4274 The SunOS and Solaris native assemblers enforce aligned data by 4275 default. We don't want to do that, because gcc can deliberately 4276 generate misaligned data if the packed attribute is used. Instead, 4277 we permit misaligned data by default, and permit the user to set an 4278 option to check for it. */ 4279 4280 void 4281 sparc_cons_align (nbytes) 4282 int nbytes; 4283 { 4284 int nalign; 4285 char *p; 4286 4287 /* Only do this if we are enforcing aligned data. */ 4288 if (! enforce_aligned_data) 4289 return; 4290 4291 /* Don't align if this is an unaligned pseudo-op. */ 4292 if (sparc_no_align_cons) 4293 return; 4294 4295 nalign = mylog2 (nbytes); 4296 if (nalign == 0) 4297 return; 4298 4299 assert (nalign > 0); 4300 4301 if (now_seg == absolute_section) 4302 { 4303 if ((abs_section_offset & ((1 << nalign) - 1)) != 0) 4304 as_bad (_("misaligned data")); 4305 return; 4306 } 4307 4308 p = frag_var (rs_align_test, 1, 1, (relax_substateT) 0, 4309 (symbolS *) NULL, (offsetT) nalign, (char *) NULL); 4310 4311 record_alignment (now_seg, nalign); 4312 } 4313 4314 /* This is called from HANDLE_ALIGN in tc-sparc.h. */ 4315 4316 void 4317 sparc_handle_align (fragp) 4318 fragS *fragp; 4319 { 4320 int count, fix; 4321 char *p; 4322 4323 count = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix; 4324 4325 switch (fragp->fr_type) 4326 { 4327 case rs_align_test: 4328 if (count != 0) 4329 as_bad_where (fragp->fr_file, fragp->fr_line, _("misaligned data")); 4330 break; 4331 4332 case rs_align_code: 4333 p = fragp->fr_literal + fragp->fr_fix; 4334 fix = 0; 4335 4336 if (count & 3) 4337 { 4338 fix = count & 3; 4339 memset (p, 0, fix); 4340 p += fix; 4341 count -= fix; 4342 } 4343 4344 if (SPARC_OPCODE_ARCH_V9_P (max_architecture) && count > 8) 4345 { 4346 unsigned wval = (0x30680000 | count >> 2); /* ba,a,pt %xcc, 1f */ 4347 if (INSN_BIG_ENDIAN) 4348 number_to_chars_bigendian (p, wval, 4); 4349 else 4350 number_to_chars_littleendian (p, wval, 4); 4351 p += 4; 4352 count -= 4; 4353 fix += 4; 4354 } 4355 4356 if (INSN_BIG_ENDIAN) 4357 number_to_chars_bigendian (p, 0x01000000, 4); 4358 else 4359 number_to_chars_littleendian (p, 0x01000000, 4); 4360 4361 fragp->fr_fix += fix; 4362 fragp->fr_var = 4; 4363 break; 4364 4365 default: 4366 break; 4367 } 4368 } 4369 4370 #ifdef OBJ_ELF 4371 /* Some special processing for a Sparc ELF file. */ 4372 4373 void 4374 sparc_elf_final_processing () 4375 { 4376 /* Set the Sparc ELF flag bits. FIXME: There should probably be some 4377 sort of BFD interface for this. */ 4378 if (sparc_arch_size == 64) 4379 { 4380 switch (sparc_memory_model) 4381 { 4382 case MM_RMO: 4383 elf_elfheader (stdoutput)->e_flags |= EF_SPARCV9_RMO; 4384 break; 4385 case MM_PSO: 4386 elf_elfheader (stdoutput)->e_flags |= EF_SPARCV9_PSO; 4387 break; 4388 default: 4389 break; 4390 } 4391 } 4392 else if (current_architecture >= SPARC_OPCODE_ARCH_V9) 4393 elf_elfheader (stdoutput)->e_flags |= EF_SPARC_32PLUS; 4394 if (current_architecture == SPARC_OPCODE_ARCH_V9A) 4395 elf_elfheader (stdoutput)->e_flags |= EF_SPARC_SUN_US1; 4396 else if (current_architecture == SPARC_OPCODE_ARCH_V9B) 4397 elf_elfheader (stdoutput)->e_flags |= EF_SPARC_SUN_US1|EF_SPARC_SUN_US3; 4398 } 4399 4400 void 4401 sparc_cons (exp, size) 4402 expressionS *exp; 4403 int size; 4404 { 4405 char *save; 4406 4407 SKIP_WHITESPACE (); 4408 sparc_cons_special_reloc = NULL; 4409 save = input_line_pointer; 4410 if (input_line_pointer[0] == '%' 4411 && input_line_pointer[1] == 'r' 4412 && input_line_pointer[2] == '_') 4413 { 4414 if (strncmp (input_line_pointer + 3, "disp", 4) == 0) 4415 { 4416 input_line_pointer += 7; 4417 sparc_cons_special_reloc = "disp"; 4418 } 4419 else if (strncmp (input_line_pointer + 3, "plt", 3) == 0) 4420 { 4421 if (size != 4 && size != 8) 4422 as_bad (_("Illegal operands: %%r_plt in %d-byte data field"), size); 4423 else 4424 { 4425 input_line_pointer += 6; 4426 sparc_cons_special_reloc = "plt"; 4427 } 4428 } 4429 else if (strncmp (input_line_pointer + 3, "tls_dtpoff", 10) == 0) 4430 { 4431 if (size != 4 && size != 8) 4432 as_bad (_("Illegal operands: %%r_tls_dtpoff in %d-byte data field"), size); 4433 else 4434 { 4435 input_line_pointer += 13; 4436 sparc_cons_special_reloc = "tls_dtpoff"; 4437 } 4438 } 4439 if (sparc_cons_special_reloc) 4440 { 4441 int bad = 0; 4442 4443 switch (size) 4444 { 4445 case 1: 4446 if (*input_line_pointer != '8') 4447 bad = 1; 4448 input_line_pointer--; 4449 break; 4450 case 2: 4451 if (input_line_pointer[0] != '1' || input_line_pointer[1] != '6') 4452 bad = 1; 4453 break; 4454 case 4: 4455 if (input_line_pointer[0] != '3' || input_line_pointer[1] != '2') 4456 bad = 1; 4457 break; 4458 case 8: 4459 if (input_line_pointer[0] != '6' || input_line_pointer[1] != '4') 4460 bad = 1; 4461 break; 4462 default: 4463 bad = 1; 4464 break; 4465 } 4466 4467 if (bad) 4468 { 4469 as_bad (_("Illegal operands: Only %%r_%s%d allowed in %d-byte data fields"), 4470 sparc_cons_special_reloc, size * 8, size); 4471 } 4472 else 4473 { 4474 input_line_pointer += 2; 4475 if (*input_line_pointer != '(') 4476 { 4477 as_bad (_("Illegal operands: %%r_%s%d requires arguments in ()"), 4478 sparc_cons_special_reloc, size * 8); 4479 bad = 1; 4480 } 4481 } 4482 4483 if (bad) 4484 { 4485 input_line_pointer = save; 4486 sparc_cons_special_reloc = NULL; 4487 } 4488 else 4489 { 4490 int c; 4491 char *end = ++input_line_pointer; 4492 int npar = 0; 4493 4494 while (! is_end_of_line[(c = *end)]) 4495 { 4496 if (c == '(') 4497 npar++; 4498 else if (c == ')') 4499 { 4500 if (!npar) 4501 break; 4502 npar--; 4503 } 4504 end++; 4505 } 4506 4507 if (c != ')') 4508 as_bad (_("Illegal operands: %%r_%s%d requires arguments in ()"), 4509 sparc_cons_special_reloc, size * 8); 4510 else 4511 { 4512 *end = '\0'; 4513 expression (exp); 4514 *end = c; 4515 if (input_line_pointer != end) 4516 { 4517 as_bad (_("Illegal operands: %%r_%s%d requires arguments in ()"), 4518 sparc_cons_special_reloc, size * 8); 4519 } 4520 else 4521 { 4522 input_line_pointer++; 4523 SKIP_WHITESPACE (); 4524 c = *input_line_pointer; 4525 if (! is_end_of_line[c] && c != ',') 4526 as_bad (_("Illegal operands: garbage after %%r_%s%d()"), 4527 sparc_cons_special_reloc, size * 8); 4528 } 4529 } 4530 } 4531 } 4532 } 4533 if (sparc_cons_special_reloc == NULL) 4534 expression (exp); 4535 } 4536 4537 #endif 4538 4539 /* This is called by emit_expr via TC_CONS_FIX_NEW when creating a 4540 reloc for a cons. We could use the definition there, except that 4541 we want to handle little endian relocs specially. */ 4542 4543 void 4544 cons_fix_new_sparc (frag, where, nbytes, exp) 4545 fragS *frag; 4546 int where; 4547 unsigned int nbytes; 4548 expressionS *exp; 4549 { 4550 bfd_reloc_code_real_type r; 4551 4552 r = (nbytes == 1 ? BFD_RELOC_8 : 4553 (nbytes == 2 ? BFD_RELOC_16 : 4554 (nbytes == 4 ? BFD_RELOC_32 : BFD_RELOC_64))); 4555 4556 if (target_little_endian_data 4557 && nbytes == 4 4558 && now_seg->flags & SEC_ALLOC) 4559 r = BFD_RELOC_SPARC_REV32; 4560 4561 if (sparc_cons_special_reloc) 4562 { 4563 if (*sparc_cons_special_reloc == 'd') 4564 switch (nbytes) 4565 { 4566 case 1: r = BFD_RELOC_8_PCREL; break; 4567 case 2: r = BFD_RELOC_16_PCREL; break; 4568 case 4: r = BFD_RELOC_32_PCREL; break; 4569 case 8: r = BFD_RELOC_64_PCREL; break; 4570 default: abort (); 4571 } 4572 else if (*sparc_cons_special_reloc == 'p') 4573 switch (nbytes) 4574 { 4575 case 4: r = BFD_RELOC_SPARC_PLT32; break; 4576 case 8: r = BFD_RELOC_SPARC_PLT64; break; 4577 } 4578 else 4579 switch (nbytes) 4580 { 4581 case 4: r = BFD_RELOC_SPARC_TLS_DTPOFF32; break; 4582 case 8: r = BFD_RELOC_SPARC_TLS_DTPOFF64; break; 4583 } 4584 } 4585 else if (sparc_no_align_cons) 4586 { 4587 switch (nbytes) 4588 { 4589 case 2: r = BFD_RELOC_SPARC_UA16; break; 4590 case 4: r = BFD_RELOC_SPARC_UA32; break; 4591 case 8: r = BFD_RELOC_SPARC_UA64; break; 4592 default: abort (); 4593 } 4594 } 4595 4596 fix_new_exp (frag, where, (int) nbytes, exp, 0, r); 4597 sparc_cons_special_reloc = NULL; 4598 } 4599 4600 void 4601 sparc_cfi_frame_initial_instructions () 4602 { 4603 cfi_add_CFA_def_cfa (14, sparc_arch_size == 64 ? 0x7ff : 0); 4604 } 4605 4606 int 4607 sparc_regname_to_dw2regnum (const char *regname) 4608 { 4609 char *p, *q; 4610 4611 if (!regname[0]) 4612 return -1; 4613 4614 q = "goli"; 4615 p = strchr (q, regname[0]); 4616 if (p) 4617 { 4618 if (regname[1] < '0' || regname[1] > '8' || regname[2]) 4619 return -1; 4620 return (p - q) * 8 + regname[1] - '0'; 4621 } 4622 if (regname[0] == 's' && regname[1] == 'p' && !regname[2]) 4623 return 14; 4624 if (regname[0] == 'f' && regname[1] == 'p' && !regname[2]) 4625 return 30; 4626 if (regname[0] == 'f' || regname[0] == 'r') 4627 { 4628 unsigned int regnum; 4629 4630 regnum = strtoul (regname + 1, &q, 10); 4631 if (p == q || *q) 4632 return -1; 4633 if (regnum >= ((regname[0] == 'f' 4634 && SPARC_OPCODE_ARCH_V9_P (max_architecture)) 4635 ? 64 : 32)) 4636 return -1; 4637 if (regname[0] == 'f') 4638 { 4639 regnum += 32; 4640 if (regnum >= 64 && (regnum & 1)) 4641 return -1; 4642 } 4643 return regnum; 4644 } 4645 return -1; 4646 } 4647 4648 void 4649 sparc_cfi_emit_pcrel_expr (expressionS *exp, unsigned int nbytes) 4650 { 4651 sparc_cons_special_reloc = "disp"; 4652 sparc_no_align_cons = 1; 4653 emit_expr (exp, nbytes); 4654 sparc_no_align_cons = 0; 4655 sparc_cons_special_reloc = NULL; 4656 } 4657