1add_llvm_component_group(RISCV) 2 3set(LLVM_TARGET_DEFINITIONS RISCV.td) 4 5tablegen(LLVM RISCVGenAsmMatcher.inc -gen-asm-matcher) 6tablegen(LLVM RISCVGenAsmWriter.inc -gen-asm-writer) 7tablegen(LLVM RISCVGenCompressInstEmitter.inc -gen-compress-inst-emitter) 8tablegen(LLVM RISCVGenDAGISel.inc -gen-dag-isel) 9tablegen(LLVM RISCVGenDisassemblerTables.inc -gen-disassembler) 10tablegen(LLVM RISCVGenGlobalISel.inc -gen-global-isel) 11tablegen(LLVM RISCVGenInstrInfo.inc -gen-instr-info) 12tablegen(LLVM RISCVGenMCCodeEmitter.inc -gen-emitter) 13tablegen(LLVM RISCVGenMCPseudoLowering.inc -gen-pseudo-lowering) 14tablegen(LLVM RISCVGenRegisterBank.inc -gen-register-bank) 15tablegen(LLVM RISCVGenRegisterInfo.inc -gen-register-info) 16tablegen(LLVM RISCVGenSearchableTables.inc -gen-searchable-tables) 17tablegen(LLVM RISCVGenSubtargetInfo.inc -gen-subtarget) 18 19add_public_tablegen_target(RISCVCommonTableGen) 20 21add_llvm_target(RISCVCodeGen 22 RISCVAsmPrinter.cpp 23 RISCVCallLowering.cpp 24 RISCVExpandAtomicPseudoInsts.cpp 25 RISCVExpandPseudoInsts.cpp 26 RISCVFrameLowering.cpp 27 RISCVInsertVSETVLI.cpp 28 RISCVInstrInfo.cpp 29 RISCVInstructionSelector.cpp 30 RISCVISelDAGToDAG.cpp 31 RISCVISelLowering.cpp 32 RISCVLegalizerInfo.cpp 33 RISCVMCInstLower.cpp 34 RISCVMergeBaseOffset.cpp 35 RISCVRegisterBankInfo.cpp 36 RISCVRegisterInfo.cpp 37 RISCVSubtarget.cpp 38 RISCVTargetMachine.cpp 39 RISCVTargetObjectFile.cpp 40 RISCVTargetTransformInfo.cpp 41 42 LINK_COMPONENTS 43 Analysis 44 AsmPrinter 45 Core 46 CodeGen 47 MC 48 RISCVDesc 49 RISCVInfo 50 SelectionDAG 51 Support 52 Target 53 GlobalISel 54 55 ADD_TO_COMPONENT 56 RISCV 57 ) 58 59add_subdirectory(AsmParser) 60add_subdirectory(Disassembler) 61add_subdirectory(MCTargetDesc) 62add_subdirectory(TargetInfo) 63