1*061da546Spatrick //===-- ARM_DWARF_Registers.h -----------------------------------*- C++ -*-===// 2*061da546Spatrick // 3*061da546Spatrick // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4*061da546Spatrick // See https://llvm.org/LICENSE.txt for license information. 5*061da546Spatrick // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6*061da546Spatrick // 7*061da546Spatrick //===----------------------------------------------------------------------===// 8*061da546Spatrick 9*061da546Spatrick #ifndef ARM_DWARF_Registers_h_ 10*061da546Spatrick #define ARM_DWARF_Registers_h_ 11*061da546Spatrick 12*061da546Spatrick enum { 13*061da546Spatrick dwarf_r0 = 0, 14*061da546Spatrick dwarf_r1, 15*061da546Spatrick dwarf_r2, 16*061da546Spatrick dwarf_r3, 17*061da546Spatrick dwarf_r4, 18*061da546Spatrick dwarf_r5, 19*061da546Spatrick dwarf_r6, 20*061da546Spatrick dwarf_r7, 21*061da546Spatrick dwarf_r8, 22*061da546Spatrick dwarf_r9, 23*061da546Spatrick dwarf_r10, 24*061da546Spatrick dwarf_r11, 25*061da546Spatrick dwarf_r12, 26*061da546Spatrick dwarf_sp, 27*061da546Spatrick dwarf_lr, 28*061da546Spatrick dwarf_pc, 29*061da546Spatrick dwarf_cpsr, 30*061da546Spatrick 31*061da546Spatrick dwarf_s0 = 64, 32*061da546Spatrick dwarf_s1, 33*061da546Spatrick dwarf_s2, 34*061da546Spatrick dwarf_s3, 35*061da546Spatrick dwarf_s4, 36*061da546Spatrick dwarf_s5, 37*061da546Spatrick dwarf_s6, 38*061da546Spatrick dwarf_s7, 39*061da546Spatrick dwarf_s8, 40*061da546Spatrick dwarf_s9, 41*061da546Spatrick dwarf_s10, 42*061da546Spatrick dwarf_s11, 43*061da546Spatrick dwarf_s12, 44*061da546Spatrick dwarf_s13, 45*061da546Spatrick dwarf_s14, 46*061da546Spatrick dwarf_s15, 47*061da546Spatrick dwarf_s16, 48*061da546Spatrick dwarf_s17, 49*061da546Spatrick dwarf_s18, 50*061da546Spatrick dwarf_s19, 51*061da546Spatrick dwarf_s20, 52*061da546Spatrick dwarf_s21, 53*061da546Spatrick dwarf_s22, 54*061da546Spatrick dwarf_s23, 55*061da546Spatrick dwarf_s24, 56*061da546Spatrick dwarf_s25, 57*061da546Spatrick dwarf_s26, 58*061da546Spatrick dwarf_s27, 59*061da546Spatrick dwarf_s28, 60*061da546Spatrick dwarf_s29, 61*061da546Spatrick dwarf_s30, 62*061da546Spatrick dwarf_s31, 63*061da546Spatrick 64*061da546Spatrick // FPA Registers 0-7 65*061da546Spatrick dwarf_f0 = 96, 66*061da546Spatrick dwarf_f1, 67*061da546Spatrick dwarf_f2, 68*061da546Spatrick dwarf_f3, 69*061da546Spatrick dwarf_f4, 70*061da546Spatrick dwarf_f5, 71*061da546Spatrick dwarf_f6, 72*061da546Spatrick dwarf_f7, 73*061da546Spatrick 74*061da546Spatrick // Intel wireless MMX general purpose registers 0 - 7 75*061da546Spatrick dwarf_wCGR0 = 104, 76*061da546Spatrick dwarf_wCGR1, 77*061da546Spatrick dwarf_wCGR2, 78*061da546Spatrick dwarf_wCGR3, 79*061da546Spatrick dwarf_wCGR4, 80*061da546Spatrick dwarf_wCGR5, 81*061da546Spatrick dwarf_wCGR6, 82*061da546Spatrick dwarf_wCGR7, 83*061da546Spatrick 84*061da546Spatrick // XScale accumulator register 0–7 (they do overlap with wCGR0 - wCGR7) 85*061da546Spatrick dwarf_ACC0 = 104, 86*061da546Spatrick dwarf_ACC1, 87*061da546Spatrick dwarf_ACC2, 88*061da546Spatrick dwarf_ACC3, 89*061da546Spatrick dwarf_ACC4, 90*061da546Spatrick dwarf_ACC5, 91*061da546Spatrick dwarf_ACC6, 92*061da546Spatrick dwarf_ACC7, 93*061da546Spatrick 94*061da546Spatrick // Intel wireless MMX data registers 0 - 15 95*061da546Spatrick dwarf_wR0 = 112, 96*061da546Spatrick dwarf_wR1, 97*061da546Spatrick dwarf_wR2, 98*061da546Spatrick dwarf_wR3, 99*061da546Spatrick dwarf_wR4, 100*061da546Spatrick dwarf_wR5, 101*061da546Spatrick dwarf_wR6, 102*061da546Spatrick dwarf_wR7, 103*061da546Spatrick dwarf_wR8, 104*061da546Spatrick dwarf_wR9, 105*061da546Spatrick dwarf_wR10, 106*061da546Spatrick dwarf_wR11, 107*061da546Spatrick dwarf_wR12, 108*061da546Spatrick dwarf_wR13, 109*061da546Spatrick dwarf_wR14, 110*061da546Spatrick dwarf_wR15, 111*061da546Spatrick 112*061da546Spatrick dwarf_spsr = 128, 113*061da546Spatrick dwarf_spsr_fiq, 114*061da546Spatrick dwarf_spsr_irq, 115*061da546Spatrick dwarf_spsr_abt, 116*061da546Spatrick dwarf_spsr_und, 117*061da546Spatrick dwarf_spsr_svc, 118*061da546Spatrick 119*061da546Spatrick dwarf_r8_usr = 144, 120*061da546Spatrick dwarf_r9_usr, 121*061da546Spatrick dwarf_r10_usr, 122*061da546Spatrick dwarf_r11_usr, 123*061da546Spatrick dwarf_r12_usr, 124*061da546Spatrick dwarf_r13_usr, 125*061da546Spatrick dwarf_r14_usr, 126*061da546Spatrick dwarf_r8_fiq, 127*061da546Spatrick dwarf_r9_fiq, 128*061da546Spatrick dwarf_r10_fiq, 129*061da546Spatrick dwarf_r11_fiq, 130*061da546Spatrick dwarf_r12_fiq, 131*061da546Spatrick dwarf_r13_fiq, 132*061da546Spatrick dwarf_r14_fiq, 133*061da546Spatrick dwarf_r13_irq, 134*061da546Spatrick dwarf_r14_irq, 135*061da546Spatrick dwarf_r13_abt, 136*061da546Spatrick dwarf_r14_abt, 137*061da546Spatrick dwarf_r13_und, 138*061da546Spatrick dwarf_r14_und, 139*061da546Spatrick dwarf_r13_svc, 140*061da546Spatrick dwarf_r14_svc, 141*061da546Spatrick 142*061da546Spatrick // Intel wireless MMX control register in co-processor 0 - 7 143*061da546Spatrick dwarf_wC0 = 192, 144*061da546Spatrick dwarf_wC1, 145*061da546Spatrick dwarf_wC2, 146*061da546Spatrick dwarf_wC3, 147*061da546Spatrick dwarf_wC4, 148*061da546Spatrick dwarf_wC5, 149*061da546Spatrick dwarf_wC6, 150*061da546Spatrick dwarf_wC7, 151*061da546Spatrick 152*061da546Spatrick // VFP-v3/Neon 153*061da546Spatrick dwarf_d0 = 256, 154*061da546Spatrick dwarf_d1, 155*061da546Spatrick dwarf_d2, 156*061da546Spatrick dwarf_d3, 157*061da546Spatrick dwarf_d4, 158*061da546Spatrick dwarf_d5, 159*061da546Spatrick dwarf_d6, 160*061da546Spatrick dwarf_d7, 161*061da546Spatrick dwarf_d8, 162*061da546Spatrick dwarf_d9, 163*061da546Spatrick dwarf_d10, 164*061da546Spatrick dwarf_d11, 165*061da546Spatrick dwarf_d12, 166*061da546Spatrick dwarf_d13, 167*061da546Spatrick dwarf_d14, 168*061da546Spatrick dwarf_d15, 169*061da546Spatrick dwarf_d16, 170*061da546Spatrick dwarf_d17, 171*061da546Spatrick dwarf_d18, 172*061da546Spatrick dwarf_d19, 173*061da546Spatrick dwarf_d20, 174*061da546Spatrick dwarf_d21, 175*061da546Spatrick dwarf_d22, 176*061da546Spatrick dwarf_d23, 177*061da546Spatrick dwarf_d24, 178*061da546Spatrick dwarf_d25, 179*061da546Spatrick dwarf_d26, 180*061da546Spatrick dwarf_d27, 181*061da546Spatrick dwarf_d28, 182*061da546Spatrick dwarf_d29, 183*061da546Spatrick dwarf_d30, 184*061da546Spatrick dwarf_d31, 185*061da546Spatrick 186*061da546Spatrick // Neon quadword registers 187*061da546Spatrick dwarf_q0 = 288, 188*061da546Spatrick dwarf_q1, 189*061da546Spatrick dwarf_q2, 190*061da546Spatrick dwarf_q3, 191*061da546Spatrick dwarf_q4, 192*061da546Spatrick dwarf_q5, 193*061da546Spatrick dwarf_q6, 194*061da546Spatrick dwarf_q7, 195*061da546Spatrick dwarf_q8, 196*061da546Spatrick dwarf_q9, 197*061da546Spatrick dwarf_q10, 198*061da546Spatrick dwarf_q11, 199*061da546Spatrick dwarf_q12, 200*061da546Spatrick dwarf_q13, 201*061da546Spatrick dwarf_q14, 202*061da546Spatrick dwarf_q15 203*061da546Spatrick }; 204*061da546Spatrick 205*061da546Spatrick #endif // ARM_DWARF_Registers_h_ 206