1 //===-- ArchSpec.cpp ------------------------------------------------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 9 #include "lldb/Utility/ArchSpec.h" 10 11 #include "lldb/Utility/Log.h" 12 #include "lldb/Utility/StringList.h" 13 #include "lldb/lldb-defines.h" 14 #include "llvm/ADT/STLExtras.h" 15 #include "llvm/BinaryFormat/COFF.h" 16 #include "llvm/BinaryFormat/ELF.h" 17 #include "llvm/BinaryFormat/MachO.h" 18 #include "llvm/Support/Compiler.h" 19 20 using namespace lldb; 21 using namespace lldb_private; 22 23 static bool cores_match(const ArchSpec::Core core1, const ArchSpec::Core core2, 24 bool try_inverse, bool enforce_exact_match); 25 26 namespace lldb_private { 27 28 struct CoreDefinition { 29 ByteOrder default_byte_order; 30 uint32_t addr_byte_size; 31 uint32_t min_opcode_byte_size; 32 uint32_t max_opcode_byte_size; 33 llvm::Triple::ArchType machine; 34 ArchSpec::Core core; 35 const char *const name; 36 }; 37 38 } // namespace lldb_private 39 40 // This core information can be looked using the ArchSpec::Core as the index 41 static const CoreDefinition g_core_definitions[] = { 42 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_generic, 43 "arm"}, 44 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv4, 45 "armv4"}, 46 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv4t, 47 "armv4t"}, 48 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv5, 49 "armv5"}, 50 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv5e, 51 "armv5e"}, 52 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv5t, 53 "armv5t"}, 54 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv6, 55 "armv6"}, 56 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv6m, 57 "armv6m"}, 58 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7, 59 "armv7"}, 60 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7l, 61 "armv7l"}, 62 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7f, 63 "armv7f"}, 64 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7s, 65 "armv7s"}, 66 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7k, 67 "armv7k"}, 68 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7m, 69 "armv7m"}, 70 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7em, 71 "armv7em"}, 72 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_xscale, 73 "xscale"}, 74 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumb, 75 "thumb"}, 76 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv4t, 77 "thumbv4t"}, 78 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv5, 79 "thumbv5"}, 80 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv5e, 81 "thumbv5e"}, 82 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv6, 83 "thumbv6"}, 84 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv6m, 85 "thumbv6m"}, 86 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv7, 87 "thumbv7"}, 88 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv7f, 89 "thumbv7f"}, 90 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv7s, 91 "thumbv7s"}, 92 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv7k, 93 "thumbv7k"}, 94 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv7m, 95 "thumbv7m"}, 96 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv7em, 97 "thumbv7em"}, 98 {eByteOrderLittle, 8, 4, 4, llvm::Triple::aarch64, 99 ArchSpec::eCore_arm_arm64, "arm64"}, 100 {eByteOrderLittle, 8, 4, 4, llvm::Triple::aarch64, 101 ArchSpec::eCore_arm_armv8, "armv8"}, 102 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv8l, 103 "armv8l"}, 104 {eByteOrderLittle, 8, 4, 4, llvm::Triple::aarch64, 105 ArchSpec::eCore_arm_arm64e, "arm64e"}, 106 {eByteOrderLittle, 4, 4, 4, llvm::Triple::aarch64_32, 107 ArchSpec::eCore_arm_arm64_32, "arm64_32"}, 108 {eByteOrderLittle, 8, 4, 4, llvm::Triple::aarch64, 109 ArchSpec::eCore_arm_aarch64, "aarch64"}, 110 111 // mips32, mips32r2, mips32r3, mips32r5, mips32r6 112 {eByteOrderBig, 4, 2, 4, llvm::Triple::mips, ArchSpec::eCore_mips32, 113 "mips"}, 114 {eByteOrderBig, 4, 2, 4, llvm::Triple::mips, ArchSpec::eCore_mips32r2, 115 "mipsr2"}, 116 {eByteOrderBig, 4, 2, 4, llvm::Triple::mips, ArchSpec::eCore_mips32r3, 117 "mipsr3"}, 118 {eByteOrderBig, 4, 2, 4, llvm::Triple::mips, ArchSpec::eCore_mips32r5, 119 "mipsr5"}, 120 {eByteOrderBig, 4, 2, 4, llvm::Triple::mips, ArchSpec::eCore_mips32r6, 121 "mipsr6"}, 122 {eByteOrderLittle, 4, 2, 4, llvm::Triple::mipsel, ArchSpec::eCore_mips32el, 123 "mipsel"}, 124 {eByteOrderLittle, 4, 2, 4, llvm::Triple::mipsel, 125 ArchSpec::eCore_mips32r2el, "mipsr2el"}, 126 {eByteOrderLittle, 4, 2, 4, llvm::Triple::mipsel, 127 ArchSpec::eCore_mips32r3el, "mipsr3el"}, 128 {eByteOrderLittle, 4, 2, 4, llvm::Triple::mipsel, 129 ArchSpec::eCore_mips32r5el, "mipsr5el"}, 130 {eByteOrderLittle, 4, 2, 4, llvm::Triple::mipsel, 131 ArchSpec::eCore_mips32r6el, "mipsr6el"}, 132 133 // mips64, mips64r2, mips64r3, mips64r5, mips64r6 134 {eByteOrderBig, 8, 2, 4, llvm::Triple::mips64, ArchSpec::eCore_mips64, 135 "mips64"}, 136 {eByteOrderBig, 8, 2, 4, llvm::Triple::mips64, ArchSpec::eCore_mips64r2, 137 "mips64r2"}, 138 {eByteOrderBig, 8, 2, 4, llvm::Triple::mips64, ArchSpec::eCore_mips64r3, 139 "mips64r3"}, 140 {eByteOrderBig, 8, 2, 4, llvm::Triple::mips64, ArchSpec::eCore_mips64r5, 141 "mips64r5"}, 142 {eByteOrderBig, 8, 2, 4, llvm::Triple::mips64, ArchSpec::eCore_mips64r6, 143 "mips64r6"}, 144 {eByteOrderLittle, 8, 2, 4, llvm::Triple::mips64el, 145 ArchSpec::eCore_mips64el, "mips64el"}, 146 {eByteOrderLittle, 8, 2, 4, llvm::Triple::mips64el, 147 ArchSpec::eCore_mips64r2el, "mips64r2el"}, 148 {eByteOrderLittle, 8, 2, 4, llvm::Triple::mips64el, 149 ArchSpec::eCore_mips64r3el, "mips64r3el"}, 150 {eByteOrderLittle, 8, 2, 4, llvm::Triple::mips64el, 151 ArchSpec::eCore_mips64r5el, "mips64r5el"}, 152 {eByteOrderLittle, 8, 2, 4, llvm::Triple::mips64el, 153 ArchSpec::eCore_mips64r6el, "mips64r6el"}, 154 155 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_generic, 156 "powerpc"}, 157 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc601, 158 "ppc601"}, 159 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc602, 160 "ppc602"}, 161 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc603, 162 "ppc603"}, 163 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc603e, 164 "ppc603e"}, 165 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc603ev, 166 "ppc603ev"}, 167 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc604, 168 "ppc604"}, 169 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc604e, 170 "ppc604e"}, 171 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc620, 172 "ppc620"}, 173 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc750, 174 "ppc750"}, 175 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc7400, 176 "ppc7400"}, 177 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc7450, 178 "ppc7450"}, 179 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc970, 180 "ppc970"}, 181 182 {eByteOrderLittle, 8, 4, 4, llvm::Triple::ppc64le, 183 ArchSpec::eCore_ppc64le_generic, "powerpc64le"}, 184 {eByteOrderBig, 8, 4, 4, llvm::Triple::ppc64, ArchSpec::eCore_ppc64_generic, 185 "powerpc64"}, 186 {eByteOrderBig, 8, 4, 4, llvm::Triple::ppc64, 187 ArchSpec::eCore_ppc64_ppc970_64, "ppc970-64"}, 188 189 {eByteOrderBig, 8, 2, 6, llvm::Triple::systemz, 190 ArchSpec::eCore_s390x_generic, "s390x"}, 191 192 {eByteOrderLittle, 4, 4, 4, llvm::Triple::sparc, 193 ArchSpec::eCore_sparc_generic, "sparc"}, 194 {eByteOrderLittle, 8, 4, 4, llvm::Triple::sparcv9, 195 ArchSpec::eCore_sparc9_generic, "sparcv9"}, 196 197 {eByteOrderLittle, 4, 1, 15, llvm::Triple::x86, ArchSpec::eCore_x86_32_i386, 198 "i386"}, 199 {eByteOrderLittle, 4, 1, 15, llvm::Triple::x86, ArchSpec::eCore_x86_32_i486, 200 "i486"}, 201 {eByteOrderLittle, 4, 1, 15, llvm::Triple::x86, 202 ArchSpec::eCore_x86_32_i486sx, "i486sx"}, 203 {eByteOrderLittle, 4, 1, 15, llvm::Triple::x86, ArchSpec::eCore_x86_32_i686, 204 "i686"}, 205 206 {eByteOrderLittle, 8, 1, 15, llvm::Triple::x86_64, 207 ArchSpec::eCore_x86_64_x86_64, "x86_64"}, 208 {eByteOrderLittle, 8, 1, 15, llvm::Triple::x86_64, 209 ArchSpec::eCore_x86_64_x86_64h, "x86_64h"}, 210 {eByteOrderLittle, 8, 1, 15, llvm::Triple::x86_64, 211 ArchSpec::eCore_x86_64_amd64, "amd64"}, 212 {eByteOrderLittle, 4, 4, 4, llvm::Triple::hexagon, 213 ArchSpec::eCore_hexagon_generic, "hexagon"}, 214 {eByteOrderLittle, 4, 4, 4, llvm::Triple::hexagon, 215 ArchSpec::eCore_hexagon_hexagonv4, "hexagonv4"}, 216 {eByteOrderLittle, 4, 4, 4, llvm::Triple::hexagon, 217 ArchSpec::eCore_hexagon_hexagonv5, "hexagonv5"}, 218 219 {eByteOrderLittle, 4, 2, 4, llvm::Triple::riscv32, ArchSpec::eCore_riscv32, 220 "riscv32"}, 221 {eByteOrderLittle, 8, 2, 4, llvm::Triple::riscv64, ArchSpec::eCore_riscv64, 222 "riscv64"}, 223 224 {eByteOrderLittle, 4, 4, 4, llvm::Triple::UnknownArch, 225 ArchSpec::eCore_uknownMach32, "unknown-mach-32"}, 226 {eByteOrderLittle, 8, 4, 4, llvm::Triple::UnknownArch, 227 ArchSpec::eCore_uknownMach64, "unknown-mach-64"}, 228 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arc, ArchSpec::eCore_arc, "arc"}, 229 230 {eByteOrderLittle, 2, 2, 4, llvm::Triple::avr, ArchSpec::eCore_avr, "avr"}, 231 232 {eByteOrderLittle, 4, 1, 4, llvm::Triple::wasm32, ArchSpec::eCore_wasm32, 233 "wasm32"}, 234 }; 235 236 // Ensure that we have an entry in the g_core_definitions for each core. If you 237 // comment out an entry above, you will need to comment out the corresponding 238 // ArchSpec::Core enumeration. 239 static_assert(sizeof(g_core_definitions) / sizeof(CoreDefinition) == 240 ArchSpec::kNumCores, 241 "make sure we have one core definition for each core"); 242 243 struct ArchDefinitionEntry { 244 ArchSpec::Core core; 245 uint32_t cpu; 246 uint32_t sub; 247 uint32_t cpu_mask; 248 uint32_t sub_mask; 249 }; 250 251 struct ArchDefinition { 252 ArchitectureType type; 253 size_t num_entries; 254 const ArchDefinitionEntry *entries; 255 const char *name; 256 }; 257 258 void ArchSpec::ListSupportedArchNames(StringList &list) { 259 for (uint32_t i = 0; i < llvm::array_lengthof(g_core_definitions); ++i) 260 list.AppendString(g_core_definitions[i].name); 261 } 262 263 void ArchSpec::AutoComplete(CompletionRequest &request) { 264 for (uint32_t i = 0; i < llvm::array_lengthof(g_core_definitions); ++i) 265 request.TryCompleteCurrentArg(g_core_definitions[i].name); 266 } 267 268 #define CPU_ANY (UINT32_MAX) 269 270 //===----------------------------------------------------------------------===// 271 // A table that gets searched linearly for matches. This table is used to 272 // convert cpu type and subtypes to architecture names, and to convert 273 // architecture names to cpu types and subtypes. The ordering is important and 274 // allows the precedence to be set when the table is built. 275 #define SUBTYPE_MASK 0x00FFFFFFu 276 277 // clang-format off 278 static const ArchDefinitionEntry g_macho_arch_entries[] = { 279 {ArchSpec::eCore_arm_generic, llvm::MachO::CPU_TYPE_ARM, CPU_ANY, UINT32_MAX, UINT32_MAX}, 280 {ArchSpec::eCore_arm_generic, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_ALL, UINT32_MAX, SUBTYPE_MASK}, 281 {ArchSpec::eCore_arm_armv4, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V4T, UINT32_MAX, SUBTYPE_MASK}, 282 {ArchSpec::eCore_arm_armv4t, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V4T, UINT32_MAX, SUBTYPE_MASK}, 283 {ArchSpec::eCore_arm_armv6, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V6, UINT32_MAX, SUBTYPE_MASK}, 284 {ArchSpec::eCore_arm_armv6m, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V6M, UINT32_MAX, SUBTYPE_MASK}, 285 {ArchSpec::eCore_arm_armv5, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V5TEJ, UINT32_MAX, SUBTYPE_MASK}, 286 {ArchSpec::eCore_arm_armv5e, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V5TEJ, UINT32_MAX, SUBTYPE_MASK}, 287 {ArchSpec::eCore_arm_armv5t, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V5TEJ, UINT32_MAX, SUBTYPE_MASK}, 288 {ArchSpec::eCore_arm_xscale, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_XSCALE, UINT32_MAX, SUBTYPE_MASK}, 289 {ArchSpec::eCore_arm_armv7, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V7, UINT32_MAX, SUBTYPE_MASK}, 290 {ArchSpec::eCore_arm_armv7f, llvm::MachO::CPU_TYPE_ARM, 10, UINT32_MAX, SUBTYPE_MASK}, 291 {ArchSpec::eCore_arm_armv7s, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V7S, UINT32_MAX, SUBTYPE_MASK}, 292 {ArchSpec::eCore_arm_armv7k, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V7K, UINT32_MAX, SUBTYPE_MASK}, 293 {ArchSpec::eCore_arm_armv7m, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V7M, UINT32_MAX, SUBTYPE_MASK}, 294 {ArchSpec::eCore_arm_armv7em, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V7EM, UINT32_MAX, SUBTYPE_MASK}, 295 {ArchSpec::eCore_arm_arm64e, llvm::MachO::CPU_TYPE_ARM64, llvm::MachO::CPU_SUBTYPE_ARM64E, UINT32_MAX, SUBTYPE_MASK}, 296 {ArchSpec::eCore_arm_arm64, llvm::MachO::CPU_TYPE_ARM64, llvm::MachO::CPU_SUBTYPE_ARM64_ALL, UINT32_MAX, SUBTYPE_MASK}, 297 {ArchSpec::eCore_arm_arm64, llvm::MachO::CPU_TYPE_ARM64, llvm::MachO::CPU_SUBTYPE_ARM64_V8, UINT32_MAX, SUBTYPE_MASK}, 298 {ArchSpec::eCore_arm_arm64, llvm::MachO::CPU_TYPE_ARM64, 13, UINT32_MAX, SUBTYPE_MASK}, 299 {ArchSpec::eCore_arm_arm64_32, llvm::MachO::CPU_TYPE_ARM64_32, 0, UINT32_MAX, SUBTYPE_MASK}, 300 {ArchSpec::eCore_arm_arm64_32, llvm::MachO::CPU_TYPE_ARM64_32, 1, UINT32_MAX, SUBTYPE_MASK}, 301 {ArchSpec::eCore_arm_arm64, llvm::MachO::CPU_TYPE_ARM64, CPU_ANY, UINT32_MAX, SUBTYPE_MASK}, 302 {ArchSpec::eCore_thumb, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_ALL, UINT32_MAX, SUBTYPE_MASK}, 303 {ArchSpec::eCore_thumbv4t, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V4T, UINT32_MAX, SUBTYPE_MASK}, 304 {ArchSpec::eCore_thumbv5, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V5, UINT32_MAX, SUBTYPE_MASK}, 305 {ArchSpec::eCore_thumbv5e, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V5, UINT32_MAX, SUBTYPE_MASK}, 306 {ArchSpec::eCore_thumbv6, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V6, UINT32_MAX, SUBTYPE_MASK}, 307 {ArchSpec::eCore_thumbv6m, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V6M, UINT32_MAX, SUBTYPE_MASK}, 308 {ArchSpec::eCore_thumbv7, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V7, UINT32_MAX, SUBTYPE_MASK}, 309 {ArchSpec::eCore_thumbv7f, llvm::MachO::CPU_TYPE_ARM, 10, UINT32_MAX, SUBTYPE_MASK}, 310 {ArchSpec::eCore_thumbv7s, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V7S, UINT32_MAX, SUBTYPE_MASK}, 311 {ArchSpec::eCore_thumbv7k, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V7K, UINT32_MAX, SUBTYPE_MASK}, 312 {ArchSpec::eCore_thumbv7m, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V7M, UINT32_MAX, SUBTYPE_MASK}, 313 {ArchSpec::eCore_thumbv7em, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V7EM, UINT32_MAX, SUBTYPE_MASK}, 314 {ArchSpec::eCore_ppc_generic, llvm::MachO::CPU_TYPE_POWERPC, CPU_ANY, UINT32_MAX, UINT32_MAX}, 315 {ArchSpec::eCore_ppc_generic, llvm::MachO::CPU_TYPE_POWERPC, llvm::MachO::CPU_SUBTYPE_POWERPC_ALL, UINT32_MAX, SUBTYPE_MASK}, 316 {ArchSpec::eCore_ppc_ppc601, llvm::MachO::CPU_TYPE_POWERPC, llvm::MachO::CPU_SUBTYPE_POWERPC_601, UINT32_MAX, SUBTYPE_MASK}, 317 {ArchSpec::eCore_ppc_ppc602, llvm::MachO::CPU_TYPE_POWERPC, llvm::MachO::CPU_SUBTYPE_POWERPC_602, UINT32_MAX, SUBTYPE_MASK}, 318 {ArchSpec::eCore_ppc_ppc603, llvm::MachO::CPU_TYPE_POWERPC, llvm::MachO::CPU_SUBTYPE_POWERPC_603, UINT32_MAX, SUBTYPE_MASK}, 319 {ArchSpec::eCore_ppc_ppc603e, llvm::MachO::CPU_TYPE_POWERPC, llvm::MachO::CPU_SUBTYPE_POWERPC_603e, UINT32_MAX, SUBTYPE_MASK}, 320 {ArchSpec::eCore_ppc_ppc603ev, llvm::MachO::CPU_TYPE_POWERPC, llvm::MachO::CPU_SUBTYPE_POWERPC_603ev, UINT32_MAX, SUBTYPE_MASK}, 321 {ArchSpec::eCore_ppc_ppc604, llvm::MachO::CPU_TYPE_POWERPC, llvm::MachO::CPU_SUBTYPE_POWERPC_604, UINT32_MAX, SUBTYPE_MASK}, 322 {ArchSpec::eCore_ppc_ppc604e, llvm::MachO::CPU_TYPE_POWERPC, llvm::MachO::CPU_SUBTYPE_POWERPC_604e, UINT32_MAX, SUBTYPE_MASK}, 323 {ArchSpec::eCore_ppc_ppc620, llvm::MachO::CPU_TYPE_POWERPC, llvm::MachO::CPU_SUBTYPE_POWERPC_620, UINT32_MAX, SUBTYPE_MASK}, 324 {ArchSpec::eCore_ppc_ppc750, llvm::MachO::CPU_TYPE_POWERPC, llvm::MachO::CPU_SUBTYPE_POWERPC_750, UINT32_MAX, SUBTYPE_MASK}, 325 {ArchSpec::eCore_ppc_ppc7400, llvm::MachO::CPU_TYPE_POWERPC, llvm::MachO::CPU_SUBTYPE_POWERPC_7400, UINT32_MAX, SUBTYPE_MASK}, 326 {ArchSpec::eCore_ppc_ppc7450, llvm::MachO::CPU_TYPE_POWERPC, llvm::MachO::CPU_SUBTYPE_POWERPC_7450, UINT32_MAX, SUBTYPE_MASK}, 327 {ArchSpec::eCore_ppc_ppc970, llvm::MachO::CPU_TYPE_POWERPC, llvm::MachO::CPU_SUBTYPE_POWERPC_970, UINT32_MAX, SUBTYPE_MASK}, 328 {ArchSpec::eCore_ppc64_generic, llvm::MachO::CPU_TYPE_POWERPC64, llvm::MachO::CPU_SUBTYPE_POWERPC_ALL, UINT32_MAX, SUBTYPE_MASK}, 329 {ArchSpec::eCore_ppc64le_generic, llvm::MachO::CPU_TYPE_POWERPC64, CPU_ANY, UINT32_MAX, SUBTYPE_MASK}, 330 {ArchSpec::eCore_ppc64_ppc970_64, llvm::MachO::CPU_TYPE_POWERPC64, 100, UINT32_MAX, SUBTYPE_MASK}, 331 {ArchSpec::eCore_x86_32_i386, llvm::MachO::CPU_TYPE_I386, llvm::MachO::CPU_SUBTYPE_I386_ALL, UINT32_MAX, SUBTYPE_MASK}, 332 {ArchSpec::eCore_x86_32_i486, llvm::MachO::CPU_TYPE_I386, llvm::MachO::CPU_SUBTYPE_486, UINT32_MAX, SUBTYPE_MASK}, 333 {ArchSpec::eCore_x86_32_i486sx, llvm::MachO::CPU_TYPE_I386, llvm::MachO::CPU_SUBTYPE_486SX, UINT32_MAX, SUBTYPE_MASK}, 334 {ArchSpec::eCore_x86_32_i386, llvm::MachO::CPU_TYPE_I386, CPU_ANY, UINT32_MAX, UINT32_MAX}, 335 {ArchSpec::eCore_x86_64_x86_64, llvm::MachO::CPU_TYPE_X86_64, llvm::MachO::CPU_SUBTYPE_X86_64_ALL, UINT32_MAX, SUBTYPE_MASK}, 336 {ArchSpec::eCore_x86_64_x86_64, llvm::MachO::CPU_TYPE_X86_64, llvm::MachO::CPU_SUBTYPE_X86_ARCH1, UINT32_MAX, SUBTYPE_MASK}, 337 {ArchSpec::eCore_x86_64_x86_64h, llvm::MachO::CPU_TYPE_X86_64, llvm::MachO::CPU_SUBTYPE_X86_64_H, UINT32_MAX, SUBTYPE_MASK}, 338 {ArchSpec::eCore_x86_64_x86_64, llvm::MachO::CPU_TYPE_X86_64, CPU_ANY, UINT32_MAX, UINT32_MAX}, 339 // Catch any unknown mach architectures so we can always use the object and symbol mach-o files 340 {ArchSpec::eCore_uknownMach32, 0, 0, 0xFF000000u, 0x00000000u}, 341 {ArchSpec::eCore_uknownMach64, llvm::MachO::CPU_ARCH_ABI64, 0, 0xFF000000u, 0x00000000u}}; 342 // clang-format on 343 344 static const ArchDefinition g_macho_arch_def = { 345 eArchTypeMachO, llvm::array_lengthof(g_macho_arch_entries), 346 g_macho_arch_entries, "mach-o"}; 347 348 //===----------------------------------------------------------------------===// 349 // A table that gets searched linearly for matches. This table is used to 350 // convert cpu type and subtypes to architecture names, and to convert 351 // architecture names to cpu types and subtypes. The ordering is important and 352 // allows the precedence to be set when the table is built. 353 static const ArchDefinitionEntry g_elf_arch_entries[] = { 354 {ArchSpec::eCore_sparc_generic, llvm::ELF::EM_SPARC, LLDB_INVALID_CPUTYPE, 355 0xFFFFFFFFu, 0xFFFFFFFFu}, // Sparc 356 {ArchSpec::eCore_x86_32_i386, llvm::ELF::EM_386, LLDB_INVALID_CPUTYPE, 357 0xFFFFFFFFu, 0xFFFFFFFFu}, // Intel 80386 358 {ArchSpec::eCore_x86_32_i486, llvm::ELF::EM_IAMCU, LLDB_INVALID_CPUTYPE, 359 0xFFFFFFFFu, 0xFFFFFFFFu}, // Intel MCU // FIXME: is this correct? 360 {ArchSpec::eCore_ppc_generic, llvm::ELF::EM_PPC, LLDB_INVALID_CPUTYPE, 361 0xFFFFFFFFu, 0xFFFFFFFFu}, // PowerPC 362 {ArchSpec::eCore_ppc64le_generic, llvm::ELF::EM_PPC64, LLDB_INVALID_CPUTYPE, 363 0xFFFFFFFFu, 0xFFFFFFFFu}, // PowerPC64le 364 {ArchSpec::eCore_ppc64_generic, llvm::ELF::EM_PPC64, LLDB_INVALID_CPUTYPE, 365 0xFFFFFFFFu, 0xFFFFFFFFu}, // PowerPC64 366 {ArchSpec::eCore_arm_generic, llvm::ELF::EM_ARM, LLDB_INVALID_CPUTYPE, 367 0xFFFFFFFFu, 0xFFFFFFFFu}, // ARM 368 {ArchSpec::eCore_arm_aarch64, llvm::ELF::EM_AARCH64, LLDB_INVALID_CPUTYPE, 369 0xFFFFFFFFu, 0xFFFFFFFFu}, // ARM64 370 {ArchSpec::eCore_s390x_generic, llvm::ELF::EM_S390, LLDB_INVALID_CPUTYPE, 371 0xFFFFFFFFu, 0xFFFFFFFFu}, // SystemZ 372 {ArchSpec::eCore_sparc9_generic, llvm::ELF::EM_SPARCV9, 373 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // SPARC V9 374 {ArchSpec::eCore_x86_64_x86_64, llvm::ELF::EM_X86_64, LLDB_INVALID_CPUTYPE, 375 0xFFFFFFFFu, 0xFFFFFFFFu}, // AMD64 376 {ArchSpec::eCore_mips32, llvm::ELF::EM_MIPS, ArchSpec::eMIPSSubType_mips32, 377 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32 378 {ArchSpec::eCore_mips32r2, llvm::ELF::EM_MIPS, 379 ArchSpec::eMIPSSubType_mips32r2, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32r2 380 {ArchSpec::eCore_mips32r6, llvm::ELF::EM_MIPS, 381 ArchSpec::eMIPSSubType_mips32r6, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32r6 382 {ArchSpec::eCore_mips32el, llvm::ELF::EM_MIPS, 383 ArchSpec::eMIPSSubType_mips32el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32el 384 {ArchSpec::eCore_mips32r2el, llvm::ELF::EM_MIPS, 385 ArchSpec::eMIPSSubType_mips32r2el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32r2el 386 {ArchSpec::eCore_mips32r6el, llvm::ELF::EM_MIPS, 387 ArchSpec::eMIPSSubType_mips32r6el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32r6el 388 {ArchSpec::eCore_mips64, llvm::ELF::EM_MIPS, ArchSpec::eMIPSSubType_mips64, 389 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64 390 {ArchSpec::eCore_mips64r2, llvm::ELF::EM_MIPS, 391 ArchSpec::eMIPSSubType_mips64r2, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64r2 392 {ArchSpec::eCore_mips64r6, llvm::ELF::EM_MIPS, 393 ArchSpec::eMIPSSubType_mips64r6, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64r6 394 {ArchSpec::eCore_mips64el, llvm::ELF::EM_MIPS, 395 ArchSpec::eMIPSSubType_mips64el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64el 396 {ArchSpec::eCore_mips64r2el, llvm::ELF::EM_MIPS, 397 ArchSpec::eMIPSSubType_mips64r2el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64r2el 398 {ArchSpec::eCore_mips64r6el, llvm::ELF::EM_MIPS, 399 ArchSpec::eMIPSSubType_mips64r6el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64r6el 400 {ArchSpec::eCore_hexagon_generic, llvm::ELF::EM_HEXAGON, 401 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // HEXAGON 402 {ArchSpec::eCore_arc, llvm::ELF::EM_ARC_COMPACT2, LLDB_INVALID_CPUTYPE, 403 0xFFFFFFFFu, 0xFFFFFFFFu}, // ARC 404 {ArchSpec::eCore_avr, llvm::ELF::EM_AVR, LLDB_INVALID_CPUTYPE, 405 0xFFFFFFFFu, 0xFFFFFFFFu}, // AVR 406 {ArchSpec::eCore_riscv32, llvm::ELF::EM_RISCV, 407 ArchSpec::eRISCVSubType_riscv32, 0xFFFFFFFFu, 0xFFFFFFFFu}, // riscv32 408 {ArchSpec::eCore_riscv64, llvm::ELF::EM_RISCV, 409 ArchSpec::eRISCVSubType_riscv64, 0xFFFFFFFFu, 0xFFFFFFFFu}, // riscv64 410 }; 411 412 static const ArchDefinition g_elf_arch_def = { 413 eArchTypeELF, 414 llvm::array_lengthof(g_elf_arch_entries), 415 g_elf_arch_entries, 416 "elf", 417 }; 418 419 static const ArchDefinitionEntry g_coff_arch_entries[] = { 420 {ArchSpec::eCore_x86_32_i386, llvm::COFF::IMAGE_FILE_MACHINE_I386, 421 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // Intel 80x86 422 {ArchSpec::eCore_ppc_generic, llvm::COFF::IMAGE_FILE_MACHINE_POWERPC, 423 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // PowerPC 424 {ArchSpec::eCore_ppc_generic, llvm::COFF::IMAGE_FILE_MACHINE_POWERPCFP, 425 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // PowerPC (with FPU) 426 {ArchSpec::eCore_arm_generic, llvm::COFF::IMAGE_FILE_MACHINE_ARM, 427 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // ARM 428 {ArchSpec::eCore_arm_armv7, llvm::COFF::IMAGE_FILE_MACHINE_ARMNT, 429 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // ARMv7 430 {ArchSpec::eCore_thumb, llvm::COFF::IMAGE_FILE_MACHINE_THUMB, 431 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // ARMv7 432 {ArchSpec::eCore_x86_64_x86_64, llvm::COFF::IMAGE_FILE_MACHINE_AMD64, 433 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // AMD64 434 {ArchSpec::eCore_arm_arm64, llvm::COFF::IMAGE_FILE_MACHINE_ARM64, 435 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu} // ARM64 436 }; 437 438 static const ArchDefinition g_coff_arch_def = { 439 eArchTypeCOFF, 440 llvm::array_lengthof(g_coff_arch_entries), 441 g_coff_arch_entries, 442 "pe-coff", 443 }; 444 445 //===----------------------------------------------------------------------===// 446 // Table of all ArchDefinitions 447 static const ArchDefinition *g_arch_definitions[] = { 448 &g_macho_arch_def, &g_elf_arch_def, &g_coff_arch_def}; 449 450 static const size_t k_num_arch_definitions = 451 llvm::array_lengthof(g_arch_definitions); 452 453 //===----------------------------------------------------------------------===// 454 // Static helper functions. 455 456 // Get the architecture definition for a given object type. 457 static const ArchDefinition *FindArchDefinition(ArchitectureType arch_type) { 458 for (unsigned int i = 0; i < k_num_arch_definitions; ++i) { 459 const ArchDefinition *def = g_arch_definitions[i]; 460 if (def->type == arch_type) 461 return def; 462 } 463 return nullptr; 464 } 465 466 // Get an architecture definition by name. 467 static const CoreDefinition *FindCoreDefinition(llvm::StringRef name) { 468 for (unsigned int i = 0; i < llvm::array_lengthof(g_core_definitions); ++i) { 469 if (name.equals_insensitive(g_core_definitions[i].name)) 470 return &g_core_definitions[i]; 471 } 472 return nullptr; 473 } 474 475 static inline const CoreDefinition *FindCoreDefinition(ArchSpec::Core core) { 476 if (core < llvm::array_lengthof(g_core_definitions)) 477 return &g_core_definitions[core]; 478 return nullptr; 479 } 480 481 // Get a definition entry by cpu type and subtype. 482 static const ArchDefinitionEntry * 483 FindArchDefinitionEntry(const ArchDefinition *def, uint32_t cpu, uint32_t sub) { 484 if (def == nullptr) 485 return nullptr; 486 487 const ArchDefinitionEntry *entries = def->entries; 488 for (size_t i = 0; i < def->num_entries; ++i) { 489 if (entries[i].cpu == (cpu & entries[i].cpu_mask)) 490 if (entries[i].sub == (sub & entries[i].sub_mask)) 491 return &entries[i]; 492 } 493 return nullptr; 494 } 495 496 static const ArchDefinitionEntry * 497 FindArchDefinitionEntry(const ArchDefinition *def, ArchSpec::Core core) { 498 if (def == nullptr) 499 return nullptr; 500 501 const ArchDefinitionEntry *entries = def->entries; 502 for (size_t i = 0; i < def->num_entries; ++i) { 503 if (entries[i].core == core) 504 return &entries[i]; 505 } 506 return nullptr; 507 } 508 509 //===----------------------------------------------------------------------===// 510 // Constructors and destructors. 511 512 ArchSpec::ArchSpec() = default; 513 514 ArchSpec::ArchSpec(const char *triple_cstr) { 515 if (triple_cstr) 516 SetTriple(triple_cstr); 517 } 518 519 ArchSpec::ArchSpec(llvm::StringRef triple_str) { SetTriple(triple_str); } 520 521 ArchSpec::ArchSpec(const llvm::Triple &triple) { SetTriple(triple); } 522 523 ArchSpec::ArchSpec(ArchitectureType arch_type, uint32_t cpu, uint32_t subtype) { 524 SetArchitecture(arch_type, cpu, subtype); 525 } 526 527 ArchSpec::~ArchSpec() = default; 528 529 void ArchSpec::Clear() { 530 m_triple = llvm::Triple(); 531 m_core = kCore_invalid; 532 m_byte_order = eByteOrderInvalid; 533 m_distribution_id.Clear(); 534 m_flags = 0; 535 } 536 537 //===----------------------------------------------------------------------===// 538 // Predicates. 539 540 const char *ArchSpec::GetArchitectureName() const { 541 const CoreDefinition *core_def = FindCoreDefinition(m_core); 542 if (core_def) 543 return core_def->name; 544 return "unknown"; 545 } 546 547 bool ArchSpec::IsMIPS() const { return GetTriple().isMIPS(); } 548 549 std::string ArchSpec::GetTargetABI() const { 550 551 std::string abi; 552 553 if (IsMIPS()) { 554 switch (GetFlags() & ArchSpec::eMIPSABI_mask) { 555 case ArchSpec::eMIPSABI_N64: 556 abi = "n64"; 557 return abi; 558 case ArchSpec::eMIPSABI_N32: 559 abi = "n32"; 560 return abi; 561 case ArchSpec::eMIPSABI_O32: 562 abi = "o32"; 563 return abi; 564 default: 565 return abi; 566 } 567 } 568 return abi; 569 } 570 571 void ArchSpec::SetFlags(const std::string &elf_abi) { 572 573 uint32_t flag = GetFlags(); 574 if (IsMIPS()) { 575 if (elf_abi == "n64") 576 flag |= ArchSpec::eMIPSABI_N64; 577 else if (elf_abi == "n32") 578 flag |= ArchSpec::eMIPSABI_N32; 579 else if (elf_abi == "o32") 580 flag |= ArchSpec::eMIPSABI_O32; 581 } 582 SetFlags(flag); 583 } 584 585 std::string ArchSpec::GetClangTargetCPU() const { 586 std::string cpu; 587 588 if (IsMIPS()) { 589 switch (m_core) { 590 case ArchSpec::eCore_mips32: 591 case ArchSpec::eCore_mips32el: 592 cpu = "mips32"; 593 break; 594 case ArchSpec::eCore_mips32r2: 595 case ArchSpec::eCore_mips32r2el: 596 cpu = "mips32r2"; 597 break; 598 case ArchSpec::eCore_mips32r3: 599 case ArchSpec::eCore_mips32r3el: 600 cpu = "mips32r3"; 601 break; 602 case ArchSpec::eCore_mips32r5: 603 case ArchSpec::eCore_mips32r5el: 604 cpu = "mips32r5"; 605 break; 606 case ArchSpec::eCore_mips32r6: 607 case ArchSpec::eCore_mips32r6el: 608 cpu = "mips32r6"; 609 break; 610 case ArchSpec::eCore_mips64: 611 case ArchSpec::eCore_mips64el: 612 cpu = "mips64"; 613 break; 614 case ArchSpec::eCore_mips64r2: 615 case ArchSpec::eCore_mips64r2el: 616 cpu = "mips64r2"; 617 break; 618 case ArchSpec::eCore_mips64r3: 619 case ArchSpec::eCore_mips64r3el: 620 cpu = "mips64r3"; 621 break; 622 case ArchSpec::eCore_mips64r5: 623 case ArchSpec::eCore_mips64r5el: 624 cpu = "mips64r5"; 625 break; 626 case ArchSpec::eCore_mips64r6: 627 case ArchSpec::eCore_mips64r6el: 628 cpu = "mips64r6"; 629 break; 630 default: 631 break; 632 } 633 } 634 return cpu; 635 } 636 637 uint32_t ArchSpec::GetMachOCPUType() const { 638 const CoreDefinition *core_def = FindCoreDefinition(m_core); 639 if (core_def) { 640 const ArchDefinitionEntry *arch_def = 641 FindArchDefinitionEntry(&g_macho_arch_def, core_def->core); 642 if (arch_def) { 643 return arch_def->cpu; 644 } 645 } 646 return LLDB_INVALID_CPUTYPE; 647 } 648 649 uint32_t ArchSpec::GetMachOCPUSubType() const { 650 const CoreDefinition *core_def = FindCoreDefinition(m_core); 651 if (core_def) { 652 const ArchDefinitionEntry *arch_def = 653 FindArchDefinitionEntry(&g_macho_arch_def, core_def->core); 654 if (arch_def) { 655 return arch_def->sub; 656 } 657 } 658 return LLDB_INVALID_CPUTYPE; 659 } 660 661 uint32_t ArchSpec::GetDataByteSize() const { 662 return 1; 663 } 664 665 uint32_t ArchSpec::GetCodeByteSize() const { 666 return 1; 667 } 668 669 llvm::Triple::ArchType ArchSpec::GetMachine() const { 670 const CoreDefinition *core_def = FindCoreDefinition(m_core); 671 if (core_def) 672 return core_def->machine; 673 674 return llvm::Triple::UnknownArch; 675 } 676 677 ConstString ArchSpec::GetDistributionId() const { 678 return m_distribution_id; 679 } 680 681 void ArchSpec::SetDistributionId(const char *distribution_id) { 682 m_distribution_id.SetCString(distribution_id); 683 } 684 685 uint32_t ArchSpec::GetAddressByteSize() const { 686 const CoreDefinition *core_def = FindCoreDefinition(m_core); 687 if (core_def) { 688 if (core_def->machine == llvm::Triple::mips64 || 689 core_def->machine == llvm::Triple::mips64el) { 690 // For N32/O32 applications Address size is 4 bytes. 691 if (m_flags & (eMIPSABI_N32 | eMIPSABI_O32)) 692 return 4; 693 } 694 return core_def->addr_byte_size; 695 } 696 return 0; 697 } 698 699 ByteOrder ArchSpec::GetDefaultEndian() const { 700 const CoreDefinition *core_def = FindCoreDefinition(m_core); 701 if (core_def) 702 return core_def->default_byte_order; 703 return eByteOrderInvalid; 704 } 705 706 bool ArchSpec::CharIsSignedByDefault() const { 707 switch (m_triple.getArch()) { 708 default: 709 return true; 710 711 case llvm::Triple::aarch64: 712 case llvm::Triple::aarch64_32: 713 case llvm::Triple::aarch64_be: 714 case llvm::Triple::arm: 715 case llvm::Triple::armeb: 716 case llvm::Triple::thumb: 717 case llvm::Triple::thumbeb: 718 return m_triple.isOSDarwin() || m_triple.isOSWindows(); 719 720 case llvm::Triple::ppc: 721 case llvm::Triple::ppc64: 722 return m_triple.isOSDarwin(); 723 724 case llvm::Triple::ppc64le: 725 case llvm::Triple::systemz: 726 case llvm::Triple::xcore: 727 case llvm::Triple::arc: 728 return false; 729 } 730 } 731 732 lldb::ByteOrder ArchSpec::GetByteOrder() const { 733 if (m_byte_order == eByteOrderInvalid) 734 return GetDefaultEndian(); 735 return m_byte_order; 736 } 737 738 //===----------------------------------------------------------------------===// 739 // Mutators. 740 741 bool ArchSpec::SetTriple(const llvm::Triple &triple) { 742 m_triple = triple; 743 UpdateCore(); 744 return IsValid(); 745 } 746 747 bool lldb_private::ParseMachCPUDashSubtypeTriple(llvm::StringRef triple_str, 748 ArchSpec &arch) { 749 // Accept "12-10" or "12.10" as cpu type/subtype 750 if (triple_str.empty()) 751 return false; 752 753 size_t pos = triple_str.find_first_of("-."); 754 if (pos == llvm::StringRef::npos) 755 return false; 756 757 llvm::StringRef cpu_str = triple_str.substr(0, pos); 758 llvm::StringRef remainder = triple_str.substr(pos + 1); 759 if (cpu_str.empty() || remainder.empty()) 760 return false; 761 762 llvm::StringRef sub_str; 763 llvm::StringRef vendor; 764 llvm::StringRef os; 765 std::tie(sub_str, remainder) = remainder.split('-'); 766 std::tie(vendor, os) = remainder.split('-'); 767 768 uint32_t cpu = 0; 769 uint32_t sub = 0; 770 if (cpu_str.getAsInteger(10, cpu) || sub_str.getAsInteger(10, sub)) 771 return false; 772 773 if (!arch.SetArchitecture(eArchTypeMachO, cpu, sub)) 774 return false; 775 if (!vendor.empty() && !os.empty()) { 776 arch.GetTriple().setVendorName(vendor); 777 arch.GetTriple().setOSName(os); 778 } 779 780 return true; 781 } 782 783 bool ArchSpec::SetTriple(llvm::StringRef triple) { 784 if (triple.empty()) { 785 Clear(); 786 return false; 787 } 788 789 if (ParseMachCPUDashSubtypeTriple(triple, *this)) 790 return true; 791 792 SetTriple(llvm::Triple(llvm::Triple::normalize(triple))); 793 return IsValid(); 794 } 795 796 bool ArchSpec::ContainsOnlyArch(const llvm::Triple &normalized_triple) { 797 return !normalized_triple.getArchName().empty() && 798 normalized_triple.getOSName().empty() && 799 normalized_triple.getVendorName().empty() && 800 normalized_triple.getEnvironmentName().empty(); 801 } 802 803 void ArchSpec::MergeFrom(const ArchSpec &other) { 804 // ios-macabi always wins over macosx. 805 if ((GetTriple().getOS() == llvm::Triple::MacOSX || 806 GetTriple().getOS() == llvm::Triple::UnknownOS) && 807 other.GetTriple().getOS() == llvm::Triple::IOS && 808 other.GetTriple().getEnvironment() == llvm::Triple::MacABI) { 809 (*this) = other; 810 return; 811 } 812 813 if (!TripleVendorWasSpecified() && other.TripleVendorWasSpecified()) 814 GetTriple().setVendor(other.GetTriple().getVendor()); 815 if (!TripleOSWasSpecified() && other.TripleOSWasSpecified()) 816 GetTriple().setOS(other.GetTriple().getOS()); 817 if (GetTriple().getArch() == llvm::Triple::UnknownArch) { 818 GetTriple().setArch(other.GetTriple().getArch()); 819 820 // MachO unknown64 isn't really invalid as the debugger can still obtain 821 // information from the binary, e.g. line tables. As such, we don't update 822 // the core here. 823 if (other.GetCore() != eCore_uknownMach64) 824 UpdateCore(); 825 } 826 if (!TripleEnvironmentWasSpecified() && 827 other.TripleEnvironmentWasSpecified()) { 828 GetTriple().setEnvironment(other.GetTriple().getEnvironment()); 829 } 830 // If this and other are both arm ArchSpecs and this ArchSpec is a generic 831 // "some kind of arm" spec but the other ArchSpec is a specific arm core, 832 // adopt the specific arm core. 833 if (GetTriple().getArch() == llvm::Triple::arm && 834 other.GetTriple().getArch() == llvm::Triple::arm && 835 IsCompatibleMatch(other) && GetCore() == ArchSpec::eCore_arm_generic && 836 other.GetCore() != ArchSpec::eCore_arm_generic) { 837 m_core = other.GetCore(); 838 CoreUpdated(false); 839 } 840 if (GetFlags() == 0) { 841 SetFlags(other.GetFlags()); 842 } 843 } 844 845 bool ArchSpec::SetArchitecture(ArchitectureType arch_type, uint32_t cpu, 846 uint32_t sub, uint32_t os) { 847 m_core = kCore_invalid; 848 bool update_triple = true; 849 const ArchDefinition *arch_def = FindArchDefinition(arch_type); 850 if (arch_def) { 851 const ArchDefinitionEntry *arch_def_entry = 852 FindArchDefinitionEntry(arch_def, cpu, sub); 853 if (arch_def_entry) { 854 const CoreDefinition *core_def = FindCoreDefinition(arch_def_entry->core); 855 if (core_def) { 856 m_core = core_def->core; 857 update_triple = false; 858 // Always use the architecture name because it might be more 859 // descriptive than the architecture enum ("armv7" -> 860 // llvm::Triple::arm). 861 m_triple.setArchName(llvm::StringRef(core_def->name)); 862 if (arch_type == eArchTypeMachO) { 863 m_triple.setVendor(llvm::Triple::Apple); 864 865 // Don't set the OS. It could be simulator, macosx, ios, watchos, 866 // tvos, bridgeos. We could get close with the cpu type - but we 867 // can't get it right all of the time. Better to leave this unset 868 // so other sections of code will set it when they have more 869 // information. NB: don't call m_triple.setOS 870 // (llvm::Triple::UnknownOS). That sets the OSName to "unknown" and 871 // the ArchSpec::TripleVendorWasSpecified() method says that any 872 // OSName setting means it was specified. 873 } else if (arch_type == eArchTypeELF) { 874 switch (os) { 875 case llvm::ELF::ELFOSABI_AIX: 876 m_triple.setOS(llvm::Triple::OSType::AIX); 877 break; 878 case llvm::ELF::ELFOSABI_FREEBSD: 879 m_triple.setOS(llvm::Triple::OSType::FreeBSD); 880 break; 881 case llvm::ELF::ELFOSABI_GNU: 882 m_triple.setOS(llvm::Triple::OSType::Linux); 883 break; 884 case llvm::ELF::ELFOSABI_NETBSD: 885 m_triple.setOS(llvm::Triple::OSType::NetBSD); 886 break; 887 case llvm::ELF::ELFOSABI_OPENBSD: 888 m_triple.setOS(llvm::Triple::OSType::OpenBSD); 889 break; 890 case llvm::ELF::ELFOSABI_SOLARIS: 891 m_triple.setOS(llvm::Triple::OSType::Solaris); 892 break; 893 } 894 } else if (arch_type == eArchTypeCOFF && os == llvm::Triple::Win32) { 895 m_triple.setVendor(llvm::Triple::PC); 896 m_triple.setOS(llvm::Triple::Win32); 897 } else { 898 m_triple.setVendor(llvm::Triple::UnknownVendor); 899 m_triple.setOS(llvm::Triple::UnknownOS); 900 } 901 // Fall back onto setting the machine type if the arch by name 902 // failed... 903 if (m_triple.getArch() == llvm::Triple::UnknownArch) 904 m_triple.setArch(core_def->machine); 905 } 906 } else { 907 Log *log(lldb_private::GetLogIfAnyCategoriesSet(LIBLLDB_LOG_TARGET | LIBLLDB_LOG_PROCESS | LIBLLDB_LOG_PLATFORM)); 908 LLDB_LOGF(log, 909 "Unable to find a core definition for cpu 0x%" PRIx32 910 " sub %" PRId32, 911 cpu, sub); 912 } 913 } 914 CoreUpdated(update_triple); 915 return IsValid(); 916 } 917 918 uint32_t ArchSpec::GetMinimumOpcodeByteSize() const { 919 const CoreDefinition *core_def = FindCoreDefinition(m_core); 920 if (core_def) 921 return core_def->min_opcode_byte_size; 922 return 0; 923 } 924 925 uint32_t ArchSpec::GetMaximumOpcodeByteSize() const { 926 const CoreDefinition *core_def = FindCoreDefinition(m_core); 927 if (core_def) 928 return core_def->max_opcode_byte_size; 929 return 0; 930 } 931 932 bool ArchSpec::IsExactMatch(const ArchSpec &rhs) const { 933 return IsEqualTo(rhs, true); 934 } 935 936 bool ArchSpec::IsCompatibleMatch(const ArchSpec &rhs) const { 937 return IsEqualTo(rhs, false); 938 } 939 940 static bool IsCompatibleEnvironment(llvm::Triple::EnvironmentType lhs, 941 llvm::Triple::EnvironmentType rhs) { 942 if (lhs == rhs) 943 return true; 944 945 // Apple simulators are a different platform than what they simulate. 946 // As the environments are different at this point, if one of them is a 947 // simulator, then they are different. 948 if (lhs == llvm::Triple::Simulator || rhs == llvm::Triple::Simulator) 949 return false; 950 951 // If any of the environment is unknown then they are compatible 952 if (lhs == llvm::Triple::UnknownEnvironment || 953 rhs == llvm::Triple::UnknownEnvironment) 954 return true; 955 956 // If one of the environment is Android and the other one is EABI then they 957 // are considered to be compatible. This is required as a workaround for 958 // shared libraries compiled for Android without the NOTE section indicating 959 // that they are using the Android ABI. 960 if ((lhs == llvm::Triple::Android && rhs == llvm::Triple::EABI) || 961 (rhs == llvm::Triple::Android && lhs == llvm::Triple::EABI) || 962 (lhs == llvm::Triple::GNUEABI && rhs == llvm::Triple::EABI) || 963 (rhs == llvm::Triple::GNUEABI && lhs == llvm::Triple::EABI) || 964 (lhs == llvm::Triple::GNUEABIHF && rhs == llvm::Triple::EABIHF) || 965 (rhs == llvm::Triple::GNUEABIHF && lhs == llvm::Triple::EABIHF)) 966 return true; 967 968 return false; 969 } 970 971 bool ArchSpec::IsEqualTo(const ArchSpec &rhs, bool exact_match) const { 972 // explicitly ignoring m_distribution_id in this method. 973 974 if (GetByteOrder() != rhs.GetByteOrder() || 975 !cores_match(GetCore(), rhs.GetCore(), true, exact_match)) 976 return false; 977 978 const llvm::Triple &lhs_triple = GetTriple(); 979 const llvm::Triple &rhs_triple = rhs.GetTriple(); 980 981 const llvm::Triple::VendorType lhs_triple_vendor = lhs_triple.getVendor(); 982 const llvm::Triple::VendorType rhs_triple_vendor = rhs_triple.getVendor(); 983 if (lhs_triple_vendor != rhs_triple_vendor) { 984 const bool rhs_vendor_specified = rhs.TripleVendorWasSpecified(); 985 const bool lhs_vendor_specified = TripleVendorWasSpecified(); 986 // Both architectures had the vendor specified, so if they aren't equal 987 // then we return false 988 if (rhs_vendor_specified && lhs_vendor_specified) 989 return false; 990 991 // Only fail if both vendor types are not unknown 992 if (lhs_triple_vendor != llvm::Triple::UnknownVendor && 993 rhs_triple_vendor != llvm::Triple::UnknownVendor) 994 return false; 995 } 996 997 const llvm::Triple::OSType lhs_triple_os = lhs_triple.getOS(); 998 const llvm::Triple::OSType rhs_triple_os = rhs_triple.getOS(); 999 const llvm::Triple::EnvironmentType lhs_triple_env = 1000 lhs_triple.getEnvironment(); 1001 const llvm::Triple::EnvironmentType rhs_triple_env = 1002 rhs_triple.getEnvironment(); 1003 1004 if (!exact_match) { 1005 // x86_64-apple-ios-macabi, x86_64-apple-macosx are compatible, no match. 1006 if ((lhs_triple_os == llvm::Triple::IOS && 1007 lhs_triple_env == llvm::Triple::MacABI && 1008 rhs_triple_os == llvm::Triple::MacOSX) || 1009 (lhs_triple_os == llvm::Triple::MacOSX && 1010 rhs_triple_os == llvm::Triple::IOS && 1011 rhs_triple_env == llvm::Triple::MacABI)) 1012 return true; 1013 } 1014 1015 // x86_64-apple-ios-macabi and x86_64-apple-ios are not compatible. 1016 if (lhs_triple_os == llvm::Triple::IOS && 1017 rhs_triple_os == llvm::Triple::IOS && 1018 (lhs_triple_env == llvm::Triple::MacABI || 1019 rhs_triple_env == llvm::Triple::MacABI) && 1020 lhs_triple_env != rhs_triple_env) 1021 return false; 1022 1023 if (lhs_triple_os != rhs_triple_os) { 1024 const bool lhs_os_specified = TripleOSWasSpecified(); 1025 const bool rhs_os_specified = rhs.TripleOSWasSpecified(); 1026 // If both OS types are specified and different, fail. 1027 if (lhs_os_specified && rhs_os_specified) 1028 return false; 1029 1030 // If the pair of os+env is both unspecified, match any other os+env combo. 1031 if (!exact_match && ((!lhs_os_specified && !lhs_triple.hasEnvironment()) || 1032 (!rhs_os_specified && !rhs_triple.hasEnvironment()))) 1033 return true; 1034 } 1035 1036 return IsCompatibleEnvironment(lhs_triple_env, rhs_triple_env); 1037 } 1038 1039 void ArchSpec::UpdateCore() { 1040 llvm::StringRef arch_name(m_triple.getArchName()); 1041 const CoreDefinition *core_def = FindCoreDefinition(arch_name); 1042 if (core_def) { 1043 m_core = core_def->core; 1044 // Set the byte order to the default byte order for an architecture. This 1045 // can be modified if needed for cases when cores handle both big and 1046 // little endian 1047 m_byte_order = core_def->default_byte_order; 1048 } else { 1049 Clear(); 1050 } 1051 } 1052 1053 //===----------------------------------------------------------------------===// 1054 // Helper methods. 1055 1056 void ArchSpec::CoreUpdated(bool update_triple) { 1057 const CoreDefinition *core_def = FindCoreDefinition(m_core); 1058 if (core_def) { 1059 if (update_triple) 1060 m_triple = llvm::Triple(core_def->name, "unknown", "unknown"); 1061 m_byte_order = core_def->default_byte_order; 1062 } else { 1063 if (update_triple) 1064 m_triple = llvm::Triple(); 1065 m_byte_order = eByteOrderInvalid; 1066 } 1067 } 1068 1069 //===----------------------------------------------------------------------===// 1070 // Operators. 1071 1072 static bool cores_match(const ArchSpec::Core core1, const ArchSpec::Core core2, 1073 bool try_inverse, bool enforce_exact_match) { 1074 if (core1 == core2) 1075 return true; 1076 1077 switch (core1) { 1078 case ArchSpec::kCore_any: 1079 return true; 1080 1081 case ArchSpec::eCore_arm_generic: 1082 if (enforce_exact_match) 1083 break; 1084 LLVM_FALLTHROUGH; 1085 case ArchSpec::kCore_arm_any: 1086 if (core2 >= ArchSpec::kCore_arm_first && core2 <= ArchSpec::kCore_arm_last) 1087 return true; 1088 if (core2 >= ArchSpec::kCore_thumb_first && 1089 core2 <= ArchSpec::kCore_thumb_last) 1090 return true; 1091 if (core2 == ArchSpec::kCore_arm_any) 1092 return true; 1093 break; 1094 1095 case ArchSpec::kCore_x86_32_any: 1096 if ((core2 >= ArchSpec::kCore_x86_32_first && 1097 core2 <= ArchSpec::kCore_x86_32_last) || 1098 (core2 == ArchSpec::kCore_x86_32_any)) 1099 return true; 1100 break; 1101 1102 case ArchSpec::kCore_x86_64_any: 1103 if ((core2 >= ArchSpec::kCore_x86_64_first && 1104 core2 <= ArchSpec::kCore_x86_64_last) || 1105 (core2 == ArchSpec::kCore_x86_64_any)) 1106 return true; 1107 break; 1108 1109 case ArchSpec::kCore_ppc_any: 1110 if ((core2 >= ArchSpec::kCore_ppc_first && 1111 core2 <= ArchSpec::kCore_ppc_last) || 1112 (core2 == ArchSpec::kCore_ppc_any)) 1113 return true; 1114 break; 1115 1116 case ArchSpec::kCore_ppc64_any: 1117 if ((core2 >= ArchSpec::kCore_ppc64_first && 1118 core2 <= ArchSpec::kCore_ppc64_last) || 1119 (core2 == ArchSpec::kCore_ppc64_any)) 1120 return true; 1121 break; 1122 1123 case ArchSpec::kCore_hexagon_any: 1124 if ((core2 >= ArchSpec::kCore_hexagon_first && 1125 core2 <= ArchSpec::kCore_hexagon_last) || 1126 (core2 == ArchSpec::kCore_hexagon_any)) 1127 return true; 1128 break; 1129 1130 // v. https://en.wikipedia.org/wiki/ARM_Cortex-M#Silicon_customization 1131 // Cortex-M0 - ARMv6-M - armv6m 1132 // Cortex-M3 - ARMv7-M - armv7m 1133 // Cortex-M4 - ARMv7E-M - armv7em 1134 case ArchSpec::eCore_arm_armv7em: 1135 if (!enforce_exact_match) { 1136 if (core2 == ArchSpec::eCore_arm_generic) 1137 return true; 1138 if (core2 == ArchSpec::eCore_arm_armv7m) 1139 return true; 1140 if (core2 == ArchSpec::eCore_arm_armv6m) 1141 return true; 1142 if (core2 == ArchSpec::eCore_arm_armv7) 1143 return true; 1144 try_inverse = true; 1145 } 1146 break; 1147 1148 // v. https://en.wikipedia.org/wiki/ARM_Cortex-M#Silicon_customization 1149 // Cortex-M0 - ARMv6-M - armv6m 1150 // Cortex-M3 - ARMv7-M - armv7m 1151 // Cortex-M4 - ARMv7E-M - armv7em 1152 case ArchSpec::eCore_arm_armv7m: 1153 if (!enforce_exact_match) { 1154 if (core2 == ArchSpec::eCore_arm_generic) 1155 return true; 1156 if (core2 == ArchSpec::eCore_arm_armv6m) 1157 return true; 1158 if (core2 == ArchSpec::eCore_arm_armv7) 1159 return true; 1160 if (core2 == ArchSpec::eCore_arm_armv7em) 1161 return true; 1162 try_inverse = true; 1163 } 1164 break; 1165 1166 // v. https://en.wikipedia.org/wiki/ARM_Cortex-M#Silicon_customization 1167 // Cortex-M0 - ARMv6-M - armv6m 1168 // Cortex-M3 - ARMv7-M - armv7m 1169 // Cortex-M4 - ARMv7E-M - armv7em 1170 case ArchSpec::eCore_arm_armv6m: 1171 if (!enforce_exact_match) { 1172 if (core2 == ArchSpec::eCore_arm_generic) 1173 return true; 1174 if (core2 == ArchSpec::eCore_arm_armv7em) 1175 return true; 1176 if (core2 == ArchSpec::eCore_arm_armv7) 1177 return true; 1178 if (core2 == ArchSpec::eCore_arm_armv6m) 1179 return true; 1180 try_inverse = false; 1181 } 1182 break; 1183 1184 case ArchSpec::eCore_arm_armv7f: 1185 case ArchSpec::eCore_arm_armv7k: 1186 case ArchSpec::eCore_arm_armv7s: 1187 case ArchSpec::eCore_arm_armv7l: 1188 case ArchSpec::eCore_arm_armv8l: 1189 if (!enforce_exact_match) { 1190 if (core2 == ArchSpec::eCore_arm_generic) 1191 return true; 1192 if (core2 == ArchSpec::eCore_arm_armv7) 1193 return true; 1194 try_inverse = false; 1195 } 1196 break; 1197 1198 case ArchSpec::eCore_x86_64_x86_64h: 1199 if (!enforce_exact_match) { 1200 if (core2 == ArchSpec::eCore_x86_64_x86_64) 1201 return true; 1202 try_inverse = false; 1203 } 1204 break; 1205 1206 case ArchSpec::eCore_x86_64_amd64: 1207 if (!enforce_exact_match) { 1208 if (core2 == ArchSpec::eCore_x86_64_x86_64) 1209 return true; 1210 try_inverse = false; 1211 } 1212 break; 1213 1214 case ArchSpec::eCore_arm_armv8: 1215 if (!enforce_exact_match) { 1216 if (core2 == ArchSpec::eCore_arm_arm64) 1217 return true; 1218 if (core2 == ArchSpec::eCore_arm_aarch64) 1219 return true; 1220 if (core2 == ArchSpec::eCore_arm_arm64e) 1221 return true; 1222 try_inverse = false; 1223 } 1224 break; 1225 1226 case ArchSpec::eCore_arm_arm64e: 1227 if (!enforce_exact_match) { 1228 if (core2 == ArchSpec::eCore_arm_arm64) 1229 return true; 1230 if (core2 == ArchSpec::eCore_arm_aarch64) 1231 return true; 1232 if (core2 == ArchSpec::eCore_arm_armv8) 1233 return true; 1234 try_inverse = false; 1235 } 1236 break; 1237 case ArchSpec::eCore_arm_aarch64: 1238 if (!enforce_exact_match) { 1239 if (core2 == ArchSpec::eCore_arm_arm64) 1240 return true; 1241 if (core2 == ArchSpec::eCore_arm_armv8) 1242 return true; 1243 if (core2 == ArchSpec::eCore_arm_arm64e) 1244 return true; 1245 try_inverse = false; 1246 } 1247 break; 1248 1249 case ArchSpec::eCore_arm_arm64: 1250 if (!enforce_exact_match) { 1251 if (core2 == ArchSpec::eCore_arm_aarch64) 1252 return true; 1253 if (core2 == ArchSpec::eCore_arm_armv8) 1254 return true; 1255 if (core2 == ArchSpec::eCore_arm_arm64e) 1256 return true; 1257 try_inverse = false; 1258 } 1259 break; 1260 1261 case ArchSpec::eCore_arm_arm64_32: 1262 if (!enforce_exact_match) { 1263 if (core2 == ArchSpec::eCore_arm_generic) 1264 return true; 1265 try_inverse = false; 1266 } 1267 break; 1268 1269 case ArchSpec::eCore_mips32: 1270 if (!enforce_exact_match) { 1271 if (core2 >= ArchSpec::kCore_mips32_first && 1272 core2 <= ArchSpec::kCore_mips32_last) 1273 return true; 1274 try_inverse = false; 1275 } 1276 break; 1277 1278 case ArchSpec::eCore_mips32el: 1279 if (!enforce_exact_match) { 1280 if (core2 >= ArchSpec::kCore_mips32el_first && 1281 core2 <= ArchSpec::kCore_mips32el_last) 1282 return true; 1283 try_inverse = true; 1284 } 1285 break; 1286 1287 case ArchSpec::eCore_mips64: 1288 if (!enforce_exact_match) { 1289 if (core2 >= ArchSpec::kCore_mips32_first && 1290 core2 <= ArchSpec::kCore_mips32_last) 1291 return true; 1292 if (core2 >= ArchSpec::kCore_mips64_first && 1293 core2 <= ArchSpec::kCore_mips64_last) 1294 return true; 1295 try_inverse = false; 1296 } 1297 break; 1298 1299 case ArchSpec::eCore_mips64el: 1300 if (!enforce_exact_match) { 1301 if (core2 >= ArchSpec::kCore_mips32el_first && 1302 core2 <= ArchSpec::kCore_mips32el_last) 1303 return true; 1304 if (core2 >= ArchSpec::kCore_mips64el_first && 1305 core2 <= ArchSpec::kCore_mips64el_last) 1306 return true; 1307 try_inverse = false; 1308 } 1309 break; 1310 1311 case ArchSpec::eCore_mips64r2: 1312 case ArchSpec::eCore_mips64r3: 1313 case ArchSpec::eCore_mips64r5: 1314 if (!enforce_exact_match) { 1315 if (core2 >= ArchSpec::kCore_mips32_first && core2 <= (core1 - 10)) 1316 return true; 1317 if (core2 >= ArchSpec::kCore_mips64_first && core2 <= (core1 - 1)) 1318 return true; 1319 try_inverse = false; 1320 } 1321 break; 1322 1323 case ArchSpec::eCore_mips64r2el: 1324 case ArchSpec::eCore_mips64r3el: 1325 case ArchSpec::eCore_mips64r5el: 1326 if (!enforce_exact_match) { 1327 if (core2 >= ArchSpec::kCore_mips32el_first && core2 <= (core1 - 10)) 1328 return true; 1329 if (core2 >= ArchSpec::kCore_mips64el_first && core2 <= (core1 - 1)) 1330 return true; 1331 try_inverse = false; 1332 } 1333 break; 1334 1335 case ArchSpec::eCore_mips32r2: 1336 case ArchSpec::eCore_mips32r3: 1337 case ArchSpec::eCore_mips32r5: 1338 if (!enforce_exact_match) { 1339 if (core2 >= ArchSpec::kCore_mips32_first && core2 <= core1) 1340 return true; 1341 } 1342 break; 1343 1344 case ArchSpec::eCore_mips32r2el: 1345 case ArchSpec::eCore_mips32r3el: 1346 case ArchSpec::eCore_mips32r5el: 1347 if (!enforce_exact_match) { 1348 if (core2 >= ArchSpec::kCore_mips32el_first && core2 <= core1) 1349 return true; 1350 } 1351 break; 1352 1353 case ArchSpec::eCore_mips32r6: 1354 if (!enforce_exact_match) { 1355 if (core2 == ArchSpec::eCore_mips32 || core2 == ArchSpec::eCore_mips32r6) 1356 return true; 1357 } 1358 break; 1359 1360 case ArchSpec::eCore_mips32r6el: 1361 if (!enforce_exact_match) { 1362 if (core2 == ArchSpec::eCore_mips32el || 1363 core2 == ArchSpec::eCore_mips32r6el) 1364 return true; 1365 } 1366 break; 1367 1368 case ArchSpec::eCore_mips64r6: 1369 if (!enforce_exact_match) { 1370 if (core2 == ArchSpec::eCore_mips32 || core2 == ArchSpec::eCore_mips32r6) 1371 return true; 1372 if (core2 == ArchSpec::eCore_mips64 || core2 == ArchSpec::eCore_mips64r6) 1373 return true; 1374 } 1375 break; 1376 1377 case ArchSpec::eCore_mips64r6el: 1378 if (!enforce_exact_match) { 1379 if (core2 == ArchSpec::eCore_mips32el || 1380 core2 == ArchSpec::eCore_mips32r6el) 1381 return true; 1382 if (core2 == ArchSpec::eCore_mips64el || 1383 core2 == ArchSpec::eCore_mips64r6el) 1384 return true; 1385 } 1386 break; 1387 1388 default: 1389 break; 1390 } 1391 if (try_inverse) 1392 return cores_match(core2, core1, false, enforce_exact_match); 1393 return false; 1394 } 1395 1396 bool lldb_private::operator<(const ArchSpec &lhs, const ArchSpec &rhs) { 1397 const ArchSpec::Core lhs_core = lhs.GetCore(); 1398 const ArchSpec::Core rhs_core = rhs.GetCore(); 1399 return lhs_core < rhs_core; 1400 } 1401 1402 1403 bool lldb_private::operator==(const ArchSpec &lhs, const ArchSpec &rhs) { 1404 return lhs.GetCore() == rhs.GetCore(); 1405 } 1406 1407 bool ArchSpec::IsFullySpecifiedTriple() const { 1408 const auto &user_specified_triple = GetTriple(); 1409 1410 bool user_triple_fully_specified = false; 1411 1412 if ((user_specified_triple.getOS() != llvm::Triple::UnknownOS) || 1413 TripleOSWasSpecified()) { 1414 if ((user_specified_triple.getVendor() != llvm::Triple::UnknownVendor) || 1415 TripleVendorWasSpecified()) { 1416 const unsigned unspecified = 0; 1417 if (!user_specified_triple.isOSDarwin() || 1418 user_specified_triple.getOSMajorVersion() != unspecified) { 1419 user_triple_fully_specified = true; 1420 } 1421 } 1422 } 1423 1424 return user_triple_fully_specified; 1425 } 1426 1427 void ArchSpec::PiecewiseTripleCompare( 1428 const ArchSpec &other, bool &arch_different, bool &vendor_different, 1429 bool &os_different, bool &os_version_different, bool &env_different) const { 1430 const llvm::Triple &me(GetTriple()); 1431 const llvm::Triple &them(other.GetTriple()); 1432 1433 arch_different = (me.getArch() != them.getArch()); 1434 1435 vendor_different = (me.getVendor() != them.getVendor()); 1436 1437 os_different = (me.getOS() != them.getOS()); 1438 1439 os_version_different = (me.getOSMajorVersion() != them.getOSMajorVersion()); 1440 1441 env_different = (me.getEnvironment() != them.getEnvironment()); 1442 } 1443 1444 bool ArchSpec::IsAlwaysThumbInstructions() const { 1445 std::string Status; 1446 if (GetTriple().getArch() == llvm::Triple::arm || 1447 GetTriple().getArch() == llvm::Triple::thumb) { 1448 // v. https://en.wikipedia.org/wiki/ARM_Cortex-M 1449 // 1450 // Cortex-M0 through Cortex-M7 are ARM processor cores which can only 1451 // execute thumb instructions. We map the cores to arch names like this: 1452 // 1453 // Cortex-M0, Cortex-M0+, Cortex-M1: armv6m Cortex-M3: armv7m Cortex-M4, 1454 // Cortex-M7: armv7em 1455 1456 if (GetCore() == ArchSpec::Core::eCore_arm_armv7m || 1457 GetCore() == ArchSpec::Core::eCore_arm_armv7em || 1458 GetCore() == ArchSpec::Core::eCore_arm_armv6m || 1459 GetCore() == ArchSpec::Core::eCore_thumbv7m || 1460 GetCore() == ArchSpec::Core::eCore_thumbv7em || 1461 GetCore() == ArchSpec::Core::eCore_thumbv6m) { 1462 return true; 1463 } 1464 // Windows on ARM is always thumb. 1465 if (GetTriple().isOSWindows()) 1466 return true; 1467 } 1468 return false; 1469 } 1470 1471 void ArchSpec::DumpTriple(llvm::raw_ostream &s) const { 1472 const llvm::Triple &triple = GetTriple(); 1473 llvm::StringRef arch_str = triple.getArchName(); 1474 llvm::StringRef vendor_str = triple.getVendorName(); 1475 llvm::StringRef os_str = triple.getOSName(); 1476 llvm::StringRef environ_str = triple.getEnvironmentName(); 1477 1478 s << llvm::formatv("{0}-{1}-{2}", arch_str.empty() ? "*" : arch_str, 1479 vendor_str.empty() ? "*" : vendor_str, 1480 os_str.empty() ? "*" : os_str); 1481 1482 if (!environ_str.empty()) 1483 s << "-" << environ_str; 1484 } 1485 1486 void llvm::yaml::ScalarTraits<ArchSpec>::output(const ArchSpec &Val, void *, 1487 raw_ostream &Out) { 1488 Val.DumpTriple(Out); 1489 } 1490 1491 llvm::StringRef 1492 llvm::yaml::ScalarTraits<ArchSpec>::input(llvm::StringRef Scalar, void *, 1493 ArchSpec &Val) { 1494 Val = ArchSpec(Scalar); 1495 return {}; 1496 } 1497