1 //===-- ArchSpec.cpp ------------------------------------------------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 9 #include "lldb/Utility/ArchSpec.h" 10 11 #include "lldb/Utility/Log.h" 12 #include "lldb/Utility/StringList.h" 13 #include "lldb/lldb-defines.h" 14 #include "llvm/ADT/STLExtras.h" 15 #include "llvm/BinaryFormat/COFF.h" 16 #include "llvm/BinaryFormat/ELF.h" 17 #include "llvm/BinaryFormat/MachO.h" 18 #include "llvm/Support/Compiler.h" 19 20 using namespace lldb; 21 using namespace lldb_private; 22 23 static bool cores_match(const ArchSpec::Core core1, const ArchSpec::Core core2, 24 bool try_inverse, bool enforce_exact_match); 25 26 namespace lldb_private { 27 28 struct CoreDefinition { 29 ByteOrder default_byte_order; 30 uint32_t addr_byte_size; 31 uint32_t min_opcode_byte_size; 32 uint32_t max_opcode_byte_size; 33 llvm::Triple::ArchType machine; 34 ArchSpec::Core core; 35 const char *const name; 36 }; 37 38 } // namespace lldb_private 39 40 // This core information can be looked using the ArchSpec::Core as the index 41 static const CoreDefinition g_core_definitions[] = { 42 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_generic, 43 "arm"}, 44 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv4, 45 "armv4"}, 46 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv4t, 47 "armv4t"}, 48 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv5, 49 "armv5"}, 50 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv5e, 51 "armv5e"}, 52 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv5t, 53 "armv5t"}, 54 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv6, 55 "armv6"}, 56 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv6m, 57 "armv6m"}, 58 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7, 59 "armv7"}, 60 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7l, 61 "armv7l"}, 62 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7f, 63 "armv7f"}, 64 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7s, 65 "armv7s"}, 66 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7k, 67 "armv7k"}, 68 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7m, 69 "armv7m"}, 70 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7em, 71 "armv7em"}, 72 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_xscale, 73 "xscale"}, 74 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumb, 75 "thumb"}, 76 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv4t, 77 "thumbv4t"}, 78 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv5, 79 "thumbv5"}, 80 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv5e, 81 "thumbv5e"}, 82 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv6, 83 "thumbv6"}, 84 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv6m, 85 "thumbv6m"}, 86 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv7, 87 "thumbv7"}, 88 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv7f, 89 "thumbv7f"}, 90 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv7s, 91 "thumbv7s"}, 92 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv7k, 93 "thumbv7k"}, 94 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv7m, 95 "thumbv7m"}, 96 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv7em, 97 "thumbv7em"}, 98 {eByteOrderLittle, 8, 4, 4, llvm::Triple::aarch64, 99 ArchSpec::eCore_arm_arm64, "arm64"}, 100 {eByteOrderLittle, 8, 4, 4, llvm::Triple::aarch64, 101 ArchSpec::eCore_arm_armv8, "armv8"}, 102 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, 103 ArchSpec::eCore_arm_armv8l, "armv8l"}, 104 {eByteOrderLittle, 4, 4, 4, llvm::Triple::aarch64_32, 105 ArchSpec::eCore_arm_arm64_32, "arm64_32"}, 106 {eByteOrderLittle, 8, 4, 4, llvm::Triple::aarch64, 107 ArchSpec::eCore_arm_aarch64, "aarch64"}, 108 109 // mips32, mips32r2, mips32r3, mips32r5, mips32r6 110 {eByteOrderBig, 4, 2, 4, llvm::Triple::mips, ArchSpec::eCore_mips32, 111 "mips"}, 112 {eByteOrderBig, 4, 2, 4, llvm::Triple::mips, ArchSpec::eCore_mips32r2, 113 "mipsr2"}, 114 {eByteOrderBig, 4, 2, 4, llvm::Triple::mips, ArchSpec::eCore_mips32r3, 115 "mipsr3"}, 116 {eByteOrderBig, 4, 2, 4, llvm::Triple::mips, ArchSpec::eCore_mips32r5, 117 "mipsr5"}, 118 {eByteOrderBig, 4, 2, 4, llvm::Triple::mips, ArchSpec::eCore_mips32r6, 119 "mipsr6"}, 120 {eByteOrderLittle, 4, 2, 4, llvm::Triple::mipsel, ArchSpec::eCore_mips32el, 121 "mipsel"}, 122 {eByteOrderLittle, 4, 2, 4, llvm::Triple::mipsel, 123 ArchSpec::eCore_mips32r2el, "mipsr2el"}, 124 {eByteOrderLittle, 4, 2, 4, llvm::Triple::mipsel, 125 ArchSpec::eCore_mips32r3el, "mipsr3el"}, 126 {eByteOrderLittle, 4, 2, 4, llvm::Triple::mipsel, 127 ArchSpec::eCore_mips32r5el, "mipsr5el"}, 128 {eByteOrderLittle, 4, 2, 4, llvm::Triple::mipsel, 129 ArchSpec::eCore_mips32r6el, "mipsr6el"}, 130 131 // mips64, mips64r2, mips64r3, mips64r5, mips64r6 132 {eByteOrderBig, 8, 2, 4, llvm::Triple::mips64, ArchSpec::eCore_mips64, 133 "mips64"}, 134 {eByteOrderBig, 8, 2, 4, llvm::Triple::mips64, ArchSpec::eCore_mips64r2, 135 "mips64r2"}, 136 {eByteOrderBig, 8, 2, 4, llvm::Triple::mips64, ArchSpec::eCore_mips64r3, 137 "mips64r3"}, 138 {eByteOrderBig, 8, 2, 4, llvm::Triple::mips64, ArchSpec::eCore_mips64r5, 139 "mips64r5"}, 140 {eByteOrderBig, 8, 2, 4, llvm::Triple::mips64, ArchSpec::eCore_mips64r6, 141 "mips64r6"}, 142 {eByteOrderLittle, 8, 2, 4, llvm::Triple::mips64el, 143 ArchSpec::eCore_mips64el, "mips64el"}, 144 {eByteOrderLittle, 8, 2, 4, llvm::Triple::mips64el, 145 ArchSpec::eCore_mips64r2el, "mips64r2el"}, 146 {eByteOrderLittle, 8, 2, 4, llvm::Triple::mips64el, 147 ArchSpec::eCore_mips64r3el, "mips64r3el"}, 148 {eByteOrderLittle, 8, 2, 4, llvm::Triple::mips64el, 149 ArchSpec::eCore_mips64r5el, "mips64r5el"}, 150 {eByteOrderLittle, 8, 2, 4, llvm::Triple::mips64el, 151 ArchSpec::eCore_mips64r6el, "mips64r6el"}, 152 153 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_generic, 154 "powerpc"}, 155 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc601, 156 "ppc601"}, 157 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc602, 158 "ppc602"}, 159 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc603, 160 "ppc603"}, 161 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc603e, 162 "ppc603e"}, 163 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc603ev, 164 "ppc603ev"}, 165 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc604, 166 "ppc604"}, 167 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc604e, 168 "ppc604e"}, 169 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc620, 170 "ppc620"}, 171 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc750, 172 "ppc750"}, 173 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc7400, 174 "ppc7400"}, 175 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc7450, 176 "ppc7450"}, 177 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc970, 178 "ppc970"}, 179 180 {eByteOrderLittle, 8, 4, 4, llvm::Triple::ppc64le, 181 ArchSpec::eCore_ppc64le_generic, "powerpc64le"}, 182 {eByteOrderBig, 8, 4, 4, llvm::Triple::ppc64, ArchSpec::eCore_ppc64_generic, 183 "powerpc64"}, 184 {eByteOrderBig, 8, 4, 4, llvm::Triple::ppc64, 185 ArchSpec::eCore_ppc64_ppc970_64, "ppc970-64"}, 186 187 {eByteOrderBig, 8, 2, 6, llvm::Triple::systemz, 188 ArchSpec::eCore_s390x_generic, "s390x"}, 189 190 {eByteOrderLittle, 4, 4, 4, llvm::Triple::sparc, 191 ArchSpec::eCore_sparc_generic, "sparc"}, 192 {eByteOrderLittle, 8, 4, 4, llvm::Triple::sparcv9, 193 ArchSpec::eCore_sparc9_generic, "sparcv9"}, 194 195 {eByteOrderLittle, 4, 1, 15, llvm::Triple::x86, ArchSpec::eCore_x86_32_i386, 196 "i386"}, 197 {eByteOrderLittle, 4, 1, 15, llvm::Triple::x86, ArchSpec::eCore_x86_32_i486, 198 "i486"}, 199 {eByteOrderLittle, 4, 1, 15, llvm::Triple::x86, 200 ArchSpec::eCore_x86_32_i486sx, "i486sx"}, 201 {eByteOrderLittle, 4, 1, 15, llvm::Triple::x86, ArchSpec::eCore_x86_32_i686, 202 "i686"}, 203 204 {eByteOrderLittle, 8, 1, 15, llvm::Triple::x86_64, 205 ArchSpec::eCore_x86_64_x86_64, "x86_64"}, 206 {eByteOrderLittle, 8, 1, 15, llvm::Triple::x86_64, 207 ArchSpec::eCore_x86_64_x86_64h, "x86_64h"}, 208 {eByteOrderLittle, 8, 1, 15, llvm::Triple::x86_64, 209 ArchSpec::eCore_x86_64_amd64, "amd64"}, 210 {eByteOrderLittle, 4, 4, 4, llvm::Triple::hexagon, 211 ArchSpec::eCore_hexagon_generic, "hexagon"}, 212 {eByteOrderLittle, 4, 4, 4, llvm::Triple::hexagon, 213 ArchSpec::eCore_hexagon_hexagonv4, "hexagonv4"}, 214 {eByteOrderLittle, 4, 4, 4, llvm::Triple::hexagon, 215 ArchSpec::eCore_hexagon_hexagonv5, "hexagonv5"}, 216 217 {eByteOrderLittle, 4, 4, 4, llvm::Triple::UnknownArch, 218 ArchSpec::eCore_uknownMach32, "unknown-mach-32"}, 219 {eByteOrderLittle, 8, 4, 4, llvm::Triple::UnknownArch, 220 ArchSpec::eCore_uknownMach64, "unknown-mach-64"}, 221 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arc, ArchSpec::eCore_arc, "arc"}, 222 223 {eByteOrderLittle, 2, 2, 4, llvm::Triple::avr, ArchSpec::eCore_avr, "avr"}, 224 225 {eByteOrderLittle, 4, 1, 4, llvm::Triple::wasm32, ArchSpec::eCore_wasm32, 226 "wasm32"}, 227 }; 228 229 // Ensure that we have an entry in the g_core_definitions for each core. If you 230 // comment out an entry above, you will need to comment out the corresponding 231 // ArchSpec::Core enumeration. 232 static_assert(sizeof(g_core_definitions) / sizeof(CoreDefinition) == 233 ArchSpec::kNumCores, 234 "make sure we have one core definition for each core"); 235 236 struct ArchDefinitionEntry { 237 ArchSpec::Core core; 238 uint32_t cpu; 239 uint32_t sub; 240 uint32_t cpu_mask; 241 uint32_t sub_mask; 242 }; 243 244 struct ArchDefinition { 245 ArchitectureType type; 246 size_t num_entries; 247 const ArchDefinitionEntry *entries; 248 const char *name; 249 }; 250 251 void ArchSpec::ListSupportedArchNames(StringList &list) { 252 for (uint32_t i = 0; i < llvm::array_lengthof(g_core_definitions); ++i) 253 list.AppendString(g_core_definitions[i].name); 254 } 255 256 void ArchSpec::AutoComplete(CompletionRequest &request) { 257 for (uint32_t i = 0; i < llvm::array_lengthof(g_core_definitions); ++i) 258 request.TryCompleteCurrentArg(g_core_definitions[i].name); 259 } 260 261 #define CPU_ANY (UINT32_MAX) 262 263 //===----------------------------------------------------------------------===// 264 // A table that gets searched linearly for matches. This table is used to 265 // convert cpu type and subtypes to architecture names, and to convert 266 // architecture names to cpu types and subtypes. The ordering is important and 267 // allows the precedence to be set when the table is built. 268 #define SUBTYPE_MASK 0x00FFFFFFu 269 270 static const ArchDefinitionEntry g_macho_arch_entries[] = { 271 {ArchSpec::eCore_arm_generic, llvm::MachO::CPU_TYPE_ARM, CPU_ANY, 272 UINT32_MAX, UINT32_MAX}, 273 {ArchSpec::eCore_arm_generic, llvm::MachO::CPU_TYPE_ARM, 0, UINT32_MAX, 274 SUBTYPE_MASK}, 275 {ArchSpec::eCore_arm_armv4, llvm::MachO::CPU_TYPE_ARM, 5, UINT32_MAX, 276 SUBTYPE_MASK}, 277 {ArchSpec::eCore_arm_armv4t, llvm::MachO::CPU_TYPE_ARM, 5, UINT32_MAX, 278 SUBTYPE_MASK}, 279 {ArchSpec::eCore_arm_armv6, llvm::MachO::CPU_TYPE_ARM, 6, UINT32_MAX, 280 SUBTYPE_MASK}, 281 {ArchSpec::eCore_arm_armv6m, llvm::MachO::CPU_TYPE_ARM, 14, UINT32_MAX, 282 SUBTYPE_MASK}, 283 {ArchSpec::eCore_arm_armv5, llvm::MachO::CPU_TYPE_ARM, 7, UINT32_MAX, 284 SUBTYPE_MASK}, 285 {ArchSpec::eCore_arm_armv5e, llvm::MachO::CPU_TYPE_ARM, 7, UINT32_MAX, 286 SUBTYPE_MASK}, 287 {ArchSpec::eCore_arm_armv5t, llvm::MachO::CPU_TYPE_ARM, 7, UINT32_MAX, 288 SUBTYPE_MASK}, 289 {ArchSpec::eCore_arm_xscale, llvm::MachO::CPU_TYPE_ARM, 8, UINT32_MAX, 290 SUBTYPE_MASK}, 291 {ArchSpec::eCore_arm_armv7, llvm::MachO::CPU_TYPE_ARM, 9, UINT32_MAX, 292 SUBTYPE_MASK}, 293 {ArchSpec::eCore_arm_armv7f, llvm::MachO::CPU_TYPE_ARM, 10, UINT32_MAX, 294 SUBTYPE_MASK}, 295 {ArchSpec::eCore_arm_armv7s, llvm::MachO::CPU_TYPE_ARM, 11, UINT32_MAX, 296 SUBTYPE_MASK}, 297 {ArchSpec::eCore_arm_armv7k, llvm::MachO::CPU_TYPE_ARM, 12, UINT32_MAX, 298 SUBTYPE_MASK}, 299 {ArchSpec::eCore_arm_armv7m, llvm::MachO::CPU_TYPE_ARM, 15, UINT32_MAX, 300 SUBTYPE_MASK}, 301 {ArchSpec::eCore_arm_armv7em, llvm::MachO::CPU_TYPE_ARM, 16, UINT32_MAX, 302 SUBTYPE_MASK}, 303 {ArchSpec::eCore_arm_arm64, llvm::MachO::CPU_TYPE_ARM64, 1, UINT32_MAX, 304 SUBTYPE_MASK}, 305 {ArchSpec::eCore_arm_arm64, llvm::MachO::CPU_TYPE_ARM64, 0, UINT32_MAX, 306 SUBTYPE_MASK}, 307 {ArchSpec::eCore_arm_arm64, llvm::MachO::CPU_TYPE_ARM64, 13, UINT32_MAX, 308 SUBTYPE_MASK}, 309 {ArchSpec::eCore_arm_arm64_32, llvm::MachO::CPU_TYPE_ARM64_32, 0, 310 UINT32_MAX, SUBTYPE_MASK}, 311 {ArchSpec::eCore_arm_arm64_32, llvm::MachO::CPU_TYPE_ARM64_32, 1, 312 UINT32_MAX, SUBTYPE_MASK}, 313 {ArchSpec::eCore_arm_arm64, llvm::MachO::CPU_TYPE_ARM64, CPU_ANY, 314 UINT32_MAX, SUBTYPE_MASK}, 315 {ArchSpec::eCore_thumb, llvm::MachO::CPU_TYPE_ARM, 0, UINT32_MAX, 316 SUBTYPE_MASK}, 317 {ArchSpec::eCore_thumbv4t, llvm::MachO::CPU_TYPE_ARM, 5, UINT32_MAX, 318 SUBTYPE_MASK}, 319 {ArchSpec::eCore_thumbv5, llvm::MachO::CPU_TYPE_ARM, 7, UINT32_MAX, 320 SUBTYPE_MASK}, 321 {ArchSpec::eCore_thumbv5e, llvm::MachO::CPU_TYPE_ARM, 7, UINT32_MAX, 322 SUBTYPE_MASK}, 323 {ArchSpec::eCore_thumbv6, llvm::MachO::CPU_TYPE_ARM, 6, UINT32_MAX, 324 SUBTYPE_MASK}, 325 {ArchSpec::eCore_thumbv6m, llvm::MachO::CPU_TYPE_ARM, 14, UINT32_MAX, 326 SUBTYPE_MASK}, 327 {ArchSpec::eCore_thumbv7, llvm::MachO::CPU_TYPE_ARM, 9, UINT32_MAX, 328 SUBTYPE_MASK}, 329 {ArchSpec::eCore_thumbv7f, llvm::MachO::CPU_TYPE_ARM, 10, UINT32_MAX, 330 SUBTYPE_MASK}, 331 {ArchSpec::eCore_thumbv7s, llvm::MachO::CPU_TYPE_ARM, 11, UINT32_MAX, 332 SUBTYPE_MASK}, 333 {ArchSpec::eCore_thumbv7k, llvm::MachO::CPU_TYPE_ARM, 12, UINT32_MAX, 334 SUBTYPE_MASK}, 335 {ArchSpec::eCore_thumbv7m, llvm::MachO::CPU_TYPE_ARM, 15, UINT32_MAX, 336 SUBTYPE_MASK}, 337 {ArchSpec::eCore_thumbv7em, llvm::MachO::CPU_TYPE_ARM, 16, UINT32_MAX, 338 SUBTYPE_MASK}, 339 {ArchSpec::eCore_ppc_generic, llvm::MachO::CPU_TYPE_POWERPC, CPU_ANY, 340 UINT32_MAX, UINT32_MAX}, 341 {ArchSpec::eCore_ppc_generic, llvm::MachO::CPU_TYPE_POWERPC, 0, UINT32_MAX, 342 SUBTYPE_MASK}, 343 {ArchSpec::eCore_ppc_ppc601, llvm::MachO::CPU_TYPE_POWERPC, 1, UINT32_MAX, 344 SUBTYPE_MASK}, 345 {ArchSpec::eCore_ppc_ppc602, llvm::MachO::CPU_TYPE_POWERPC, 2, UINT32_MAX, 346 SUBTYPE_MASK}, 347 {ArchSpec::eCore_ppc_ppc603, llvm::MachO::CPU_TYPE_POWERPC, 3, UINT32_MAX, 348 SUBTYPE_MASK}, 349 {ArchSpec::eCore_ppc_ppc603e, llvm::MachO::CPU_TYPE_POWERPC, 4, UINT32_MAX, 350 SUBTYPE_MASK}, 351 {ArchSpec::eCore_ppc_ppc603ev, llvm::MachO::CPU_TYPE_POWERPC, 5, UINT32_MAX, 352 SUBTYPE_MASK}, 353 {ArchSpec::eCore_ppc_ppc604, llvm::MachO::CPU_TYPE_POWERPC, 6, UINT32_MAX, 354 SUBTYPE_MASK}, 355 {ArchSpec::eCore_ppc_ppc604e, llvm::MachO::CPU_TYPE_POWERPC, 7, UINT32_MAX, 356 SUBTYPE_MASK}, 357 {ArchSpec::eCore_ppc_ppc620, llvm::MachO::CPU_TYPE_POWERPC, 8, UINT32_MAX, 358 SUBTYPE_MASK}, 359 {ArchSpec::eCore_ppc_ppc750, llvm::MachO::CPU_TYPE_POWERPC, 9, UINT32_MAX, 360 SUBTYPE_MASK}, 361 {ArchSpec::eCore_ppc_ppc7400, llvm::MachO::CPU_TYPE_POWERPC, 10, UINT32_MAX, 362 SUBTYPE_MASK}, 363 {ArchSpec::eCore_ppc_ppc7450, llvm::MachO::CPU_TYPE_POWERPC, 11, UINT32_MAX, 364 SUBTYPE_MASK}, 365 {ArchSpec::eCore_ppc_ppc970, llvm::MachO::CPU_TYPE_POWERPC, 100, UINT32_MAX, 366 SUBTYPE_MASK}, 367 {ArchSpec::eCore_ppc64_generic, llvm::MachO::CPU_TYPE_POWERPC64, 0, 368 UINT32_MAX, SUBTYPE_MASK}, 369 {ArchSpec::eCore_ppc64le_generic, llvm::MachO::CPU_TYPE_POWERPC64, CPU_ANY, 370 UINT32_MAX, SUBTYPE_MASK}, 371 {ArchSpec::eCore_ppc64_ppc970_64, llvm::MachO::CPU_TYPE_POWERPC64, 100, 372 UINT32_MAX, SUBTYPE_MASK}, 373 {ArchSpec::eCore_x86_32_i386, llvm::MachO::CPU_TYPE_I386, 3, UINT32_MAX, 374 SUBTYPE_MASK}, 375 {ArchSpec::eCore_x86_32_i486, llvm::MachO::CPU_TYPE_I386, 4, UINT32_MAX, 376 SUBTYPE_MASK}, 377 {ArchSpec::eCore_x86_32_i486sx, llvm::MachO::CPU_TYPE_I386, 0x84, 378 UINT32_MAX, SUBTYPE_MASK}, 379 {ArchSpec::eCore_x86_32_i386, llvm::MachO::CPU_TYPE_I386, CPU_ANY, 380 UINT32_MAX, UINT32_MAX}, 381 {ArchSpec::eCore_x86_64_x86_64, llvm::MachO::CPU_TYPE_X86_64, 3, UINT32_MAX, 382 SUBTYPE_MASK}, 383 {ArchSpec::eCore_x86_64_x86_64, llvm::MachO::CPU_TYPE_X86_64, 4, UINT32_MAX, 384 SUBTYPE_MASK}, 385 {ArchSpec::eCore_x86_64_x86_64h, llvm::MachO::CPU_TYPE_X86_64, 8, 386 UINT32_MAX, SUBTYPE_MASK}, 387 {ArchSpec::eCore_x86_64_x86_64, llvm::MachO::CPU_TYPE_X86_64, CPU_ANY, 388 UINT32_MAX, UINT32_MAX}, 389 // Catch any unknown mach architectures so we can always use the object and 390 // symbol mach-o files 391 {ArchSpec::eCore_uknownMach32, 0, 0, 0xFF000000u, 0x00000000u}, 392 {ArchSpec::eCore_uknownMach64, llvm::MachO::CPU_ARCH_ABI64, 0, 0xFF000000u, 393 0x00000000u}}; 394 395 static const ArchDefinition g_macho_arch_def = { 396 eArchTypeMachO, llvm::array_lengthof(g_macho_arch_entries), 397 g_macho_arch_entries, "mach-o"}; 398 399 //===----------------------------------------------------------------------===// 400 // A table that gets searched linearly for matches. This table is used to 401 // convert cpu type and subtypes to architecture names, and to convert 402 // architecture names to cpu types and subtypes. The ordering is important and 403 // allows the precedence to be set when the table is built. 404 static const ArchDefinitionEntry g_elf_arch_entries[] = { 405 {ArchSpec::eCore_sparc_generic, llvm::ELF::EM_SPARC, LLDB_INVALID_CPUTYPE, 406 0xFFFFFFFFu, 0xFFFFFFFFu}, // Sparc 407 {ArchSpec::eCore_x86_32_i386, llvm::ELF::EM_386, LLDB_INVALID_CPUTYPE, 408 0xFFFFFFFFu, 0xFFFFFFFFu}, // Intel 80386 409 {ArchSpec::eCore_x86_32_i486, llvm::ELF::EM_IAMCU, LLDB_INVALID_CPUTYPE, 410 0xFFFFFFFFu, 0xFFFFFFFFu}, // Intel MCU // FIXME: is this correct? 411 {ArchSpec::eCore_ppc_generic, llvm::ELF::EM_PPC, LLDB_INVALID_CPUTYPE, 412 0xFFFFFFFFu, 0xFFFFFFFFu}, // PowerPC 413 {ArchSpec::eCore_ppc64le_generic, llvm::ELF::EM_PPC64, LLDB_INVALID_CPUTYPE, 414 0xFFFFFFFFu, 0xFFFFFFFFu}, // PowerPC64le 415 {ArchSpec::eCore_ppc64_generic, llvm::ELF::EM_PPC64, LLDB_INVALID_CPUTYPE, 416 0xFFFFFFFFu, 0xFFFFFFFFu}, // PowerPC64 417 {ArchSpec::eCore_arm_generic, llvm::ELF::EM_ARM, LLDB_INVALID_CPUTYPE, 418 0xFFFFFFFFu, 0xFFFFFFFFu}, // ARM 419 {ArchSpec::eCore_arm_aarch64, llvm::ELF::EM_AARCH64, LLDB_INVALID_CPUTYPE, 420 0xFFFFFFFFu, 0xFFFFFFFFu}, // ARM64 421 {ArchSpec::eCore_s390x_generic, llvm::ELF::EM_S390, LLDB_INVALID_CPUTYPE, 422 0xFFFFFFFFu, 0xFFFFFFFFu}, // SystemZ 423 {ArchSpec::eCore_sparc9_generic, llvm::ELF::EM_SPARCV9, 424 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // SPARC V9 425 {ArchSpec::eCore_x86_64_x86_64, llvm::ELF::EM_X86_64, LLDB_INVALID_CPUTYPE, 426 0xFFFFFFFFu, 0xFFFFFFFFu}, // AMD64 427 {ArchSpec::eCore_mips32, llvm::ELF::EM_MIPS, ArchSpec::eMIPSSubType_mips32, 428 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32 429 {ArchSpec::eCore_mips32r2, llvm::ELF::EM_MIPS, 430 ArchSpec::eMIPSSubType_mips32r2, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32r2 431 {ArchSpec::eCore_mips32r6, llvm::ELF::EM_MIPS, 432 ArchSpec::eMIPSSubType_mips32r6, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32r6 433 {ArchSpec::eCore_mips32el, llvm::ELF::EM_MIPS, 434 ArchSpec::eMIPSSubType_mips32el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32el 435 {ArchSpec::eCore_mips32r2el, llvm::ELF::EM_MIPS, 436 ArchSpec::eMIPSSubType_mips32r2el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32r2el 437 {ArchSpec::eCore_mips32r6el, llvm::ELF::EM_MIPS, 438 ArchSpec::eMIPSSubType_mips32r6el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32r6el 439 {ArchSpec::eCore_mips64, llvm::ELF::EM_MIPS, ArchSpec::eMIPSSubType_mips64, 440 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64 441 {ArchSpec::eCore_mips64r2, llvm::ELF::EM_MIPS, 442 ArchSpec::eMIPSSubType_mips64r2, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64r2 443 {ArchSpec::eCore_mips64r6, llvm::ELF::EM_MIPS, 444 ArchSpec::eMIPSSubType_mips64r6, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64r6 445 {ArchSpec::eCore_mips64el, llvm::ELF::EM_MIPS, 446 ArchSpec::eMIPSSubType_mips64el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64el 447 {ArchSpec::eCore_mips64r2el, llvm::ELF::EM_MIPS, 448 ArchSpec::eMIPSSubType_mips64r2el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64r2el 449 {ArchSpec::eCore_mips64r6el, llvm::ELF::EM_MIPS, 450 ArchSpec::eMIPSSubType_mips64r6el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64r6el 451 {ArchSpec::eCore_hexagon_generic, llvm::ELF::EM_HEXAGON, 452 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // HEXAGON 453 {ArchSpec::eCore_arc, llvm::ELF::EM_ARC_COMPACT2, LLDB_INVALID_CPUTYPE, 454 0xFFFFFFFFu, 0xFFFFFFFFu}, // ARC 455 {ArchSpec::eCore_avr, llvm::ELF::EM_AVR, LLDB_INVALID_CPUTYPE, 456 0xFFFFFFFFu, 0xFFFFFFFFu}, // AVR 457 }; 458 459 static const ArchDefinition g_elf_arch_def = { 460 eArchTypeELF, 461 llvm::array_lengthof(g_elf_arch_entries), 462 g_elf_arch_entries, 463 "elf", 464 }; 465 466 static const ArchDefinitionEntry g_coff_arch_entries[] = { 467 {ArchSpec::eCore_x86_32_i386, llvm::COFF::IMAGE_FILE_MACHINE_I386, 468 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // Intel 80x86 469 {ArchSpec::eCore_ppc_generic, llvm::COFF::IMAGE_FILE_MACHINE_POWERPC, 470 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // PowerPC 471 {ArchSpec::eCore_ppc_generic, llvm::COFF::IMAGE_FILE_MACHINE_POWERPCFP, 472 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // PowerPC (with FPU) 473 {ArchSpec::eCore_arm_generic, llvm::COFF::IMAGE_FILE_MACHINE_ARM, 474 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // ARM 475 {ArchSpec::eCore_arm_armv7, llvm::COFF::IMAGE_FILE_MACHINE_ARMNT, 476 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // ARMv7 477 {ArchSpec::eCore_thumb, llvm::COFF::IMAGE_FILE_MACHINE_THUMB, 478 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // ARMv7 479 {ArchSpec::eCore_x86_64_x86_64, llvm::COFF::IMAGE_FILE_MACHINE_AMD64, 480 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // AMD64 481 {ArchSpec::eCore_arm_arm64, llvm::COFF::IMAGE_FILE_MACHINE_ARM64, 482 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu} // ARM64 483 }; 484 485 static const ArchDefinition g_coff_arch_def = { 486 eArchTypeCOFF, 487 llvm::array_lengthof(g_coff_arch_entries), 488 g_coff_arch_entries, 489 "pe-coff", 490 }; 491 492 //===----------------------------------------------------------------------===// 493 // Table of all ArchDefinitions 494 static const ArchDefinition *g_arch_definitions[] = { 495 &g_macho_arch_def, &g_elf_arch_def, &g_coff_arch_def}; 496 497 static const size_t k_num_arch_definitions = 498 llvm::array_lengthof(g_arch_definitions); 499 500 //===----------------------------------------------------------------------===// 501 // Static helper functions. 502 503 // Get the architecture definition for a given object type. 504 static const ArchDefinition *FindArchDefinition(ArchitectureType arch_type) { 505 for (unsigned int i = 0; i < k_num_arch_definitions; ++i) { 506 const ArchDefinition *def = g_arch_definitions[i]; 507 if (def->type == arch_type) 508 return def; 509 } 510 return nullptr; 511 } 512 513 // Get an architecture definition by name. 514 static const CoreDefinition *FindCoreDefinition(llvm::StringRef name) { 515 for (unsigned int i = 0; i < llvm::array_lengthof(g_core_definitions); ++i) { 516 if (name.equals_lower(g_core_definitions[i].name)) 517 return &g_core_definitions[i]; 518 } 519 return nullptr; 520 } 521 522 static inline const CoreDefinition *FindCoreDefinition(ArchSpec::Core core) { 523 if (core < llvm::array_lengthof(g_core_definitions)) 524 return &g_core_definitions[core]; 525 return nullptr; 526 } 527 528 // Get a definition entry by cpu type and subtype. 529 static const ArchDefinitionEntry * 530 FindArchDefinitionEntry(const ArchDefinition *def, uint32_t cpu, uint32_t sub) { 531 if (def == nullptr) 532 return nullptr; 533 534 const ArchDefinitionEntry *entries = def->entries; 535 for (size_t i = 0; i < def->num_entries; ++i) { 536 if (entries[i].cpu == (cpu & entries[i].cpu_mask)) 537 if (entries[i].sub == (sub & entries[i].sub_mask)) 538 return &entries[i]; 539 } 540 return nullptr; 541 } 542 543 static const ArchDefinitionEntry * 544 FindArchDefinitionEntry(const ArchDefinition *def, ArchSpec::Core core) { 545 if (def == nullptr) 546 return nullptr; 547 548 const ArchDefinitionEntry *entries = def->entries; 549 for (size_t i = 0; i < def->num_entries; ++i) { 550 if (entries[i].core == core) 551 return &entries[i]; 552 } 553 return nullptr; 554 } 555 556 //===----------------------------------------------------------------------===// 557 // Constructors and destructors. 558 559 ArchSpec::ArchSpec() {} 560 561 ArchSpec::ArchSpec(const char *triple_cstr) { 562 if (triple_cstr) 563 SetTriple(triple_cstr); 564 } 565 566 ArchSpec::ArchSpec(llvm::StringRef triple_str) { SetTriple(triple_str); } 567 568 ArchSpec::ArchSpec(const llvm::Triple &triple) { SetTriple(triple); } 569 570 ArchSpec::ArchSpec(ArchitectureType arch_type, uint32_t cpu, uint32_t subtype) { 571 SetArchitecture(arch_type, cpu, subtype); 572 } 573 574 ArchSpec::~ArchSpec() = default; 575 576 void ArchSpec::Clear() { 577 m_triple = llvm::Triple(); 578 m_core = kCore_invalid; 579 m_byte_order = eByteOrderInvalid; 580 m_distribution_id.Clear(); 581 m_flags = 0; 582 } 583 584 //===----------------------------------------------------------------------===// 585 // Predicates. 586 587 const char *ArchSpec::GetArchitectureName() const { 588 const CoreDefinition *core_def = FindCoreDefinition(m_core); 589 if (core_def) 590 return core_def->name; 591 return "unknown"; 592 } 593 594 bool ArchSpec::IsMIPS() const { return GetTriple().isMIPS(); } 595 596 std::string ArchSpec::GetTargetABI() const { 597 598 std::string abi; 599 600 if (IsMIPS()) { 601 switch (GetFlags() & ArchSpec::eMIPSABI_mask) { 602 case ArchSpec::eMIPSABI_N64: 603 abi = "n64"; 604 return abi; 605 case ArchSpec::eMIPSABI_N32: 606 abi = "n32"; 607 return abi; 608 case ArchSpec::eMIPSABI_O32: 609 abi = "o32"; 610 return abi; 611 default: 612 return abi; 613 } 614 } 615 return abi; 616 } 617 618 void ArchSpec::SetFlags(std::string elf_abi) { 619 620 uint32_t flag = GetFlags(); 621 if (IsMIPS()) { 622 if (elf_abi == "n64") 623 flag |= ArchSpec::eMIPSABI_N64; 624 else if (elf_abi == "n32") 625 flag |= ArchSpec::eMIPSABI_N32; 626 else if (elf_abi == "o32") 627 flag |= ArchSpec::eMIPSABI_O32; 628 } 629 SetFlags(flag); 630 } 631 632 std::string ArchSpec::GetClangTargetCPU() const { 633 std::string cpu; 634 635 if (IsMIPS()) { 636 switch (m_core) { 637 case ArchSpec::eCore_mips32: 638 case ArchSpec::eCore_mips32el: 639 cpu = "mips32"; 640 break; 641 case ArchSpec::eCore_mips32r2: 642 case ArchSpec::eCore_mips32r2el: 643 cpu = "mips32r2"; 644 break; 645 case ArchSpec::eCore_mips32r3: 646 case ArchSpec::eCore_mips32r3el: 647 cpu = "mips32r3"; 648 break; 649 case ArchSpec::eCore_mips32r5: 650 case ArchSpec::eCore_mips32r5el: 651 cpu = "mips32r5"; 652 break; 653 case ArchSpec::eCore_mips32r6: 654 case ArchSpec::eCore_mips32r6el: 655 cpu = "mips32r6"; 656 break; 657 case ArchSpec::eCore_mips64: 658 case ArchSpec::eCore_mips64el: 659 cpu = "mips64"; 660 break; 661 case ArchSpec::eCore_mips64r2: 662 case ArchSpec::eCore_mips64r2el: 663 cpu = "mips64r2"; 664 break; 665 case ArchSpec::eCore_mips64r3: 666 case ArchSpec::eCore_mips64r3el: 667 cpu = "mips64r3"; 668 break; 669 case ArchSpec::eCore_mips64r5: 670 case ArchSpec::eCore_mips64r5el: 671 cpu = "mips64r5"; 672 break; 673 case ArchSpec::eCore_mips64r6: 674 case ArchSpec::eCore_mips64r6el: 675 cpu = "mips64r6"; 676 break; 677 default: 678 break; 679 } 680 } 681 return cpu; 682 } 683 684 uint32_t ArchSpec::GetMachOCPUType() const { 685 const CoreDefinition *core_def = FindCoreDefinition(m_core); 686 if (core_def) { 687 const ArchDefinitionEntry *arch_def = 688 FindArchDefinitionEntry(&g_macho_arch_def, core_def->core); 689 if (arch_def) { 690 return arch_def->cpu; 691 } 692 } 693 return LLDB_INVALID_CPUTYPE; 694 } 695 696 uint32_t ArchSpec::GetMachOCPUSubType() const { 697 const CoreDefinition *core_def = FindCoreDefinition(m_core); 698 if (core_def) { 699 const ArchDefinitionEntry *arch_def = 700 FindArchDefinitionEntry(&g_macho_arch_def, core_def->core); 701 if (arch_def) { 702 return arch_def->sub; 703 } 704 } 705 return LLDB_INVALID_CPUTYPE; 706 } 707 708 uint32_t ArchSpec::GetDataByteSize() const { 709 return 1; 710 } 711 712 uint32_t ArchSpec::GetCodeByteSize() const { 713 return 1; 714 } 715 716 llvm::Triple::ArchType ArchSpec::GetMachine() const { 717 const CoreDefinition *core_def = FindCoreDefinition(m_core); 718 if (core_def) 719 return core_def->machine; 720 721 return llvm::Triple::UnknownArch; 722 } 723 724 ConstString ArchSpec::GetDistributionId() const { 725 return m_distribution_id; 726 } 727 728 void ArchSpec::SetDistributionId(const char *distribution_id) { 729 m_distribution_id.SetCString(distribution_id); 730 } 731 732 uint32_t ArchSpec::GetAddressByteSize() const { 733 const CoreDefinition *core_def = FindCoreDefinition(m_core); 734 if (core_def) { 735 if (core_def->machine == llvm::Triple::mips64 || 736 core_def->machine == llvm::Triple::mips64el) { 737 // For N32/O32 applications Address size is 4 bytes. 738 if (m_flags & (eMIPSABI_N32 | eMIPSABI_O32)) 739 return 4; 740 } 741 return core_def->addr_byte_size; 742 } 743 return 0; 744 } 745 746 ByteOrder ArchSpec::GetDefaultEndian() const { 747 const CoreDefinition *core_def = FindCoreDefinition(m_core); 748 if (core_def) 749 return core_def->default_byte_order; 750 return eByteOrderInvalid; 751 } 752 753 bool ArchSpec::CharIsSignedByDefault() const { 754 switch (m_triple.getArch()) { 755 default: 756 return true; 757 758 case llvm::Triple::aarch64: 759 case llvm::Triple::aarch64_32: 760 case llvm::Triple::aarch64_be: 761 case llvm::Triple::arm: 762 case llvm::Triple::armeb: 763 case llvm::Triple::thumb: 764 case llvm::Triple::thumbeb: 765 return m_triple.isOSDarwin() || m_triple.isOSWindows(); 766 767 case llvm::Triple::ppc: 768 case llvm::Triple::ppc64: 769 return m_triple.isOSDarwin(); 770 771 case llvm::Triple::ppc64le: 772 case llvm::Triple::systemz: 773 case llvm::Triple::xcore: 774 case llvm::Triple::arc: 775 return false; 776 } 777 } 778 779 lldb::ByteOrder ArchSpec::GetByteOrder() const { 780 if (m_byte_order == eByteOrderInvalid) 781 return GetDefaultEndian(); 782 return m_byte_order; 783 } 784 785 //===----------------------------------------------------------------------===// 786 // Mutators. 787 788 bool ArchSpec::SetTriple(const llvm::Triple &triple) { 789 m_triple = triple; 790 UpdateCore(); 791 return IsValid(); 792 } 793 794 bool lldb_private::ParseMachCPUDashSubtypeTriple(llvm::StringRef triple_str, 795 ArchSpec &arch) { 796 // Accept "12-10" or "12.10" as cpu type/subtype 797 if (triple_str.empty()) 798 return false; 799 800 size_t pos = triple_str.find_first_of("-."); 801 if (pos == llvm::StringRef::npos) 802 return false; 803 804 llvm::StringRef cpu_str = triple_str.substr(0, pos); 805 llvm::StringRef remainder = triple_str.substr(pos + 1); 806 if (cpu_str.empty() || remainder.empty()) 807 return false; 808 809 llvm::StringRef sub_str; 810 llvm::StringRef vendor; 811 llvm::StringRef os; 812 std::tie(sub_str, remainder) = remainder.split('-'); 813 std::tie(vendor, os) = remainder.split('-'); 814 815 uint32_t cpu = 0; 816 uint32_t sub = 0; 817 if (cpu_str.getAsInteger(10, cpu) || sub_str.getAsInteger(10, sub)) 818 return false; 819 820 if (!arch.SetArchitecture(eArchTypeMachO, cpu, sub)) 821 return false; 822 if (!vendor.empty() && !os.empty()) { 823 arch.GetTriple().setVendorName(vendor); 824 arch.GetTriple().setOSName(os); 825 } 826 827 return true; 828 } 829 830 bool ArchSpec::SetTriple(llvm::StringRef triple) { 831 if (triple.empty()) { 832 Clear(); 833 return false; 834 } 835 836 if (ParseMachCPUDashSubtypeTriple(triple, *this)) 837 return true; 838 839 SetTriple(llvm::Triple(llvm::Triple::normalize(triple))); 840 return IsValid(); 841 } 842 843 bool ArchSpec::ContainsOnlyArch(const llvm::Triple &normalized_triple) { 844 return !normalized_triple.getArchName().empty() && 845 normalized_triple.getOSName().empty() && 846 normalized_triple.getVendorName().empty() && 847 normalized_triple.getEnvironmentName().empty(); 848 } 849 850 void ArchSpec::MergeFrom(const ArchSpec &other) { 851 if (!TripleVendorWasSpecified() && other.TripleVendorWasSpecified()) 852 GetTriple().setVendor(other.GetTriple().getVendor()); 853 if (!TripleOSWasSpecified() && other.TripleOSWasSpecified()) 854 GetTriple().setOS(other.GetTriple().getOS()); 855 if (GetTriple().getArch() == llvm::Triple::UnknownArch) { 856 GetTriple().setArch(other.GetTriple().getArch()); 857 858 // MachO unknown64 isn't really invalid as the debugger can still obtain 859 // information from the binary, e.g. line tables. As such, we don't update 860 // the core here. 861 if (other.GetCore() != eCore_uknownMach64) 862 UpdateCore(); 863 } 864 if (!TripleEnvironmentWasSpecified() && 865 other.TripleEnvironmentWasSpecified()) { 866 GetTriple().setEnvironment(other.GetTriple().getEnvironment()); 867 } 868 // If this and other are both arm ArchSpecs and this ArchSpec is a generic 869 // "some kind of arm" spec but the other ArchSpec is a specific arm core, 870 // adopt the specific arm core. 871 if (GetTriple().getArch() == llvm::Triple::arm && 872 other.GetTriple().getArch() == llvm::Triple::arm && 873 IsCompatibleMatch(other) && GetCore() == ArchSpec::eCore_arm_generic && 874 other.GetCore() != ArchSpec::eCore_arm_generic) { 875 m_core = other.GetCore(); 876 CoreUpdated(false); 877 } 878 if (GetFlags() == 0) { 879 SetFlags(other.GetFlags()); 880 } 881 } 882 883 bool ArchSpec::SetArchitecture(ArchitectureType arch_type, uint32_t cpu, 884 uint32_t sub, uint32_t os) { 885 m_core = kCore_invalid; 886 bool update_triple = true; 887 const ArchDefinition *arch_def = FindArchDefinition(arch_type); 888 if (arch_def) { 889 const ArchDefinitionEntry *arch_def_entry = 890 FindArchDefinitionEntry(arch_def, cpu, sub); 891 if (arch_def_entry) { 892 const CoreDefinition *core_def = FindCoreDefinition(arch_def_entry->core); 893 if (core_def) { 894 m_core = core_def->core; 895 update_triple = false; 896 // Always use the architecture name because it might be more 897 // descriptive than the architecture enum ("armv7" -> 898 // llvm::Triple::arm). 899 m_triple.setArchName(llvm::StringRef(core_def->name)); 900 if (arch_type == eArchTypeMachO) { 901 m_triple.setVendor(llvm::Triple::Apple); 902 903 // Don't set the OS. It could be simulator, macosx, ios, watchos, 904 // tvos, bridgeos. We could get close with the cpu type - but we 905 // can't get it right all of the time. Better to leave this unset 906 // so other sections of code will set it when they have more 907 // information. NB: don't call m_triple.setOS 908 // (llvm::Triple::UnknownOS). That sets the OSName to "unknown" and 909 // the ArchSpec::TripleVendorWasSpecified() method says that any 910 // OSName setting means it was specified. 911 } else if (arch_type == eArchTypeELF) { 912 switch (os) { 913 case llvm::ELF::ELFOSABI_AIX: 914 m_triple.setOS(llvm::Triple::OSType::AIX); 915 break; 916 case llvm::ELF::ELFOSABI_FREEBSD: 917 m_triple.setOS(llvm::Triple::OSType::FreeBSD); 918 break; 919 case llvm::ELF::ELFOSABI_GNU: 920 m_triple.setOS(llvm::Triple::OSType::Linux); 921 break; 922 case llvm::ELF::ELFOSABI_NETBSD: 923 m_triple.setOS(llvm::Triple::OSType::NetBSD); 924 break; 925 case llvm::ELF::ELFOSABI_OPENBSD: 926 m_triple.setOS(llvm::Triple::OSType::OpenBSD); 927 break; 928 case llvm::ELF::ELFOSABI_SOLARIS: 929 m_triple.setOS(llvm::Triple::OSType::Solaris); 930 break; 931 } 932 } else if (arch_type == eArchTypeCOFF && os == llvm::Triple::Win32) { 933 m_triple.setVendor(llvm::Triple::PC); 934 m_triple.setOS(llvm::Triple::Win32); 935 } else { 936 m_triple.setVendor(llvm::Triple::UnknownVendor); 937 m_triple.setOS(llvm::Triple::UnknownOS); 938 } 939 // Fall back onto setting the machine type if the arch by name 940 // failed... 941 if (m_triple.getArch() == llvm::Triple::UnknownArch) 942 m_triple.setArch(core_def->machine); 943 } 944 } else { 945 Log *log(lldb_private::GetLogIfAnyCategoriesSet(LIBLLDB_LOG_TARGET | LIBLLDB_LOG_PROCESS | LIBLLDB_LOG_PLATFORM)); 946 LLDB_LOGF(log, 947 "Unable to find a core definition for cpu 0x%" PRIx32 948 " sub %" PRId32, 949 cpu, sub); 950 } 951 } 952 CoreUpdated(update_triple); 953 return IsValid(); 954 } 955 956 uint32_t ArchSpec::GetMinimumOpcodeByteSize() const { 957 const CoreDefinition *core_def = FindCoreDefinition(m_core); 958 if (core_def) 959 return core_def->min_opcode_byte_size; 960 return 0; 961 } 962 963 uint32_t ArchSpec::GetMaximumOpcodeByteSize() const { 964 const CoreDefinition *core_def = FindCoreDefinition(m_core); 965 if (core_def) 966 return core_def->max_opcode_byte_size; 967 return 0; 968 } 969 970 bool ArchSpec::IsExactMatch(const ArchSpec &rhs) const { 971 return IsEqualTo(rhs, true); 972 } 973 974 bool ArchSpec::IsCompatibleMatch(const ArchSpec &rhs) const { 975 return IsEqualTo(rhs, false); 976 } 977 978 static bool IsCompatibleEnvironment(llvm::Triple::EnvironmentType lhs, 979 llvm::Triple::EnvironmentType rhs) { 980 if (lhs == rhs) 981 return true; 982 983 // If any of the environment is unknown then they are compatible 984 if (lhs == llvm::Triple::UnknownEnvironment || 985 rhs == llvm::Triple::UnknownEnvironment) 986 return true; 987 988 // If one of the environment is Android and the other one is EABI then they 989 // are considered to be compatible. This is required as a workaround for 990 // shared libraries compiled for Android without the NOTE section indicating 991 // that they are using the Android ABI. 992 if ((lhs == llvm::Triple::Android && rhs == llvm::Triple::EABI) || 993 (rhs == llvm::Triple::Android && lhs == llvm::Triple::EABI) || 994 (lhs == llvm::Triple::GNUEABI && rhs == llvm::Triple::EABI) || 995 (rhs == llvm::Triple::GNUEABI && lhs == llvm::Triple::EABI) || 996 (lhs == llvm::Triple::GNUEABIHF && rhs == llvm::Triple::EABIHF) || 997 (rhs == llvm::Triple::GNUEABIHF && lhs == llvm::Triple::EABIHF)) 998 return true; 999 1000 return false; 1001 } 1002 1003 bool ArchSpec::IsEqualTo(const ArchSpec &rhs, bool exact_match) const { 1004 // explicitly ignoring m_distribution_id in this method. 1005 1006 if (GetByteOrder() != rhs.GetByteOrder()) 1007 return false; 1008 1009 const ArchSpec::Core lhs_core = GetCore(); 1010 const ArchSpec::Core rhs_core = rhs.GetCore(); 1011 1012 const bool core_match = cores_match(lhs_core, rhs_core, true, exact_match); 1013 1014 if (core_match) { 1015 const llvm::Triple &lhs_triple = GetTriple(); 1016 const llvm::Triple &rhs_triple = rhs.GetTriple(); 1017 1018 const llvm::Triple::VendorType lhs_triple_vendor = lhs_triple.getVendor(); 1019 const llvm::Triple::VendorType rhs_triple_vendor = rhs_triple.getVendor(); 1020 if (lhs_triple_vendor != rhs_triple_vendor) { 1021 const bool rhs_vendor_specified = rhs.TripleVendorWasSpecified(); 1022 const bool lhs_vendor_specified = TripleVendorWasSpecified(); 1023 // Both architectures had the vendor specified, so if they aren't equal 1024 // then we return false 1025 if (rhs_vendor_specified && lhs_vendor_specified) 1026 return false; 1027 1028 // Only fail if both vendor types are not unknown 1029 if (lhs_triple_vendor != llvm::Triple::UnknownVendor && 1030 rhs_triple_vendor != llvm::Triple::UnknownVendor) 1031 return false; 1032 } 1033 1034 const llvm::Triple::OSType lhs_triple_os = lhs_triple.getOS(); 1035 const llvm::Triple::OSType rhs_triple_os = rhs_triple.getOS(); 1036 if (lhs_triple_os != rhs_triple_os) { 1037 const bool rhs_os_specified = rhs.TripleOSWasSpecified(); 1038 const bool lhs_os_specified = TripleOSWasSpecified(); 1039 // Both architectures had the OS specified, so if they aren't equal then 1040 // we return false 1041 if (rhs_os_specified && lhs_os_specified) 1042 return false; 1043 1044 // Only fail if both os types are not unknown 1045 if (lhs_triple_os != llvm::Triple::UnknownOS && 1046 rhs_triple_os != llvm::Triple::UnknownOS) 1047 return false; 1048 } 1049 1050 const llvm::Triple::EnvironmentType lhs_triple_env = 1051 lhs_triple.getEnvironment(); 1052 const llvm::Triple::EnvironmentType rhs_triple_env = 1053 rhs_triple.getEnvironment(); 1054 1055 return IsCompatibleEnvironment(lhs_triple_env, rhs_triple_env); 1056 } 1057 return false; 1058 } 1059 1060 void ArchSpec::UpdateCore() { 1061 llvm::StringRef arch_name(m_triple.getArchName()); 1062 const CoreDefinition *core_def = FindCoreDefinition(arch_name); 1063 if (core_def) { 1064 m_core = core_def->core; 1065 // Set the byte order to the default byte order for an architecture. This 1066 // can be modified if needed for cases when cores handle both big and 1067 // little endian 1068 m_byte_order = core_def->default_byte_order; 1069 } else { 1070 Clear(); 1071 } 1072 } 1073 1074 //===----------------------------------------------------------------------===// 1075 // Helper methods. 1076 1077 void ArchSpec::CoreUpdated(bool update_triple) { 1078 const CoreDefinition *core_def = FindCoreDefinition(m_core); 1079 if (core_def) { 1080 if (update_triple) 1081 m_triple = llvm::Triple(core_def->name, "unknown", "unknown"); 1082 m_byte_order = core_def->default_byte_order; 1083 } else { 1084 if (update_triple) 1085 m_triple = llvm::Triple(); 1086 m_byte_order = eByteOrderInvalid; 1087 } 1088 } 1089 1090 //===----------------------------------------------------------------------===// 1091 // Operators. 1092 1093 static bool cores_match(const ArchSpec::Core core1, const ArchSpec::Core core2, 1094 bool try_inverse, bool enforce_exact_match) { 1095 if (core1 == core2) 1096 return true; 1097 1098 switch (core1) { 1099 case ArchSpec::kCore_any: 1100 return true; 1101 1102 case ArchSpec::eCore_arm_generic: 1103 if (enforce_exact_match) 1104 break; 1105 LLVM_FALLTHROUGH; 1106 case ArchSpec::kCore_arm_any: 1107 if (core2 >= ArchSpec::kCore_arm_first && core2 <= ArchSpec::kCore_arm_last) 1108 return true; 1109 if (core2 >= ArchSpec::kCore_thumb_first && 1110 core2 <= ArchSpec::kCore_thumb_last) 1111 return true; 1112 if (core2 == ArchSpec::kCore_arm_any) 1113 return true; 1114 break; 1115 1116 case ArchSpec::kCore_x86_32_any: 1117 if ((core2 >= ArchSpec::kCore_x86_32_first && 1118 core2 <= ArchSpec::kCore_x86_32_last) || 1119 (core2 == ArchSpec::kCore_x86_32_any)) 1120 return true; 1121 break; 1122 1123 case ArchSpec::kCore_x86_64_any: 1124 if ((core2 >= ArchSpec::kCore_x86_64_first && 1125 core2 <= ArchSpec::kCore_x86_64_last) || 1126 (core2 == ArchSpec::kCore_x86_64_any)) 1127 return true; 1128 break; 1129 1130 case ArchSpec::kCore_ppc_any: 1131 if ((core2 >= ArchSpec::kCore_ppc_first && 1132 core2 <= ArchSpec::kCore_ppc_last) || 1133 (core2 == ArchSpec::kCore_ppc_any)) 1134 return true; 1135 break; 1136 1137 case ArchSpec::kCore_ppc64_any: 1138 if ((core2 >= ArchSpec::kCore_ppc64_first && 1139 core2 <= ArchSpec::kCore_ppc64_last) || 1140 (core2 == ArchSpec::kCore_ppc64_any)) 1141 return true; 1142 break; 1143 1144 case ArchSpec::eCore_arm_armv6m: 1145 if (!enforce_exact_match) { 1146 if (core2 == ArchSpec::eCore_arm_generic) 1147 return true; 1148 try_inverse = false; 1149 if (core2 == ArchSpec::eCore_arm_armv7) 1150 return true; 1151 if (core2 == ArchSpec::eCore_arm_armv6m) 1152 return true; 1153 } 1154 break; 1155 1156 case ArchSpec::kCore_hexagon_any: 1157 if ((core2 >= ArchSpec::kCore_hexagon_first && 1158 core2 <= ArchSpec::kCore_hexagon_last) || 1159 (core2 == ArchSpec::kCore_hexagon_any)) 1160 return true; 1161 break; 1162 1163 // v. https://en.wikipedia.org/wiki/ARM_Cortex-M#Silicon_customization 1164 // Cortex-M0 - ARMv6-M - armv6m Cortex-M3 - ARMv7-M - armv7m Cortex-M4 - 1165 // ARMv7E-M - armv7em 1166 case ArchSpec::eCore_arm_armv7em: 1167 if (!enforce_exact_match) { 1168 if (core2 == ArchSpec::eCore_arm_generic) 1169 return true; 1170 if (core2 == ArchSpec::eCore_arm_armv7m) 1171 return true; 1172 if (core2 == ArchSpec::eCore_arm_armv6m) 1173 return true; 1174 if (core2 == ArchSpec::eCore_arm_armv7) 1175 return true; 1176 try_inverse = true; 1177 } 1178 break; 1179 1180 // v. https://en.wikipedia.org/wiki/ARM_Cortex-M#Silicon_customization 1181 // Cortex-M0 - ARMv6-M - armv6m Cortex-M3 - ARMv7-M - armv7m Cortex-M4 - 1182 // ARMv7E-M - armv7em 1183 case ArchSpec::eCore_arm_armv7m: 1184 if (!enforce_exact_match) { 1185 if (core2 == ArchSpec::eCore_arm_generic) 1186 return true; 1187 if (core2 == ArchSpec::eCore_arm_armv6m) 1188 return true; 1189 if (core2 == ArchSpec::eCore_arm_armv7) 1190 return true; 1191 if (core2 == ArchSpec::eCore_arm_armv7em) 1192 return true; 1193 try_inverse = true; 1194 } 1195 break; 1196 1197 case ArchSpec::eCore_arm_armv7f: 1198 case ArchSpec::eCore_arm_armv7k: 1199 case ArchSpec::eCore_arm_armv7s: 1200 case ArchSpec::eCore_arm_armv7l: 1201 case ArchSpec::eCore_arm_armv8l: 1202 if (!enforce_exact_match) { 1203 if (core2 == ArchSpec::eCore_arm_generic) 1204 return true; 1205 if (core2 == ArchSpec::eCore_arm_armv7) 1206 return true; 1207 try_inverse = false; 1208 } 1209 break; 1210 1211 case ArchSpec::eCore_x86_64_x86_64h: 1212 if (!enforce_exact_match) { 1213 if (core2 == ArchSpec::eCore_x86_64_x86_64) 1214 return true; 1215 try_inverse = false; 1216 } 1217 break; 1218 1219 case ArchSpec::eCore_x86_64_amd64: 1220 if (!enforce_exact_match) { 1221 if (core2 == ArchSpec::eCore_x86_64_x86_64) 1222 return true; 1223 try_inverse = false; 1224 } 1225 break; 1226 1227 case ArchSpec::eCore_arm_armv8: 1228 if (!enforce_exact_match) { 1229 if (core2 == ArchSpec::eCore_arm_arm64) 1230 return true; 1231 if (core2 == ArchSpec::eCore_arm_aarch64) 1232 return true; 1233 try_inverse = false; 1234 } 1235 break; 1236 1237 case ArchSpec::eCore_arm_aarch64: 1238 if (!enforce_exact_match) { 1239 if (core2 == ArchSpec::eCore_arm_arm64) 1240 return true; 1241 if (core2 == ArchSpec::eCore_arm_armv8) 1242 return true; 1243 try_inverse = false; 1244 } 1245 break; 1246 1247 case ArchSpec::eCore_arm_arm64: 1248 if (!enforce_exact_match) { 1249 if (core2 == ArchSpec::eCore_arm_aarch64) 1250 return true; 1251 if (core2 == ArchSpec::eCore_arm_armv8) 1252 return true; 1253 try_inverse = false; 1254 } 1255 break; 1256 1257 case ArchSpec::eCore_arm_arm64_32: 1258 if (!enforce_exact_match) { 1259 if (core2 == ArchSpec::eCore_arm_generic) 1260 return true; 1261 try_inverse = false; 1262 } 1263 break; 1264 1265 case ArchSpec::eCore_mips32: 1266 if (!enforce_exact_match) { 1267 if (core2 >= ArchSpec::kCore_mips32_first && 1268 core2 <= ArchSpec::kCore_mips32_last) 1269 return true; 1270 try_inverse = false; 1271 } 1272 break; 1273 1274 case ArchSpec::eCore_mips32el: 1275 if (!enforce_exact_match) { 1276 if (core2 >= ArchSpec::kCore_mips32el_first && 1277 core2 <= ArchSpec::kCore_mips32el_last) 1278 return true; 1279 try_inverse = true; 1280 } 1281 break; 1282 1283 case ArchSpec::eCore_mips64: 1284 if (!enforce_exact_match) { 1285 if (core2 >= ArchSpec::kCore_mips32_first && 1286 core2 <= ArchSpec::kCore_mips32_last) 1287 return true; 1288 if (core2 >= ArchSpec::kCore_mips64_first && 1289 core2 <= ArchSpec::kCore_mips64_last) 1290 return true; 1291 try_inverse = false; 1292 } 1293 break; 1294 1295 case ArchSpec::eCore_mips64el: 1296 if (!enforce_exact_match) { 1297 if (core2 >= ArchSpec::kCore_mips32el_first && 1298 core2 <= ArchSpec::kCore_mips32el_last) 1299 return true; 1300 if (core2 >= ArchSpec::kCore_mips64el_first && 1301 core2 <= ArchSpec::kCore_mips64el_last) 1302 return true; 1303 try_inverse = false; 1304 } 1305 break; 1306 1307 case ArchSpec::eCore_mips64r2: 1308 case ArchSpec::eCore_mips64r3: 1309 case ArchSpec::eCore_mips64r5: 1310 if (!enforce_exact_match) { 1311 if (core2 >= ArchSpec::kCore_mips32_first && core2 <= (core1 - 10)) 1312 return true; 1313 if (core2 >= ArchSpec::kCore_mips64_first && core2 <= (core1 - 1)) 1314 return true; 1315 try_inverse = false; 1316 } 1317 break; 1318 1319 case ArchSpec::eCore_mips64r2el: 1320 case ArchSpec::eCore_mips64r3el: 1321 case ArchSpec::eCore_mips64r5el: 1322 if (!enforce_exact_match) { 1323 if (core2 >= ArchSpec::kCore_mips32el_first && core2 <= (core1 - 10)) 1324 return true; 1325 if (core2 >= ArchSpec::kCore_mips64el_first && core2 <= (core1 - 1)) 1326 return true; 1327 try_inverse = false; 1328 } 1329 break; 1330 1331 case ArchSpec::eCore_mips32r2: 1332 case ArchSpec::eCore_mips32r3: 1333 case ArchSpec::eCore_mips32r5: 1334 if (!enforce_exact_match) { 1335 if (core2 >= ArchSpec::kCore_mips32_first && core2 <= core1) 1336 return true; 1337 } 1338 break; 1339 1340 case ArchSpec::eCore_mips32r2el: 1341 case ArchSpec::eCore_mips32r3el: 1342 case ArchSpec::eCore_mips32r5el: 1343 if (!enforce_exact_match) { 1344 if (core2 >= ArchSpec::kCore_mips32el_first && core2 <= core1) 1345 return true; 1346 } 1347 break; 1348 1349 case ArchSpec::eCore_mips32r6: 1350 if (!enforce_exact_match) { 1351 if (core2 == ArchSpec::eCore_mips32 || core2 == ArchSpec::eCore_mips32r6) 1352 return true; 1353 } 1354 break; 1355 1356 case ArchSpec::eCore_mips32r6el: 1357 if (!enforce_exact_match) { 1358 if (core2 == ArchSpec::eCore_mips32el || 1359 core2 == ArchSpec::eCore_mips32r6el) 1360 return true; 1361 } 1362 break; 1363 1364 case ArchSpec::eCore_mips64r6: 1365 if (!enforce_exact_match) { 1366 if (core2 == ArchSpec::eCore_mips32 || core2 == ArchSpec::eCore_mips32r6) 1367 return true; 1368 if (core2 == ArchSpec::eCore_mips64 || core2 == ArchSpec::eCore_mips64r6) 1369 return true; 1370 } 1371 break; 1372 1373 case ArchSpec::eCore_mips64r6el: 1374 if (!enforce_exact_match) { 1375 if (core2 == ArchSpec::eCore_mips32el || 1376 core2 == ArchSpec::eCore_mips32r6el) 1377 return true; 1378 if (core2 == ArchSpec::eCore_mips64el || 1379 core2 == ArchSpec::eCore_mips64r6el) 1380 return true; 1381 } 1382 break; 1383 1384 default: 1385 break; 1386 } 1387 if (try_inverse) 1388 return cores_match(core2, core1, false, enforce_exact_match); 1389 return false; 1390 } 1391 1392 bool lldb_private::operator<(const ArchSpec &lhs, const ArchSpec &rhs) { 1393 const ArchSpec::Core lhs_core = lhs.GetCore(); 1394 const ArchSpec::Core rhs_core = rhs.GetCore(); 1395 return lhs_core < rhs_core; 1396 } 1397 1398 1399 bool lldb_private::operator==(const ArchSpec &lhs, const ArchSpec &rhs) { 1400 return lhs.GetCore() == rhs.GetCore(); 1401 } 1402 1403 bool ArchSpec::IsFullySpecifiedTriple() const { 1404 const auto &user_specified_triple = GetTriple(); 1405 1406 bool user_triple_fully_specified = false; 1407 1408 if ((user_specified_triple.getOS() != llvm::Triple::UnknownOS) || 1409 TripleOSWasSpecified()) { 1410 if ((user_specified_triple.getVendor() != llvm::Triple::UnknownVendor) || 1411 TripleVendorWasSpecified()) { 1412 const unsigned unspecified = 0; 1413 if (user_specified_triple.getOSMajorVersion() != unspecified) { 1414 user_triple_fully_specified = true; 1415 } 1416 } 1417 } 1418 1419 return user_triple_fully_specified; 1420 } 1421 1422 void ArchSpec::PiecewiseTripleCompare( 1423 const ArchSpec &other, bool &arch_different, bool &vendor_different, 1424 bool &os_different, bool &os_version_different, bool &env_different) const { 1425 const llvm::Triple &me(GetTriple()); 1426 const llvm::Triple &them(other.GetTriple()); 1427 1428 arch_different = (me.getArch() != them.getArch()); 1429 1430 vendor_different = (me.getVendor() != them.getVendor()); 1431 1432 os_different = (me.getOS() != them.getOS()); 1433 1434 os_version_different = (me.getOSMajorVersion() != them.getOSMajorVersion()); 1435 1436 env_different = (me.getEnvironment() != them.getEnvironment()); 1437 } 1438 1439 bool ArchSpec::IsAlwaysThumbInstructions() const { 1440 std::string Status; 1441 if (GetTriple().getArch() == llvm::Triple::arm || 1442 GetTriple().getArch() == llvm::Triple::thumb) { 1443 // v. https://en.wikipedia.org/wiki/ARM_Cortex-M 1444 // 1445 // Cortex-M0 through Cortex-M7 are ARM processor cores which can only 1446 // execute thumb instructions. We map the cores to arch names like this: 1447 // 1448 // Cortex-M0, Cortex-M0+, Cortex-M1: armv6m Cortex-M3: armv7m Cortex-M4, 1449 // Cortex-M7: armv7em 1450 1451 if (GetCore() == ArchSpec::Core::eCore_arm_armv7m || 1452 GetCore() == ArchSpec::Core::eCore_arm_armv7em || 1453 GetCore() == ArchSpec::Core::eCore_arm_armv6m || 1454 GetCore() == ArchSpec::Core::eCore_thumbv7m || 1455 GetCore() == ArchSpec::Core::eCore_thumbv7em || 1456 GetCore() == ArchSpec::Core::eCore_thumbv6m) { 1457 return true; 1458 } 1459 // Windows on ARM is always thumb. 1460 if (GetTriple().isOSWindows()) 1461 return true; 1462 } 1463 return false; 1464 } 1465 1466 void ArchSpec::DumpTriple(llvm::raw_ostream &s) const { 1467 const llvm::Triple &triple = GetTriple(); 1468 llvm::StringRef arch_str = triple.getArchName(); 1469 llvm::StringRef vendor_str = triple.getVendorName(); 1470 llvm::StringRef os_str = triple.getOSName(); 1471 llvm::StringRef environ_str = triple.getEnvironmentName(); 1472 1473 s << llvm::formatv("{0}-{1}-{2}", arch_str.empty() ? "*" : arch_str, 1474 vendor_str.empty() ? "*" : vendor_str, 1475 os_str.empty() ? "*" : os_str); 1476 1477 if (!environ_str.empty()) 1478 s << "-" << environ_str; 1479 } 1480 1481 void llvm::yaml::ScalarTraits<ArchSpec>::output(const ArchSpec &Val, void *, 1482 raw_ostream &Out) { 1483 Val.DumpTriple(Out); 1484 } 1485 1486 llvm::StringRef 1487 llvm::yaml::ScalarTraits<ArchSpec>::input(llvm::StringRef Scalar, void *, 1488 ArchSpec &Val) { 1489 Val = ArchSpec(Scalar); 1490 return {}; 1491 } 1492