1 //===-- ArchSpec.cpp --------------------------------------------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 9 #include "lldb/Utility/ArchSpec.h" 10 11 #include "lldb/Utility/Log.h" 12 #include "lldb/Utility/StringList.h" 13 #include "lldb/lldb-defines.h" 14 #include "llvm/ADT/STLExtras.h" 15 #include "llvm/BinaryFormat/COFF.h" 16 #include "llvm/BinaryFormat/ELF.h" 17 #include "llvm/BinaryFormat/MachO.h" 18 #include "llvm/Support/Compiler.h" 19 20 using namespace lldb; 21 using namespace lldb_private; 22 23 static bool cores_match(const ArchSpec::Core core1, const ArchSpec::Core core2, 24 bool try_inverse, bool enforce_exact_match); 25 26 namespace lldb_private { 27 28 struct CoreDefinition { 29 ByteOrder default_byte_order; 30 uint32_t addr_byte_size; 31 uint32_t min_opcode_byte_size; 32 uint32_t max_opcode_byte_size; 33 llvm::Triple::ArchType machine; 34 ArchSpec::Core core; 35 const char *const name; 36 }; 37 38 } // namespace lldb_private 39 40 // This core information can be looked using the ArchSpec::Core as the index 41 static const CoreDefinition g_core_definitions[] = { 42 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_generic, 43 "arm"}, 44 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv4, 45 "armv4"}, 46 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv4t, 47 "armv4t"}, 48 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv5, 49 "armv5"}, 50 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv5e, 51 "armv5e"}, 52 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv5t, 53 "armv5t"}, 54 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv6, 55 "armv6"}, 56 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv6m, 57 "armv6m"}, 58 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7, 59 "armv7"}, 60 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7l, 61 "armv7l"}, 62 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7f, 63 "armv7f"}, 64 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7s, 65 "armv7s"}, 66 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7k, 67 "armv7k"}, 68 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7m, 69 "armv7m"}, 70 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7em, 71 "armv7em"}, 72 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_xscale, 73 "xscale"}, 74 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumb, 75 "thumb"}, 76 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv4t, 77 "thumbv4t"}, 78 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv5, 79 "thumbv5"}, 80 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv5e, 81 "thumbv5e"}, 82 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv6, 83 "thumbv6"}, 84 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv6m, 85 "thumbv6m"}, 86 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv7, 87 "thumbv7"}, 88 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv7f, 89 "thumbv7f"}, 90 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv7s, 91 "thumbv7s"}, 92 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv7k, 93 "thumbv7k"}, 94 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv7m, 95 "thumbv7m"}, 96 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv7em, 97 "thumbv7em"}, 98 {eByteOrderLittle, 8, 4, 4, llvm::Triple::aarch64, 99 ArchSpec::eCore_arm_arm64, "arm64"}, 100 {eByteOrderLittle, 8, 4, 4, llvm::Triple::aarch64, 101 ArchSpec::eCore_arm_armv8, "armv8"}, 102 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, 103 ArchSpec::eCore_arm_armv8l, "armv8l"}, 104 {eByteOrderLittle, 4, 4, 4, llvm::Triple::aarch64_32, 105 ArchSpec::eCore_arm_arm64_32, "arm64_32"}, 106 {eByteOrderLittle, 8, 4, 4, llvm::Triple::aarch64, 107 ArchSpec::eCore_arm_aarch64, "aarch64"}, 108 109 // mips32, mips32r2, mips32r3, mips32r5, mips32r6 110 {eByteOrderBig, 4, 2, 4, llvm::Triple::mips, ArchSpec::eCore_mips32, 111 "mips"}, 112 {eByteOrderBig, 4, 2, 4, llvm::Triple::mips, ArchSpec::eCore_mips32r2, 113 "mipsr2"}, 114 {eByteOrderBig, 4, 2, 4, llvm::Triple::mips, ArchSpec::eCore_mips32r3, 115 "mipsr3"}, 116 {eByteOrderBig, 4, 2, 4, llvm::Triple::mips, ArchSpec::eCore_mips32r5, 117 "mipsr5"}, 118 {eByteOrderBig, 4, 2, 4, llvm::Triple::mips, ArchSpec::eCore_mips32r6, 119 "mipsr6"}, 120 {eByteOrderLittle, 4, 2, 4, llvm::Triple::mipsel, ArchSpec::eCore_mips32el, 121 "mipsel"}, 122 {eByteOrderLittle, 4, 2, 4, llvm::Triple::mipsel, 123 ArchSpec::eCore_mips32r2el, "mipsr2el"}, 124 {eByteOrderLittle, 4, 2, 4, llvm::Triple::mipsel, 125 ArchSpec::eCore_mips32r3el, "mipsr3el"}, 126 {eByteOrderLittle, 4, 2, 4, llvm::Triple::mipsel, 127 ArchSpec::eCore_mips32r5el, "mipsr5el"}, 128 {eByteOrderLittle, 4, 2, 4, llvm::Triple::mipsel, 129 ArchSpec::eCore_mips32r6el, "mipsr6el"}, 130 131 // mips64, mips64r2, mips64r3, mips64r5, mips64r6 132 {eByteOrderBig, 8, 2, 4, llvm::Triple::mips64, ArchSpec::eCore_mips64, 133 "mips64"}, 134 {eByteOrderBig, 8, 2, 4, llvm::Triple::mips64, ArchSpec::eCore_mips64r2, 135 "mips64r2"}, 136 {eByteOrderBig, 8, 2, 4, llvm::Triple::mips64, ArchSpec::eCore_mips64r3, 137 "mips64r3"}, 138 {eByteOrderBig, 8, 2, 4, llvm::Triple::mips64, ArchSpec::eCore_mips64r5, 139 "mips64r5"}, 140 {eByteOrderBig, 8, 2, 4, llvm::Triple::mips64, ArchSpec::eCore_mips64r6, 141 "mips64r6"}, 142 {eByteOrderLittle, 8, 2, 4, llvm::Triple::mips64el, 143 ArchSpec::eCore_mips64el, "mips64el"}, 144 {eByteOrderLittle, 8, 2, 4, llvm::Triple::mips64el, 145 ArchSpec::eCore_mips64r2el, "mips64r2el"}, 146 {eByteOrderLittle, 8, 2, 4, llvm::Triple::mips64el, 147 ArchSpec::eCore_mips64r3el, "mips64r3el"}, 148 {eByteOrderLittle, 8, 2, 4, llvm::Triple::mips64el, 149 ArchSpec::eCore_mips64r5el, "mips64r5el"}, 150 {eByteOrderLittle, 8, 2, 4, llvm::Triple::mips64el, 151 ArchSpec::eCore_mips64r6el, "mips64r6el"}, 152 153 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_generic, 154 "powerpc"}, 155 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc601, 156 "ppc601"}, 157 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc602, 158 "ppc602"}, 159 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc603, 160 "ppc603"}, 161 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc603e, 162 "ppc603e"}, 163 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc603ev, 164 "ppc603ev"}, 165 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc604, 166 "ppc604"}, 167 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc604e, 168 "ppc604e"}, 169 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc620, 170 "ppc620"}, 171 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc750, 172 "ppc750"}, 173 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc7400, 174 "ppc7400"}, 175 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc7450, 176 "ppc7450"}, 177 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc970, 178 "ppc970"}, 179 180 {eByteOrderLittle, 8, 4, 4, llvm::Triple::ppc64le, 181 ArchSpec::eCore_ppc64le_generic, "powerpc64le"}, 182 {eByteOrderBig, 8, 4, 4, llvm::Triple::ppc64, ArchSpec::eCore_ppc64_generic, 183 "powerpc64"}, 184 {eByteOrderBig, 8, 4, 4, llvm::Triple::ppc64, 185 ArchSpec::eCore_ppc64_ppc970_64, "ppc970-64"}, 186 187 {eByteOrderBig, 8, 2, 6, llvm::Triple::systemz, 188 ArchSpec::eCore_s390x_generic, "s390x"}, 189 190 {eByteOrderLittle, 4, 4, 4, llvm::Triple::sparc, 191 ArchSpec::eCore_sparc_generic, "sparc"}, 192 {eByteOrderLittle, 8, 4, 4, llvm::Triple::sparcv9, 193 ArchSpec::eCore_sparc9_generic, "sparcv9"}, 194 195 {eByteOrderLittle, 4, 1, 15, llvm::Triple::x86, ArchSpec::eCore_x86_32_i386, 196 "i386"}, 197 {eByteOrderLittle, 4, 1, 15, llvm::Triple::x86, ArchSpec::eCore_x86_32_i486, 198 "i486"}, 199 {eByteOrderLittle, 4, 1, 15, llvm::Triple::x86, 200 ArchSpec::eCore_x86_32_i486sx, "i486sx"}, 201 {eByteOrderLittle, 4, 1, 15, llvm::Triple::x86, ArchSpec::eCore_x86_32_i686, 202 "i686"}, 203 204 {eByteOrderLittle, 8, 1, 15, llvm::Triple::x86_64, 205 ArchSpec::eCore_x86_64_x86_64, "x86_64"}, 206 {eByteOrderLittle, 8, 1, 15, llvm::Triple::x86_64, 207 ArchSpec::eCore_x86_64_x86_64h, "x86_64h"}, 208 {eByteOrderLittle, 8, 1, 15, llvm::Triple::x86_64, 209 ArchSpec::eCore_x86_64_amd64, "amd64"}, 210 {eByteOrderLittle, 4, 4, 4, llvm::Triple::hexagon, 211 ArchSpec::eCore_hexagon_generic, "hexagon"}, 212 {eByteOrderLittle, 4, 4, 4, llvm::Triple::hexagon, 213 ArchSpec::eCore_hexagon_hexagonv4, "hexagonv4"}, 214 {eByteOrderLittle, 4, 4, 4, llvm::Triple::hexagon, 215 ArchSpec::eCore_hexagon_hexagonv5, "hexagonv5"}, 216 217 {eByteOrderLittle, 4, 4, 4, llvm::Triple::UnknownArch, 218 ArchSpec::eCore_uknownMach32, "unknown-mach-32"}, 219 {eByteOrderLittle, 8, 4, 4, llvm::Triple::UnknownArch, 220 ArchSpec::eCore_uknownMach64, "unknown-mach-64"}, 221 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arc, ArchSpec::eCore_arc, "arc"} 222 }; 223 224 // Ensure that we have an entry in the g_core_definitions for each core. If you 225 // comment out an entry above, you will need to comment out the corresponding 226 // ArchSpec::Core enumeration. 227 static_assert(sizeof(g_core_definitions) / sizeof(CoreDefinition) == 228 ArchSpec::kNumCores, 229 "make sure we have one core definition for each core"); 230 231 struct ArchDefinitionEntry { 232 ArchSpec::Core core; 233 uint32_t cpu; 234 uint32_t sub; 235 uint32_t cpu_mask; 236 uint32_t sub_mask; 237 }; 238 239 struct ArchDefinition { 240 ArchitectureType type; 241 size_t num_entries; 242 const ArchDefinitionEntry *entries; 243 const char *name; 244 }; 245 246 void ArchSpec::ListSupportedArchNames(StringList &list) { 247 for (uint32_t i = 0; i < llvm::array_lengthof(g_core_definitions); ++i) 248 list.AppendString(g_core_definitions[i].name); 249 } 250 251 void ArchSpec::AutoComplete(CompletionRequest &request) { 252 for (uint32_t i = 0; i < llvm::array_lengthof(g_core_definitions); ++i) 253 request.TryCompleteCurrentArg(g_core_definitions[i].name); 254 } 255 256 #define CPU_ANY (UINT32_MAX) 257 258 //===----------------------------------------------------------------------===// 259 // A table that gets searched linearly for matches. This table is used to 260 // convert cpu type and subtypes to architecture names, and to convert 261 // architecture names to cpu types and subtypes. The ordering is important and 262 // allows the precedence to be set when the table is built. 263 #define SUBTYPE_MASK 0x00FFFFFFu 264 265 static const ArchDefinitionEntry g_macho_arch_entries[] = { 266 {ArchSpec::eCore_arm_generic, llvm::MachO::CPU_TYPE_ARM, CPU_ANY, 267 UINT32_MAX, UINT32_MAX}, 268 {ArchSpec::eCore_arm_generic, llvm::MachO::CPU_TYPE_ARM, 0, UINT32_MAX, 269 SUBTYPE_MASK}, 270 {ArchSpec::eCore_arm_armv4, llvm::MachO::CPU_TYPE_ARM, 5, UINT32_MAX, 271 SUBTYPE_MASK}, 272 {ArchSpec::eCore_arm_armv4t, llvm::MachO::CPU_TYPE_ARM, 5, UINT32_MAX, 273 SUBTYPE_MASK}, 274 {ArchSpec::eCore_arm_armv6, llvm::MachO::CPU_TYPE_ARM, 6, UINT32_MAX, 275 SUBTYPE_MASK}, 276 {ArchSpec::eCore_arm_armv6m, llvm::MachO::CPU_TYPE_ARM, 14, UINT32_MAX, 277 SUBTYPE_MASK}, 278 {ArchSpec::eCore_arm_armv5, llvm::MachO::CPU_TYPE_ARM, 7, UINT32_MAX, 279 SUBTYPE_MASK}, 280 {ArchSpec::eCore_arm_armv5e, llvm::MachO::CPU_TYPE_ARM, 7, UINT32_MAX, 281 SUBTYPE_MASK}, 282 {ArchSpec::eCore_arm_armv5t, llvm::MachO::CPU_TYPE_ARM, 7, UINT32_MAX, 283 SUBTYPE_MASK}, 284 {ArchSpec::eCore_arm_xscale, llvm::MachO::CPU_TYPE_ARM, 8, UINT32_MAX, 285 SUBTYPE_MASK}, 286 {ArchSpec::eCore_arm_armv7, llvm::MachO::CPU_TYPE_ARM, 9, UINT32_MAX, 287 SUBTYPE_MASK}, 288 {ArchSpec::eCore_arm_armv7f, llvm::MachO::CPU_TYPE_ARM, 10, UINT32_MAX, 289 SUBTYPE_MASK}, 290 {ArchSpec::eCore_arm_armv7s, llvm::MachO::CPU_TYPE_ARM, 11, UINT32_MAX, 291 SUBTYPE_MASK}, 292 {ArchSpec::eCore_arm_armv7k, llvm::MachO::CPU_TYPE_ARM, 12, UINT32_MAX, 293 SUBTYPE_MASK}, 294 {ArchSpec::eCore_arm_armv7m, llvm::MachO::CPU_TYPE_ARM, 15, UINT32_MAX, 295 SUBTYPE_MASK}, 296 {ArchSpec::eCore_arm_armv7em, llvm::MachO::CPU_TYPE_ARM, 16, UINT32_MAX, 297 SUBTYPE_MASK}, 298 {ArchSpec::eCore_arm_arm64, llvm::MachO::CPU_TYPE_ARM64, 1, UINT32_MAX, 299 SUBTYPE_MASK}, 300 {ArchSpec::eCore_arm_arm64, llvm::MachO::CPU_TYPE_ARM64, 0, UINT32_MAX, 301 SUBTYPE_MASK}, 302 {ArchSpec::eCore_arm_arm64, llvm::MachO::CPU_TYPE_ARM64, 13, UINT32_MAX, 303 SUBTYPE_MASK}, 304 {ArchSpec::eCore_arm_arm64_32, llvm::MachO::CPU_TYPE_ARM64_32, 0, 305 UINT32_MAX, SUBTYPE_MASK}, 306 {ArchSpec::eCore_arm_arm64_32, llvm::MachO::CPU_TYPE_ARM64_32, 1, 307 UINT32_MAX, SUBTYPE_MASK}, 308 {ArchSpec::eCore_arm_arm64, llvm::MachO::CPU_TYPE_ARM64, CPU_ANY, 309 UINT32_MAX, SUBTYPE_MASK}, 310 {ArchSpec::eCore_thumb, llvm::MachO::CPU_TYPE_ARM, 0, UINT32_MAX, 311 SUBTYPE_MASK}, 312 {ArchSpec::eCore_thumbv4t, llvm::MachO::CPU_TYPE_ARM, 5, UINT32_MAX, 313 SUBTYPE_MASK}, 314 {ArchSpec::eCore_thumbv5, llvm::MachO::CPU_TYPE_ARM, 7, UINT32_MAX, 315 SUBTYPE_MASK}, 316 {ArchSpec::eCore_thumbv5e, llvm::MachO::CPU_TYPE_ARM, 7, UINT32_MAX, 317 SUBTYPE_MASK}, 318 {ArchSpec::eCore_thumbv6, llvm::MachO::CPU_TYPE_ARM, 6, UINT32_MAX, 319 SUBTYPE_MASK}, 320 {ArchSpec::eCore_thumbv6m, llvm::MachO::CPU_TYPE_ARM, 14, UINT32_MAX, 321 SUBTYPE_MASK}, 322 {ArchSpec::eCore_thumbv7, llvm::MachO::CPU_TYPE_ARM, 9, UINT32_MAX, 323 SUBTYPE_MASK}, 324 {ArchSpec::eCore_thumbv7f, llvm::MachO::CPU_TYPE_ARM, 10, UINT32_MAX, 325 SUBTYPE_MASK}, 326 {ArchSpec::eCore_thumbv7s, llvm::MachO::CPU_TYPE_ARM, 11, UINT32_MAX, 327 SUBTYPE_MASK}, 328 {ArchSpec::eCore_thumbv7k, llvm::MachO::CPU_TYPE_ARM, 12, UINT32_MAX, 329 SUBTYPE_MASK}, 330 {ArchSpec::eCore_thumbv7m, llvm::MachO::CPU_TYPE_ARM, 15, UINT32_MAX, 331 SUBTYPE_MASK}, 332 {ArchSpec::eCore_thumbv7em, llvm::MachO::CPU_TYPE_ARM, 16, UINT32_MAX, 333 SUBTYPE_MASK}, 334 {ArchSpec::eCore_ppc_generic, llvm::MachO::CPU_TYPE_POWERPC, CPU_ANY, 335 UINT32_MAX, UINT32_MAX}, 336 {ArchSpec::eCore_ppc_generic, llvm::MachO::CPU_TYPE_POWERPC, 0, UINT32_MAX, 337 SUBTYPE_MASK}, 338 {ArchSpec::eCore_ppc_ppc601, llvm::MachO::CPU_TYPE_POWERPC, 1, UINT32_MAX, 339 SUBTYPE_MASK}, 340 {ArchSpec::eCore_ppc_ppc602, llvm::MachO::CPU_TYPE_POWERPC, 2, UINT32_MAX, 341 SUBTYPE_MASK}, 342 {ArchSpec::eCore_ppc_ppc603, llvm::MachO::CPU_TYPE_POWERPC, 3, UINT32_MAX, 343 SUBTYPE_MASK}, 344 {ArchSpec::eCore_ppc_ppc603e, llvm::MachO::CPU_TYPE_POWERPC, 4, UINT32_MAX, 345 SUBTYPE_MASK}, 346 {ArchSpec::eCore_ppc_ppc603ev, llvm::MachO::CPU_TYPE_POWERPC, 5, UINT32_MAX, 347 SUBTYPE_MASK}, 348 {ArchSpec::eCore_ppc_ppc604, llvm::MachO::CPU_TYPE_POWERPC, 6, UINT32_MAX, 349 SUBTYPE_MASK}, 350 {ArchSpec::eCore_ppc_ppc604e, llvm::MachO::CPU_TYPE_POWERPC, 7, UINT32_MAX, 351 SUBTYPE_MASK}, 352 {ArchSpec::eCore_ppc_ppc620, llvm::MachO::CPU_TYPE_POWERPC, 8, UINT32_MAX, 353 SUBTYPE_MASK}, 354 {ArchSpec::eCore_ppc_ppc750, llvm::MachO::CPU_TYPE_POWERPC, 9, UINT32_MAX, 355 SUBTYPE_MASK}, 356 {ArchSpec::eCore_ppc_ppc7400, llvm::MachO::CPU_TYPE_POWERPC, 10, UINT32_MAX, 357 SUBTYPE_MASK}, 358 {ArchSpec::eCore_ppc_ppc7450, llvm::MachO::CPU_TYPE_POWERPC, 11, UINT32_MAX, 359 SUBTYPE_MASK}, 360 {ArchSpec::eCore_ppc_ppc970, llvm::MachO::CPU_TYPE_POWERPC, 100, UINT32_MAX, 361 SUBTYPE_MASK}, 362 {ArchSpec::eCore_ppc64_generic, llvm::MachO::CPU_TYPE_POWERPC64, 0, 363 UINT32_MAX, SUBTYPE_MASK}, 364 {ArchSpec::eCore_ppc64le_generic, llvm::MachO::CPU_TYPE_POWERPC64, CPU_ANY, 365 UINT32_MAX, SUBTYPE_MASK}, 366 {ArchSpec::eCore_ppc64_ppc970_64, llvm::MachO::CPU_TYPE_POWERPC64, 100, 367 UINT32_MAX, SUBTYPE_MASK}, 368 {ArchSpec::eCore_x86_32_i386, llvm::MachO::CPU_TYPE_I386, 3, UINT32_MAX, 369 SUBTYPE_MASK}, 370 {ArchSpec::eCore_x86_32_i486, llvm::MachO::CPU_TYPE_I386, 4, UINT32_MAX, 371 SUBTYPE_MASK}, 372 {ArchSpec::eCore_x86_32_i486sx, llvm::MachO::CPU_TYPE_I386, 0x84, 373 UINT32_MAX, SUBTYPE_MASK}, 374 {ArchSpec::eCore_x86_32_i386, llvm::MachO::CPU_TYPE_I386, CPU_ANY, 375 UINT32_MAX, UINT32_MAX}, 376 {ArchSpec::eCore_x86_64_x86_64, llvm::MachO::CPU_TYPE_X86_64, 3, UINT32_MAX, 377 SUBTYPE_MASK}, 378 {ArchSpec::eCore_x86_64_x86_64, llvm::MachO::CPU_TYPE_X86_64, 4, UINT32_MAX, 379 SUBTYPE_MASK}, 380 {ArchSpec::eCore_x86_64_x86_64h, llvm::MachO::CPU_TYPE_X86_64, 8, 381 UINT32_MAX, SUBTYPE_MASK}, 382 {ArchSpec::eCore_x86_64_x86_64, llvm::MachO::CPU_TYPE_X86_64, CPU_ANY, 383 UINT32_MAX, UINT32_MAX}, 384 // Catch any unknown mach architectures so we can always use the object and 385 // symbol mach-o files 386 {ArchSpec::eCore_uknownMach32, 0, 0, 0xFF000000u, 0x00000000u}, 387 {ArchSpec::eCore_uknownMach64, llvm::MachO::CPU_ARCH_ABI64, 0, 0xFF000000u, 388 0x00000000u}}; 389 390 static const ArchDefinition g_macho_arch_def = { 391 eArchTypeMachO, llvm::array_lengthof(g_macho_arch_entries), 392 g_macho_arch_entries, "mach-o"}; 393 394 //===----------------------------------------------------------------------===// 395 // A table that gets searched linearly for matches. This table is used to 396 // convert cpu type and subtypes to architecture names, and to convert 397 // architecture names to cpu types and subtypes. The ordering is important and 398 // allows the precedence to be set when the table is built. 399 static const ArchDefinitionEntry g_elf_arch_entries[] = { 400 {ArchSpec::eCore_sparc_generic, llvm::ELF::EM_SPARC, LLDB_INVALID_CPUTYPE, 401 0xFFFFFFFFu, 0xFFFFFFFFu}, // Sparc 402 {ArchSpec::eCore_x86_32_i386, llvm::ELF::EM_386, LLDB_INVALID_CPUTYPE, 403 0xFFFFFFFFu, 0xFFFFFFFFu}, // Intel 80386 404 {ArchSpec::eCore_x86_32_i486, llvm::ELF::EM_IAMCU, LLDB_INVALID_CPUTYPE, 405 0xFFFFFFFFu, 0xFFFFFFFFu}, // Intel MCU // FIXME: is this correct? 406 {ArchSpec::eCore_ppc_generic, llvm::ELF::EM_PPC, LLDB_INVALID_CPUTYPE, 407 0xFFFFFFFFu, 0xFFFFFFFFu}, // PowerPC 408 {ArchSpec::eCore_ppc64le_generic, llvm::ELF::EM_PPC64, LLDB_INVALID_CPUTYPE, 409 0xFFFFFFFFu, 0xFFFFFFFFu}, // PowerPC64le 410 {ArchSpec::eCore_ppc64_generic, llvm::ELF::EM_PPC64, LLDB_INVALID_CPUTYPE, 411 0xFFFFFFFFu, 0xFFFFFFFFu}, // PowerPC64 412 {ArchSpec::eCore_arm_generic, llvm::ELF::EM_ARM, LLDB_INVALID_CPUTYPE, 413 0xFFFFFFFFu, 0xFFFFFFFFu}, // ARM 414 {ArchSpec::eCore_arm_aarch64, llvm::ELF::EM_AARCH64, LLDB_INVALID_CPUTYPE, 415 0xFFFFFFFFu, 0xFFFFFFFFu}, // ARM64 416 {ArchSpec::eCore_s390x_generic, llvm::ELF::EM_S390, LLDB_INVALID_CPUTYPE, 417 0xFFFFFFFFu, 0xFFFFFFFFu}, // SystemZ 418 {ArchSpec::eCore_sparc9_generic, llvm::ELF::EM_SPARCV9, 419 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // SPARC V9 420 {ArchSpec::eCore_x86_64_x86_64, llvm::ELF::EM_X86_64, LLDB_INVALID_CPUTYPE, 421 0xFFFFFFFFu, 0xFFFFFFFFu}, // AMD64 422 {ArchSpec::eCore_mips32, llvm::ELF::EM_MIPS, ArchSpec::eMIPSSubType_mips32, 423 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32 424 {ArchSpec::eCore_mips32r2, llvm::ELF::EM_MIPS, 425 ArchSpec::eMIPSSubType_mips32r2, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32r2 426 {ArchSpec::eCore_mips32r6, llvm::ELF::EM_MIPS, 427 ArchSpec::eMIPSSubType_mips32r6, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32r6 428 {ArchSpec::eCore_mips32el, llvm::ELF::EM_MIPS, 429 ArchSpec::eMIPSSubType_mips32el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32el 430 {ArchSpec::eCore_mips32r2el, llvm::ELF::EM_MIPS, 431 ArchSpec::eMIPSSubType_mips32r2el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32r2el 432 {ArchSpec::eCore_mips32r6el, llvm::ELF::EM_MIPS, 433 ArchSpec::eMIPSSubType_mips32r6el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32r6el 434 {ArchSpec::eCore_mips64, llvm::ELF::EM_MIPS, ArchSpec::eMIPSSubType_mips64, 435 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64 436 {ArchSpec::eCore_mips64r2, llvm::ELF::EM_MIPS, 437 ArchSpec::eMIPSSubType_mips64r2, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64r2 438 {ArchSpec::eCore_mips64r6, llvm::ELF::EM_MIPS, 439 ArchSpec::eMIPSSubType_mips64r6, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64r6 440 {ArchSpec::eCore_mips64el, llvm::ELF::EM_MIPS, 441 ArchSpec::eMIPSSubType_mips64el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64el 442 {ArchSpec::eCore_mips64r2el, llvm::ELF::EM_MIPS, 443 ArchSpec::eMIPSSubType_mips64r2el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64r2el 444 {ArchSpec::eCore_mips64r6el, llvm::ELF::EM_MIPS, 445 ArchSpec::eMIPSSubType_mips64r6el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64r6el 446 {ArchSpec::eCore_hexagon_generic, llvm::ELF::EM_HEXAGON, 447 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // HEXAGON 448 {ArchSpec::eCore_arc, llvm::ELF::EM_ARC_COMPACT2, LLDB_INVALID_CPUTYPE, 449 0xFFFFFFFFu, 0xFFFFFFFFu}, // ARC 450 }; 451 452 static const ArchDefinition g_elf_arch_def = { 453 eArchTypeELF, 454 llvm::array_lengthof(g_elf_arch_entries), 455 g_elf_arch_entries, 456 "elf", 457 }; 458 459 static const ArchDefinitionEntry g_coff_arch_entries[] = { 460 {ArchSpec::eCore_x86_32_i386, llvm::COFF::IMAGE_FILE_MACHINE_I386, 461 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // Intel 80x86 462 {ArchSpec::eCore_ppc_generic, llvm::COFF::IMAGE_FILE_MACHINE_POWERPC, 463 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // PowerPC 464 {ArchSpec::eCore_ppc_generic, llvm::COFF::IMAGE_FILE_MACHINE_POWERPCFP, 465 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // PowerPC (with FPU) 466 {ArchSpec::eCore_arm_generic, llvm::COFF::IMAGE_FILE_MACHINE_ARM, 467 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // ARM 468 {ArchSpec::eCore_arm_armv7, llvm::COFF::IMAGE_FILE_MACHINE_ARMNT, 469 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // ARMv7 470 {ArchSpec::eCore_thumb, llvm::COFF::IMAGE_FILE_MACHINE_THUMB, 471 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // ARMv7 472 {ArchSpec::eCore_x86_64_x86_64, llvm::COFF::IMAGE_FILE_MACHINE_AMD64, 473 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // AMD64 474 {ArchSpec::eCore_arm_arm64, llvm::COFF::IMAGE_FILE_MACHINE_ARM64, 475 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu} // ARM64 476 }; 477 478 static const ArchDefinition g_coff_arch_def = { 479 eArchTypeCOFF, 480 llvm::array_lengthof(g_coff_arch_entries), 481 g_coff_arch_entries, 482 "pe-coff", 483 }; 484 485 //===----------------------------------------------------------------------===// 486 // Table of all ArchDefinitions 487 static const ArchDefinition *g_arch_definitions[] = { 488 &g_macho_arch_def, &g_elf_arch_def, &g_coff_arch_def}; 489 490 static const size_t k_num_arch_definitions = 491 llvm::array_lengthof(g_arch_definitions); 492 493 //===----------------------------------------------------------------------===// 494 // Static helper functions. 495 496 // Get the architecture definition for a given object type. 497 static const ArchDefinition *FindArchDefinition(ArchitectureType arch_type) { 498 for (unsigned int i = 0; i < k_num_arch_definitions; ++i) { 499 const ArchDefinition *def = g_arch_definitions[i]; 500 if (def->type == arch_type) 501 return def; 502 } 503 return nullptr; 504 } 505 506 // Get an architecture definition by name. 507 static const CoreDefinition *FindCoreDefinition(llvm::StringRef name) { 508 for (unsigned int i = 0; i < llvm::array_lengthof(g_core_definitions); ++i) { 509 if (name.equals_lower(g_core_definitions[i].name)) 510 return &g_core_definitions[i]; 511 } 512 return nullptr; 513 } 514 515 static inline const CoreDefinition *FindCoreDefinition(ArchSpec::Core core) { 516 if (core < llvm::array_lengthof(g_core_definitions)) 517 return &g_core_definitions[core]; 518 return nullptr; 519 } 520 521 // Get a definition entry by cpu type and subtype. 522 static const ArchDefinitionEntry * 523 FindArchDefinitionEntry(const ArchDefinition *def, uint32_t cpu, uint32_t sub) { 524 if (def == nullptr) 525 return nullptr; 526 527 const ArchDefinitionEntry *entries = def->entries; 528 for (size_t i = 0; i < def->num_entries; ++i) { 529 if (entries[i].cpu == (cpu & entries[i].cpu_mask)) 530 if (entries[i].sub == (sub & entries[i].sub_mask)) 531 return &entries[i]; 532 } 533 return nullptr; 534 } 535 536 static const ArchDefinitionEntry * 537 FindArchDefinitionEntry(const ArchDefinition *def, ArchSpec::Core core) { 538 if (def == nullptr) 539 return nullptr; 540 541 const ArchDefinitionEntry *entries = def->entries; 542 for (size_t i = 0; i < def->num_entries; ++i) { 543 if (entries[i].core == core) 544 return &entries[i]; 545 } 546 return nullptr; 547 } 548 549 //===----------------------------------------------------------------------===// 550 // Constructors and destructors. 551 552 ArchSpec::ArchSpec() {} 553 554 ArchSpec::ArchSpec(const char *triple_cstr) { 555 if (triple_cstr) 556 SetTriple(triple_cstr); 557 } 558 559 ArchSpec::ArchSpec(llvm::StringRef triple_str) { SetTriple(triple_str); } 560 561 ArchSpec::ArchSpec(const llvm::Triple &triple) { SetTriple(triple); } 562 563 ArchSpec::ArchSpec(ArchitectureType arch_type, uint32_t cpu, uint32_t subtype) { 564 SetArchitecture(arch_type, cpu, subtype); 565 } 566 567 ArchSpec::~ArchSpec() = default; 568 569 void ArchSpec::Clear() { 570 m_triple = llvm::Triple(); 571 m_core = kCore_invalid; 572 m_byte_order = eByteOrderInvalid; 573 m_distribution_id.Clear(); 574 m_flags = 0; 575 } 576 577 //===----------------------------------------------------------------------===// 578 // Predicates. 579 580 const char *ArchSpec::GetArchitectureName() const { 581 const CoreDefinition *core_def = FindCoreDefinition(m_core); 582 if (core_def) 583 return core_def->name; 584 return "unknown"; 585 } 586 587 bool ArchSpec::IsMIPS() const { return GetTriple().isMIPS(); } 588 589 std::string ArchSpec::GetTargetABI() const { 590 591 std::string abi; 592 593 if (IsMIPS()) { 594 switch (GetFlags() & ArchSpec::eMIPSABI_mask) { 595 case ArchSpec::eMIPSABI_N64: 596 abi = "n64"; 597 return abi; 598 case ArchSpec::eMIPSABI_N32: 599 abi = "n32"; 600 return abi; 601 case ArchSpec::eMIPSABI_O32: 602 abi = "o32"; 603 return abi; 604 default: 605 return abi; 606 } 607 } 608 return abi; 609 } 610 611 void ArchSpec::SetFlags(std::string elf_abi) { 612 613 uint32_t flag = GetFlags(); 614 if (IsMIPS()) { 615 if (elf_abi == "n64") 616 flag |= ArchSpec::eMIPSABI_N64; 617 else if (elf_abi == "n32") 618 flag |= ArchSpec::eMIPSABI_N32; 619 else if (elf_abi == "o32") 620 flag |= ArchSpec::eMIPSABI_O32; 621 } 622 SetFlags(flag); 623 } 624 625 std::string ArchSpec::GetClangTargetCPU() const { 626 std::string cpu; 627 628 if (IsMIPS()) { 629 switch (m_core) { 630 case ArchSpec::eCore_mips32: 631 case ArchSpec::eCore_mips32el: 632 cpu = "mips32"; 633 break; 634 case ArchSpec::eCore_mips32r2: 635 case ArchSpec::eCore_mips32r2el: 636 cpu = "mips32r2"; 637 break; 638 case ArchSpec::eCore_mips32r3: 639 case ArchSpec::eCore_mips32r3el: 640 cpu = "mips32r3"; 641 break; 642 case ArchSpec::eCore_mips32r5: 643 case ArchSpec::eCore_mips32r5el: 644 cpu = "mips32r5"; 645 break; 646 case ArchSpec::eCore_mips32r6: 647 case ArchSpec::eCore_mips32r6el: 648 cpu = "mips32r6"; 649 break; 650 case ArchSpec::eCore_mips64: 651 case ArchSpec::eCore_mips64el: 652 cpu = "mips64"; 653 break; 654 case ArchSpec::eCore_mips64r2: 655 case ArchSpec::eCore_mips64r2el: 656 cpu = "mips64r2"; 657 break; 658 case ArchSpec::eCore_mips64r3: 659 case ArchSpec::eCore_mips64r3el: 660 cpu = "mips64r3"; 661 break; 662 case ArchSpec::eCore_mips64r5: 663 case ArchSpec::eCore_mips64r5el: 664 cpu = "mips64r5"; 665 break; 666 case ArchSpec::eCore_mips64r6: 667 case ArchSpec::eCore_mips64r6el: 668 cpu = "mips64r6"; 669 break; 670 default: 671 break; 672 } 673 } 674 return cpu; 675 } 676 677 uint32_t ArchSpec::GetMachOCPUType() const { 678 const CoreDefinition *core_def = FindCoreDefinition(m_core); 679 if (core_def) { 680 const ArchDefinitionEntry *arch_def = 681 FindArchDefinitionEntry(&g_macho_arch_def, core_def->core); 682 if (arch_def) { 683 return arch_def->cpu; 684 } 685 } 686 return LLDB_INVALID_CPUTYPE; 687 } 688 689 uint32_t ArchSpec::GetMachOCPUSubType() const { 690 const CoreDefinition *core_def = FindCoreDefinition(m_core); 691 if (core_def) { 692 const ArchDefinitionEntry *arch_def = 693 FindArchDefinitionEntry(&g_macho_arch_def, core_def->core); 694 if (arch_def) { 695 return arch_def->sub; 696 } 697 } 698 return LLDB_INVALID_CPUTYPE; 699 } 700 701 uint32_t ArchSpec::GetDataByteSize() const { 702 return 1; 703 } 704 705 uint32_t ArchSpec::GetCodeByteSize() const { 706 return 1; 707 } 708 709 llvm::Triple::ArchType ArchSpec::GetMachine() const { 710 const CoreDefinition *core_def = FindCoreDefinition(m_core); 711 if (core_def) 712 return core_def->machine; 713 714 return llvm::Triple::UnknownArch; 715 } 716 717 ConstString ArchSpec::GetDistributionId() const { 718 return m_distribution_id; 719 } 720 721 void ArchSpec::SetDistributionId(const char *distribution_id) { 722 m_distribution_id.SetCString(distribution_id); 723 } 724 725 uint32_t ArchSpec::GetAddressByteSize() const { 726 const CoreDefinition *core_def = FindCoreDefinition(m_core); 727 if (core_def) { 728 if (core_def->machine == llvm::Triple::mips64 || 729 core_def->machine == llvm::Triple::mips64el) { 730 // For N32/O32 applications Address size is 4 bytes. 731 if (m_flags & (eMIPSABI_N32 | eMIPSABI_O32)) 732 return 4; 733 } 734 return core_def->addr_byte_size; 735 } 736 return 0; 737 } 738 739 ByteOrder ArchSpec::GetDefaultEndian() const { 740 const CoreDefinition *core_def = FindCoreDefinition(m_core); 741 if (core_def) 742 return core_def->default_byte_order; 743 return eByteOrderInvalid; 744 } 745 746 bool ArchSpec::CharIsSignedByDefault() const { 747 switch (m_triple.getArch()) { 748 default: 749 return true; 750 751 case llvm::Triple::aarch64: 752 case llvm::Triple::aarch64_32: 753 case llvm::Triple::aarch64_be: 754 case llvm::Triple::arm: 755 case llvm::Triple::armeb: 756 case llvm::Triple::thumb: 757 case llvm::Triple::thumbeb: 758 return m_triple.isOSDarwin() || m_triple.isOSWindows(); 759 760 case llvm::Triple::ppc: 761 case llvm::Triple::ppc64: 762 return m_triple.isOSDarwin(); 763 764 case llvm::Triple::ppc64le: 765 case llvm::Triple::systemz: 766 case llvm::Triple::xcore: 767 case llvm::Triple::arc: 768 return false; 769 } 770 } 771 772 lldb::ByteOrder ArchSpec::GetByteOrder() const { 773 if (m_byte_order == eByteOrderInvalid) 774 return GetDefaultEndian(); 775 return m_byte_order; 776 } 777 778 //===----------------------------------------------------------------------===// 779 // Mutators. 780 781 bool ArchSpec::SetTriple(const llvm::Triple &triple) { 782 m_triple = triple; 783 UpdateCore(); 784 return IsValid(); 785 } 786 787 bool lldb_private::ParseMachCPUDashSubtypeTriple(llvm::StringRef triple_str, 788 ArchSpec &arch) { 789 // Accept "12-10" or "12.10" as cpu type/subtype 790 if (triple_str.empty()) 791 return false; 792 793 size_t pos = triple_str.find_first_of("-."); 794 if (pos == llvm::StringRef::npos) 795 return false; 796 797 llvm::StringRef cpu_str = triple_str.substr(0, pos); 798 llvm::StringRef remainder = triple_str.substr(pos + 1); 799 if (cpu_str.empty() || remainder.empty()) 800 return false; 801 802 llvm::StringRef sub_str; 803 llvm::StringRef vendor; 804 llvm::StringRef os; 805 std::tie(sub_str, remainder) = remainder.split('-'); 806 std::tie(vendor, os) = remainder.split('-'); 807 808 uint32_t cpu = 0; 809 uint32_t sub = 0; 810 if (cpu_str.getAsInteger(10, cpu) || sub_str.getAsInteger(10, sub)) 811 return false; 812 813 if (!arch.SetArchitecture(eArchTypeMachO, cpu, sub)) 814 return false; 815 if (!vendor.empty() && !os.empty()) { 816 arch.GetTriple().setVendorName(vendor); 817 arch.GetTriple().setOSName(os); 818 } 819 820 return true; 821 } 822 823 bool ArchSpec::SetTriple(llvm::StringRef triple) { 824 if (triple.empty()) { 825 Clear(); 826 return false; 827 } 828 829 if (ParseMachCPUDashSubtypeTriple(triple, *this)) 830 return true; 831 832 SetTriple(llvm::Triple(llvm::Triple::normalize(triple))); 833 return IsValid(); 834 } 835 836 bool ArchSpec::ContainsOnlyArch(const llvm::Triple &normalized_triple) { 837 return !normalized_triple.getArchName().empty() && 838 normalized_triple.getOSName().empty() && 839 normalized_triple.getVendorName().empty() && 840 normalized_triple.getEnvironmentName().empty(); 841 } 842 843 void ArchSpec::MergeFrom(const ArchSpec &other) { 844 if (!TripleVendorWasSpecified() && other.TripleVendorWasSpecified()) 845 GetTriple().setVendor(other.GetTriple().getVendor()); 846 if (!TripleOSWasSpecified() && other.TripleOSWasSpecified()) 847 GetTriple().setOS(other.GetTriple().getOS()); 848 if (GetTriple().getArch() == llvm::Triple::UnknownArch) { 849 GetTriple().setArch(other.GetTriple().getArch()); 850 851 // MachO unknown64 isn't really invalid as the debugger can still obtain 852 // information from the binary, e.g. line tables. As such, we don't update 853 // the core here. 854 if (other.GetCore() != eCore_uknownMach64) 855 UpdateCore(); 856 } 857 if (!TripleEnvironmentWasSpecified() && 858 other.TripleEnvironmentWasSpecified()) { 859 GetTriple().setEnvironment(other.GetTriple().getEnvironment()); 860 } 861 // If this and other are both arm ArchSpecs and this ArchSpec is a generic 862 // "some kind of arm" spec but the other ArchSpec is a specific arm core, 863 // adopt the specific arm core. 864 if (GetTriple().getArch() == llvm::Triple::arm && 865 other.GetTriple().getArch() == llvm::Triple::arm && 866 IsCompatibleMatch(other) && GetCore() == ArchSpec::eCore_arm_generic && 867 other.GetCore() != ArchSpec::eCore_arm_generic) { 868 m_core = other.GetCore(); 869 CoreUpdated(false); 870 } 871 if (GetFlags() == 0) { 872 SetFlags(other.GetFlags()); 873 } 874 } 875 876 bool ArchSpec::SetArchitecture(ArchitectureType arch_type, uint32_t cpu, 877 uint32_t sub, uint32_t os) { 878 m_core = kCore_invalid; 879 bool update_triple = true; 880 const ArchDefinition *arch_def = FindArchDefinition(arch_type); 881 if (arch_def) { 882 const ArchDefinitionEntry *arch_def_entry = 883 FindArchDefinitionEntry(arch_def, cpu, sub); 884 if (arch_def_entry) { 885 const CoreDefinition *core_def = FindCoreDefinition(arch_def_entry->core); 886 if (core_def) { 887 m_core = core_def->core; 888 update_triple = false; 889 // Always use the architecture name because it might be more 890 // descriptive than the architecture enum ("armv7" -> 891 // llvm::Triple::arm). 892 m_triple.setArchName(llvm::StringRef(core_def->name)); 893 if (arch_type == eArchTypeMachO) { 894 m_triple.setVendor(llvm::Triple::Apple); 895 896 // Don't set the OS. It could be simulator, macosx, ios, watchos, 897 // tvos, bridgeos. We could get close with the cpu type - but we 898 // can't get it right all of the time. Better to leave this unset 899 // so other sections of code will set it when they have more 900 // information. NB: don't call m_triple.setOS 901 // (llvm::Triple::UnknownOS). That sets the OSName to "unknown" and 902 // the ArchSpec::TripleVendorWasSpecified() method says that any 903 // OSName setting means it was specified. 904 } else if (arch_type == eArchTypeELF) { 905 switch (os) { 906 case llvm::ELF::ELFOSABI_AIX: 907 m_triple.setOS(llvm::Triple::OSType::AIX); 908 break; 909 case llvm::ELF::ELFOSABI_FREEBSD: 910 m_triple.setOS(llvm::Triple::OSType::FreeBSD); 911 break; 912 case llvm::ELF::ELFOSABI_GNU: 913 m_triple.setOS(llvm::Triple::OSType::Linux); 914 break; 915 case llvm::ELF::ELFOSABI_NETBSD: 916 m_triple.setOS(llvm::Triple::OSType::NetBSD); 917 break; 918 case llvm::ELF::ELFOSABI_OPENBSD: 919 m_triple.setOS(llvm::Triple::OSType::OpenBSD); 920 break; 921 case llvm::ELF::ELFOSABI_SOLARIS: 922 m_triple.setOS(llvm::Triple::OSType::Solaris); 923 break; 924 } 925 } else if (arch_type == eArchTypeCOFF && os == llvm::Triple::Win32) { 926 m_triple.setVendor(llvm::Triple::PC); 927 m_triple.setOS(llvm::Triple::Win32); 928 } else { 929 m_triple.setVendor(llvm::Triple::UnknownVendor); 930 m_triple.setOS(llvm::Triple::UnknownOS); 931 } 932 // Fall back onto setting the machine type if the arch by name 933 // failed... 934 if (m_triple.getArch() == llvm::Triple::UnknownArch) 935 m_triple.setArch(core_def->machine); 936 } 937 } else { 938 Log *log(lldb_private::GetLogIfAnyCategoriesSet(LIBLLDB_LOG_TARGET | LIBLLDB_LOG_PROCESS | LIBLLDB_LOG_PLATFORM)); 939 LLDB_LOGF(log, 940 "Unable to find a core definition for cpu 0x%" PRIx32 941 " sub %" PRId32, 942 cpu, sub); 943 } 944 } 945 CoreUpdated(update_triple); 946 return IsValid(); 947 } 948 949 uint32_t ArchSpec::GetMinimumOpcodeByteSize() const { 950 const CoreDefinition *core_def = FindCoreDefinition(m_core); 951 if (core_def) 952 return core_def->min_opcode_byte_size; 953 return 0; 954 } 955 956 uint32_t ArchSpec::GetMaximumOpcodeByteSize() const { 957 const CoreDefinition *core_def = FindCoreDefinition(m_core); 958 if (core_def) 959 return core_def->max_opcode_byte_size; 960 return 0; 961 } 962 963 bool ArchSpec::IsExactMatch(const ArchSpec &rhs) const { 964 return IsEqualTo(rhs, true); 965 } 966 967 bool ArchSpec::IsCompatibleMatch(const ArchSpec &rhs) const { 968 return IsEqualTo(rhs, false); 969 } 970 971 static bool IsCompatibleEnvironment(llvm::Triple::EnvironmentType lhs, 972 llvm::Triple::EnvironmentType rhs) { 973 if (lhs == rhs) 974 return true; 975 976 // If any of the environment is unknown then they are compatible 977 if (lhs == llvm::Triple::UnknownEnvironment || 978 rhs == llvm::Triple::UnknownEnvironment) 979 return true; 980 981 // If one of the environment is Android and the other one is EABI then they 982 // are considered to be compatible. This is required as a workaround for 983 // shared libraries compiled for Android without the NOTE section indicating 984 // that they are using the Android ABI. 985 if ((lhs == llvm::Triple::Android && rhs == llvm::Triple::EABI) || 986 (rhs == llvm::Triple::Android && lhs == llvm::Triple::EABI) || 987 (lhs == llvm::Triple::GNUEABI && rhs == llvm::Triple::EABI) || 988 (rhs == llvm::Triple::GNUEABI && lhs == llvm::Triple::EABI) || 989 (lhs == llvm::Triple::GNUEABIHF && rhs == llvm::Triple::EABIHF) || 990 (rhs == llvm::Triple::GNUEABIHF && lhs == llvm::Triple::EABIHF)) 991 return true; 992 993 return false; 994 } 995 996 bool ArchSpec::IsEqualTo(const ArchSpec &rhs, bool exact_match) const { 997 // explicitly ignoring m_distribution_id in this method. 998 999 if (GetByteOrder() != rhs.GetByteOrder()) 1000 return false; 1001 1002 const ArchSpec::Core lhs_core = GetCore(); 1003 const ArchSpec::Core rhs_core = rhs.GetCore(); 1004 1005 const bool core_match = cores_match(lhs_core, rhs_core, true, exact_match); 1006 1007 if (core_match) { 1008 const llvm::Triple &lhs_triple = GetTriple(); 1009 const llvm::Triple &rhs_triple = rhs.GetTriple(); 1010 1011 const llvm::Triple::VendorType lhs_triple_vendor = lhs_triple.getVendor(); 1012 const llvm::Triple::VendorType rhs_triple_vendor = rhs_triple.getVendor(); 1013 if (lhs_triple_vendor != rhs_triple_vendor) { 1014 const bool rhs_vendor_specified = rhs.TripleVendorWasSpecified(); 1015 const bool lhs_vendor_specified = TripleVendorWasSpecified(); 1016 // Both architectures had the vendor specified, so if they aren't equal 1017 // then we return false 1018 if (rhs_vendor_specified && lhs_vendor_specified) 1019 return false; 1020 1021 // Only fail if both vendor types are not unknown 1022 if (lhs_triple_vendor != llvm::Triple::UnknownVendor && 1023 rhs_triple_vendor != llvm::Triple::UnknownVendor) 1024 return false; 1025 } 1026 1027 const llvm::Triple::OSType lhs_triple_os = lhs_triple.getOS(); 1028 const llvm::Triple::OSType rhs_triple_os = rhs_triple.getOS(); 1029 if (lhs_triple_os != rhs_triple_os) { 1030 const bool rhs_os_specified = rhs.TripleOSWasSpecified(); 1031 const bool lhs_os_specified = TripleOSWasSpecified(); 1032 // Both architectures had the OS specified, so if they aren't equal then 1033 // we return false 1034 if (rhs_os_specified && lhs_os_specified) 1035 return false; 1036 1037 // Only fail if both os types are not unknown 1038 if (lhs_triple_os != llvm::Triple::UnknownOS && 1039 rhs_triple_os != llvm::Triple::UnknownOS) 1040 return false; 1041 } 1042 1043 const llvm::Triple::EnvironmentType lhs_triple_env = 1044 lhs_triple.getEnvironment(); 1045 const llvm::Triple::EnvironmentType rhs_triple_env = 1046 rhs_triple.getEnvironment(); 1047 1048 return IsCompatibleEnvironment(lhs_triple_env, rhs_triple_env); 1049 } 1050 return false; 1051 } 1052 1053 void ArchSpec::UpdateCore() { 1054 llvm::StringRef arch_name(m_triple.getArchName()); 1055 const CoreDefinition *core_def = FindCoreDefinition(arch_name); 1056 if (core_def) { 1057 m_core = core_def->core; 1058 // Set the byte order to the default byte order for an architecture. This 1059 // can be modified if needed for cases when cores handle both big and 1060 // little endian 1061 m_byte_order = core_def->default_byte_order; 1062 } else { 1063 Clear(); 1064 } 1065 } 1066 1067 //===----------------------------------------------------------------------===// 1068 // Helper methods. 1069 1070 void ArchSpec::CoreUpdated(bool update_triple) { 1071 const CoreDefinition *core_def = FindCoreDefinition(m_core); 1072 if (core_def) { 1073 if (update_triple) 1074 m_triple = llvm::Triple(core_def->name, "unknown", "unknown"); 1075 m_byte_order = core_def->default_byte_order; 1076 } else { 1077 if (update_triple) 1078 m_triple = llvm::Triple(); 1079 m_byte_order = eByteOrderInvalid; 1080 } 1081 } 1082 1083 //===----------------------------------------------------------------------===// 1084 // Operators. 1085 1086 static bool cores_match(const ArchSpec::Core core1, const ArchSpec::Core core2, 1087 bool try_inverse, bool enforce_exact_match) { 1088 if (core1 == core2) 1089 return true; 1090 1091 switch (core1) { 1092 case ArchSpec::kCore_any: 1093 return true; 1094 1095 case ArchSpec::eCore_arm_generic: 1096 if (enforce_exact_match) 1097 break; 1098 LLVM_FALLTHROUGH; 1099 case ArchSpec::kCore_arm_any: 1100 if (core2 >= ArchSpec::kCore_arm_first && core2 <= ArchSpec::kCore_arm_last) 1101 return true; 1102 if (core2 >= ArchSpec::kCore_thumb_first && 1103 core2 <= ArchSpec::kCore_thumb_last) 1104 return true; 1105 if (core2 == ArchSpec::kCore_arm_any) 1106 return true; 1107 break; 1108 1109 case ArchSpec::kCore_x86_32_any: 1110 if ((core2 >= ArchSpec::kCore_x86_32_first && 1111 core2 <= ArchSpec::kCore_x86_32_last) || 1112 (core2 == ArchSpec::kCore_x86_32_any)) 1113 return true; 1114 break; 1115 1116 case ArchSpec::kCore_x86_64_any: 1117 if ((core2 >= ArchSpec::kCore_x86_64_first && 1118 core2 <= ArchSpec::kCore_x86_64_last) || 1119 (core2 == ArchSpec::kCore_x86_64_any)) 1120 return true; 1121 break; 1122 1123 case ArchSpec::kCore_ppc_any: 1124 if ((core2 >= ArchSpec::kCore_ppc_first && 1125 core2 <= ArchSpec::kCore_ppc_last) || 1126 (core2 == ArchSpec::kCore_ppc_any)) 1127 return true; 1128 break; 1129 1130 case ArchSpec::kCore_ppc64_any: 1131 if ((core2 >= ArchSpec::kCore_ppc64_first && 1132 core2 <= ArchSpec::kCore_ppc64_last) || 1133 (core2 == ArchSpec::kCore_ppc64_any)) 1134 return true; 1135 break; 1136 1137 case ArchSpec::eCore_arm_armv6m: 1138 if (!enforce_exact_match) { 1139 if (core2 == ArchSpec::eCore_arm_generic) 1140 return true; 1141 try_inverse = false; 1142 if (core2 == ArchSpec::eCore_arm_armv7) 1143 return true; 1144 if (core2 == ArchSpec::eCore_arm_armv6m) 1145 return true; 1146 } 1147 break; 1148 1149 case ArchSpec::kCore_hexagon_any: 1150 if ((core2 >= ArchSpec::kCore_hexagon_first && 1151 core2 <= ArchSpec::kCore_hexagon_last) || 1152 (core2 == ArchSpec::kCore_hexagon_any)) 1153 return true; 1154 break; 1155 1156 // v. https://en.wikipedia.org/wiki/ARM_Cortex-M#Silicon_customization 1157 // Cortex-M0 - ARMv6-M - armv6m Cortex-M3 - ARMv7-M - armv7m Cortex-M4 - 1158 // ARMv7E-M - armv7em 1159 case ArchSpec::eCore_arm_armv7em: 1160 if (!enforce_exact_match) { 1161 if (core2 == ArchSpec::eCore_arm_generic) 1162 return true; 1163 if (core2 == ArchSpec::eCore_arm_armv7m) 1164 return true; 1165 if (core2 == ArchSpec::eCore_arm_armv6m) 1166 return true; 1167 if (core2 == ArchSpec::eCore_arm_armv7) 1168 return true; 1169 try_inverse = true; 1170 } 1171 break; 1172 1173 // v. https://en.wikipedia.org/wiki/ARM_Cortex-M#Silicon_customization 1174 // Cortex-M0 - ARMv6-M - armv6m Cortex-M3 - ARMv7-M - armv7m Cortex-M4 - 1175 // ARMv7E-M - armv7em 1176 case ArchSpec::eCore_arm_armv7m: 1177 if (!enforce_exact_match) { 1178 if (core2 == ArchSpec::eCore_arm_generic) 1179 return true; 1180 if (core2 == ArchSpec::eCore_arm_armv6m) 1181 return true; 1182 if (core2 == ArchSpec::eCore_arm_armv7) 1183 return true; 1184 if (core2 == ArchSpec::eCore_arm_armv7em) 1185 return true; 1186 try_inverse = true; 1187 } 1188 break; 1189 1190 case ArchSpec::eCore_arm_armv7f: 1191 case ArchSpec::eCore_arm_armv7k: 1192 case ArchSpec::eCore_arm_armv7s: 1193 case ArchSpec::eCore_arm_armv7l: 1194 case ArchSpec::eCore_arm_armv8l: 1195 if (!enforce_exact_match) { 1196 if (core2 == ArchSpec::eCore_arm_generic) 1197 return true; 1198 if (core2 == ArchSpec::eCore_arm_armv7) 1199 return true; 1200 try_inverse = false; 1201 } 1202 break; 1203 1204 case ArchSpec::eCore_x86_64_x86_64h: 1205 if (!enforce_exact_match) { 1206 if (core2 == ArchSpec::eCore_x86_64_x86_64) 1207 return true; 1208 try_inverse = false; 1209 } 1210 break; 1211 1212 case ArchSpec::eCore_x86_64_amd64: 1213 if (!enforce_exact_match) { 1214 if (core2 == ArchSpec::eCore_x86_64_x86_64) 1215 return true; 1216 try_inverse = false; 1217 } 1218 break; 1219 1220 case ArchSpec::eCore_arm_armv8: 1221 if (!enforce_exact_match) { 1222 if (core2 == ArchSpec::eCore_arm_arm64) 1223 return true; 1224 if (core2 == ArchSpec::eCore_arm_aarch64) 1225 return true; 1226 try_inverse = false; 1227 } 1228 break; 1229 1230 case ArchSpec::eCore_arm_aarch64: 1231 if (!enforce_exact_match) { 1232 if (core2 == ArchSpec::eCore_arm_arm64) 1233 return true; 1234 if (core2 == ArchSpec::eCore_arm_armv8) 1235 return true; 1236 try_inverse = false; 1237 } 1238 break; 1239 1240 case ArchSpec::eCore_arm_arm64: 1241 if (!enforce_exact_match) { 1242 if (core2 == ArchSpec::eCore_arm_aarch64) 1243 return true; 1244 if (core2 == ArchSpec::eCore_arm_armv8) 1245 return true; 1246 try_inverse = false; 1247 } 1248 break; 1249 1250 case ArchSpec::eCore_arm_arm64_32: 1251 if (!enforce_exact_match) { 1252 if (core2 == ArchSpec::eCore_arm_generic) 1253 return true; 1254 try_inverse = false; 1255 } 1256 break; 1257 1258 case ArchSpec::eCore_mips32: 1259 if (!enforce_exact_match) { 1260 if (core2 >= ArchSpec::kCore_mips32_first && 1261 core2 <= ArchSpec::kCore_mips32_last) 1262 return true; 1263 try_inverse = false; 1264 } 1265 break; 1266 1267 case ArchSpec::eCore_mips32el: 1268 if (!enforce_exact_match) { 1269 if (core2 >= ArchSpec::kCore_mips32el_first && 1270 core2 <= ArchSpec::kCore_mips32el_last) 1271 return true; 1272 try_inverse = true; 1273 } 1274 break; 1275 1276 case ArchSpec::eCore_mips64: 1277 if (!enforce_exact_match) { 1278 if (core2 >= ArchSpec::kCore_mips32_first && 1279 core2 <= ArchSpec::kCore_mips32_last) 1280 return true; 1281 if (core2 >= ArchSpec::kCore_mips64_first && 1282 core2 <= ArchSpec::kCore_mips64_last) 1283 return true; 1284 try_inverse = false; 1285 } 1286 break; 1287 1288 case ArchSpec::eCore_mips64el: 1289 if (!enforce_exact_match) { 1290 if (core2 >= ArchSpec::kCore_mips32el_first && 1291 core2 <= ArchSpec::kCore_mips32el_last) 1292 return true; 1293 if (core2 >= ArchSpec::kCore_mips64el_first && 1294 core2 <= ArchSpec::kCore_mips64el_last) 1295 return true; 1296 try_inverse = false; 1297 } 1298 break; 1299 1300 case ArchSpec::eCore_mips64r2: 1301 case ArchSpec::eCore_mips64r3: 1302 case ArchSpec::eCore_mips64r5: 1303 if (!enforce_exact_match) { 1304 if (core2 >= ArchSpec::kCore_mips32_first && core2 <= (core1 - 10)) 1305 return true; 1306 if (core2 >= ArchSpec::kCore_mips64_first && core2 <= (core1 - 1)) 1307 return true; 1308 try_inverse = false; 1309 } 1310 break; 1311 1312 case ArchSpec::eCore_mips64r2el: 1313 case ArchSpec::eCore_mips64r3el: 1314 case ArchSpec::eCore_mips64r5el: 1315 if (!enforce_exact_match) { 1316 if (core2 >= ArchSpec::kCore_mips32el_first && core2 <= (core1 - 10)) 1317 return true; 1318 if (core2 >= ArchSpec::kCore_mips64el_first && core2 <= (core1 - 1)) 1319 return true; 1320 try_inverse = false; 1321 } 1322 break; 1323 1324 case ArchSpec::eCore_mips32r2: 1325 case ArchSpec::eCore_mips32r3: 1326 case ArchSpec::eCore_mips32r5: 1327 if (!enforce_exact_match) { 1328 if (core2 >= ArchSpec::kCore_mips32_first && core2 <= core1) 1329 return true; 1330 } 1331 break; 1332 1333 case ArchSpec::eCore_mips32r2el: 1334 case ArchSpec::eCore_mips32r3el: 1335 case ArchSpec::eCore_mips32r5el: 1336 if (!enforce_exact_match) { 1337 if (core2 >= ArchSpec::kCore_mips32el_first && core2 <= core1) 1338 return true; 1339 } 1340 break; 1341 1342 case ArchSpec::eCore_mips32r6: 1343 if (!enforce_exact_match) { 1344 if (core2 == ArchSpec::eCore_mips32 || core2 == ArchSpec::eCore_mips32r6) 1345 return true; 1346 } 1347 break; 1348 1349 case ArchSpec::eCore_mips32r6el: 1350 if (!enforce_exact_match) { 1351 if (core2 == ArchSpec::eCore_mips32el || 1352 core2 == ArchSpec::eCore_mips32r6el) 1353 return true; 1354 } 1355 break; 1356 1357 case ArchSpec::eCore_mips64r6: 1358 if (!enforce_exact_match) { 1359 if (core2 == ArchSpec::eCore_mips32 || core2 == ArchSpec::eCore_mips32r6) 1360 return true; 1361 if (core2 == ArchSpec::eCore_mips64 || core2 == ArchSpec::eCore_mips64r6) 1362 return true; 1363 } 1364 break; 1365 1366 case ArchSpec::eCore_mips64r6el: 1367 if (!enforce_exact_match) { 1368 if (core2 == ArchSpec::eCore_mips32el || 1369 core2 == ArchSpec::eCore_mips32r6el) 1370 return true; 1371 if (core2 == ArchSpec::eCore_mips64el || 1372 core2 == ArchSpec::eCore_mips64r6el) 1373 return true; 1374 } 1375 break; 1376 1377 default: 1378 break; 1379 } 1380 if (try_inverse) 1381 return cores_match(core2, core1, false, enforce_exact_match); 1382 return false; 1383 } 1384 1385 bool lldb_private::operator<(const ArchSpec &lhs, const ArchSpec &rhs) { 1386 const ArchSpec::Core lhs_core = lhs.GetCore(); 1387 const ArchSpec::Core rhs_core = rhs.GetCore(); 1388 return lhs_core < rhs_core; 1389 } 1390 1391 1392 bool lldb_private::operator==(const ArchSpec &lhs, const ArchSpec &rhs) { 1393 return lhs.GetCore() == rhs.GetCore(); 1394 } 1395 1396 bool ArchSpec::IsFullySpecifiedTriple() const { 1397 const auto &user_specified_triple = GetTriple(); 1398 1399 bool user_triple_fully_specified = false; 1400 1401 if ((user_specified_triple.getOS() != llvm::Triple::UnknownOS) || 1402 TripleOSWasSpecified()) { 1403 if ((user_specified_triple.getVendor() != llvm::Triple::UnknownVendor) || 1404 TripleVendorWasSpecified()) { 1405 const unsigned unspecified = 0; 1406 if (user_specified_triple.getOSMajorVersion() != unspecified) { 1407 user_triple_fully_specified = true; 1408 } 1409 } 1410 } 1411 1412 return user_triple_fully_specified; 1413 } 1414 1415 void ArchSpec::PiecewiseTripleCompare( 1416 const ArchSpec &other, bool &arch_different, bool &vendor_different, 1417 bool &os_different, bool &os_version_different, bool &env_different) const { 1418 const llvm::Triple &me(GetTriple()); 1419 const llvm::Triple &them(other.GetTriple()); 1420 1421 arch_different = (me.getArch() != them.getArch()); 1422 1423 vendor_different = (me.getVendor() != them.getVendor()); 1424 1425 os_different = (me.getOS() != them.getOS()); 1426 1427 os_version_different = (me.getOSMajorVersion() != them.getOSMajorVersion()); 1428 1429 env_different = (me.getEnvironment() != them.getEnvironment()); 1430 } 1431 1432 bool ArchSpec::IsAlwaysThumbInstructions() const { 1433 std::string Status; 1434 if (GetTriple().getArch() == llvm::Triple::arm || 1435 GetTriple().getArch() == llvm::Triple::thumb) { 1436 // v. https://en.wikipedia.org/wiki/ARM_Cortex-M 1437 // 1438 // Cortex-M0 through Cortex-M7 are ARM processor cores which can only 1439 // execute thumb instructions. We map the cores to arch names like this: 1440 // 1441 // Cortex-M0, Cortex-M0+, Cortex-M1: armv6m Cortex-M3: armv7m Cortex-M4, 1442 // Cortex-M7: armv7em 1443 1444 if (GetCore() == ArchSpec::Core::eCore_arm_armv7m || 1445 GetCore() == ArchSpec::Core::eCore_arm_armv7em || 1446 GetCore() == ArchSpec::Core::eCore_arm_armv6m || 1447 GetCore() == ArchSpec::Core::eCore_thumbv7m || 1448 GetCore() == ArchSpec::Core::eCore_thumbv7em || 1449 GetCore() == ArchSpec::Core::eCore_thumbv6m) { 1450 return true; 1451 } 1452 // Windows on ARM is always thumb. 1453 if (GetTriple().isOSWindows()) 1454 return true; 1455 } 1456 return false; 1457 } 1458 1459 void ArchSpec::DumpTriple(llvm::raw_ostream &s) const { 1460 const llvm::Triple &triple = GetTriple(); 1461 llvm::StringRef arch_str = triple.getArchName(); 1462 llvm::StringRef vendor_str = triple.getVendorName(); 1463 llvm::StringRef os_str = triple.getOSName(); 1464 llvm::StringRef environ_str = triple.getEnvironmentName(); 1465 1466 s << llvm::formatv("{0}-{1}-{2}", arch_str.empty() ? "*" : arch_str, 1467 vendor_str.empty() ? "*" : vendor_str, 1468 os_str.empty() ? "*" : os_str); 1469 1470 if (!environ_str.empty()) 1471 s << "-" << environ_str; 1472 } 1473