1be691f3bSpatrick //===-- RegisterInfos_arm64_sve.h -------------------------------*- C++ -*-===// 2be691f3bSpatrick // 3be691f3bSpatrick // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4be691f3bSpatrick // See https://llvm.org/LICENSE.txt for license information. 5be691f3bSpatrick // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6be691f3bSpatrick // 7be691f3bSpatrick //===----------------------------------------------------------------------===// 8be691f3bSpatrick 9be691f3bSpatrick #ifdef DECLARE_REGISTER_INFOS_ARM64_STRUCT 10be691f3bSpatrick 11be691f3bSpatrick enum { 12be691f3bSpatrick sve_vg = exc_far, 13be691f3bSpatrick 14be691f3bSpatrick sve_z0, 15be691f3bSpatrick sve_z1, 16be691f3bSpatrick sve_z2, 17be691f3bSpatrick sve_z3, 18be691f3bSpatrick sve_z4, 19be691f3bSpatrick sve_z5, 20be691f3bSpatrick sve_z6, 21be691f3bSpatrick sve_z7, 22be691f3bSpatrick sve_z8, 23be691f3bSpatrick sve_z9, 24be691f3bSpatrick sve_z10, 25be691f3bSpatrick sve_z11, 26be691f3bSpatrick sve_z12, 27be691f3bSpatrick sve_z13, 28be691f3bSpatrick sve_z14, 29be691f3bSpatrick sve_z15, 30be691f3bSpatrick sve_z16, 31be691f3bSpatrick sve_z17, 32be691f3bSpatrick sve_z18, 33be691f3bSpatrick sve_z19, 34be691f3bSpatrick sve_z20, 35be691f3bSpatrick sve_z21, 36be691f3bSpatrick sve_z22, 37be691f3bSpatrick sve_z23, 38be691f3bSpatrick sve_z24, 39be691f3bSpatrick sve_z25, 40be691f3bSpatrick sve_z26, 41be691f3bSpatrick sve_z27, 42be691f3bSpatrick sve_z28, 43be691f3bSpatrick sve_z29, 44be691f3bSpatrick sve_z30, 45be691f3bSpatrick sve_z31, 46be691f3bSpatrick 47be691f3bSpatrick sve_p0, 48be691f3bSpatrick sve_p1, 49be691f3bSpatrick sve_p2, 50be691f3bSpatrick sve_p3, 51be691f3bSpatrick sve_p4, 52be691f3bSpatrick sve_p5, 53be691f3bSpatrick sve_p6, 54be691f3bSpatrick sve_p7, 55be691f3bSpatrick sve_p8, 56be691f3bSpatrick sve_p9, 57be691f3bSpatrick sve_p10, 58be691f3bSpatrick sve_p11, 59be691f3bSpatrick sve_p12, 60be691f3bSpatrick sve_p13, 61be691f3bSpatrick sve_p14, 62be691f3bSpatrick sve_p15, 63be691f3bSpatrick 64be691f3bSpatrick sve_ffr, 65be691f3bSpatrick }; 66be691f3bSpatrick 67be691f3bSpatrick #ifndef SVE_OFFSET_VG 68be691f3bSpatrick #error SVE_OFFSET_VG must be defined before including this header file 69be691f3bSpatrick #endif 70be691f3bSpatrick 71be691f3bSpatrick static uint32_t g_sve_s0_invalidates[] = {sve_z0, fpu_v0, fpu_d0, 72be691f3bSpatrick LLDB_INVALID_REGNUM}; 73be691f3bSpatrick static uint32_t g_sve_s1_invalidates[] = {sve_z1, fpu_v1, fpu_d1, 74be691f3bSpatrick LLDB_INVALID_REGNUM}; 75be691f3bSpatrick static uint32_t g_sve_s2_invalidates[] = {sve_z2, fpu_v2, fpu_d2, 76be691f3bSpatrick LLDB_INVALID_REGNUM}; 77be691f3bSpatrick static uint32_t g_sve_s3_invalidates[] = {sve_z3, fpu_v3, fpu_d3, 78be691f3bSpatrick LLDB_INVALID_REGNUM}; 79be691f3bSpatrick static uint32_t g_sve_s4_invalidates[] = {sve_z4, fpu_v4, fpu_d4, 80be691f3bSpatrick LLDB_INVALID_REGNUM}; 81be691f3bSpatrick static uint32_t g_sve_s5_invalidates[] = {sve_z5, fpu_v5, fpu_d5, 82be691f3bSpatrick LLDB_INVALID_REGNUM}; 83be691f3bSpatrick static uint32_t g_sve_s6_invalidates[] = {sve_z6, fpu_v6, fpu_d6, 84be691f3bSpatrick LLDB_INVALID_REGNUM}; 85be691f3bSpatrick static uint32_t g_sve_s7_invalidates[] = {sve_z7, fpu_v7, fpu_d7, 86be691f3bSpatrick LLDB_INVALID_REGNUM}; 87be691f3bSpatrick static uint32_t g_sve_s8_invalidates[] = {sve_z8, fpu_v8, fpu_d8, 88be691f3bSpatrick LLDB_INVALID_REGNUM}; 89be691f3bSpatrick static uint32_t g_sve_s9_invalidates[] = {sve_z9, fpu_v9, fpu_d9, 90be691f3bSpatrick LLDB_INVALID_REGNUM}; 91be691f3bSpatrick static uint32_t g_sve_s10_invalidates[] = {sve_z10, fpu_v10, fpu_d10, 92be691f3bSpatrick LLDB_INVALID_REGNUM}; 93be691f3bSpatrick static uint32_t g_sve_s11_invalidates[] = {sve_z11, fpu_v11, fpu_d11, 94be691f3bSpatrick LLDB_INVALID_REGNUM}; 95be691f3bSpatrick static uint32_t g_sve_s12_invalidates[] = {sve_z12, fpu_v12, fpu_d12, 96be691f3bSpatrick LLDB_INVALID_REGNUM}; 97be691f3bSpatrick static uint32_t g_sve_s13_invalidates[] = {sve_z13, fpu_v13, fpu_d13, 98be691f3bSpatrick LLDB_INVALID_REGNUM}; 99be691f3bSpatrick static uint32_t g_sve_s14_invalidates[] = {sve_z14, fpu_v14, fpu_d14, 100be691f3bSpatrick LLDB_INVALID_REGNUM}; 101be691f3bSpatrick static uint32_t g_sve_s15_invalidates[] = {sve_z15, fpu_v15, fpu_d15, 102be691f3bSpatrick LLDB_INVALID_REGNUM}; 103be691f3bSpatrick static uint32_t g_sve_s16_invalidates[] = {sve_z16, fpu_v16, fpu_d16, 104be691f3bSpatrick LLDB_INVALID_REGNUM}; 105be691f3bSpatrick static uint32_t g_sve_s17_invalidates[] = {sve_z17, fpu_v17, fpu_d17, 106be691f3bSpatrick LLDB_INVALID_REGNUM}; 107be691f3bSpatrick static uint32_t g_sve_s18_invalidates[] = {sve_z18, fpu_v18, fpu_d18, 108be691f3bSpatrick LLDB_INVALID_REGNUM}; 109be691f3bSpatrick static uint32_t g_sve_s19_invalidates[] = {sve_z19, fpu_v19, fpu_d19, 110be691f3bSpatrick LLDB_INVALID_REGNUM}; 111be691f3bSpatrick static uint32_t g_sve_s20_invalidates[] = {sve_z20, fpu_v20, fpu_d20, 112be691f3bSpatrick LLDB_INVALID_REGNUM}; 113be691f3bSpatrick static uint32_t g_sve_s21_invalidates[] = {sve_z21, fpu_v21, fpu_d21, 114be691f3bSpatrick LLDB_INVALID_REGNUM}; 115be691f3bSpatrick static uint32_t g_sve_s22_invalidates[] = {sve_z22, fpu_v22, fpu_d22, 116be691f3bSpatrick LLDB_INVALID_REGNUM}; 117be691f3bSpatrick static uint32_t g_sve_s23_invalidates[] = {sve_z23, fpu_v23, fpu_d23, 118be691f3bSpatrick LLDB_INVALID_REGNUM}; 119be691f3bSpatrick static uint32_t g_sve_s24_invalidates[] = {sve_z24, fpu_v24, fpu_d24, 120be691f3bSpatrick LLDB_INVALID_REGNUM}; 121be691f3bSpatrick static uint32_t g_sve_s25_invalidates[] = {sve_z25, fpu_v25, fpu_d25, 122be691f3bSpatrick LLDB_INVALID_REGNUM}; 123be691f3bSpatrick static uint32_t g_sve_s26_invalidates[] = {sve_z26, fpu_v26, fpu_d26, 124be691f3bSpatrick LLDB_INVALID_REGNUM}; 125be691f3bSpatrick static uint32_t g_sve_s27_invalidates[] = {sve_z27, fpu_v27, fpu_d27, 126be691f3bSpatrick LLDB_INVALID_REGNUM}; 127be691f3bSpatrick static uint32_t g_sve_s28_invalidates[] = {sve_z28, fpu_v28, fpu_d28, 128be691f3bSpatrick LLDB_INVALID_REGNUM}; 129be691f3bSpatrick static uint32_t g_sve_s29_invalidates[] = {sve_z29, fpu_v29, fpu_d29, 130be691f3bSpatrick LLDB_INVALID_REGNUM}; 131be691f3bSpatrick static uint32_t g_sve_s30_invalidates[] = {sve_z30, fpu_v30, fpu_d30, 132be691f3bSpatrick LLDB_INVALID_REGNUM}; 133be691f3bSpatrick static uint32_t g_sve_s31_invalidates[] = {sve_z31, fpu_v31, fpu_d31, 134be691f3bSpatrick LLDB_INVALID_REGNUM}; 135be691f3bSpatrick 136be691f3bSpatrick static uint32_t g_sve_d0_invalidates[] = {sve_z0, fpu_v0, fpu_s0, 137be691f3bSpatrick LLDB_INVALID_REGNUM}; 138be691f3bSpatrick static uint32_t g_sve_d1_invalidates[] = {sve_z1, fpu_v1, fpu_s1, 139be691f3bSpatrick LLDB_INVALID_REGNUM}; 140be691f3bSpatrick static uint32_t g_sve_d2_invalidates[] = {sve_z2, fpu_v2, fpu_s2, 141be691f3bSpatrick LLDB_INVALID_REGNUM}; 142be691f3bSpatrick static uint32_t g_sve_d3_invalidates[] = {sve_z3, fpu_v3, fpu_s3, 143be691f3bSpatrick LLDB_INVALID_REGNUM}; 144be691f3bSpatrick static uint32_t g_sve_d4_invalidates[] = {sve_z4, fpu_v4, fpu_s4, 145be691f3bSpatrick LLDB_INVALID_REGNUM}; 146be691f3bSpatrick static uint32_t g_sve_d5_invalidates[] = {sve_z5, fpu_v5, fpu_s5, 147be691f3bSpatrick LLDB_INVALID_REGNUM}; 148be691f3bSpatrick static uint32_t g_sve_d6_invalidates[] = {sve_z6, fpu_v6, fpu_s6, 149be691f3bSpatrick LLDB_INVALID_REGNUM}; 150be691f3bSpatrick static uint32_t g_sve_d7_invalidates[] = {sve_z7, fpu_v7, fpu_s7, 151be691f3bSpatrick LLDB_INVALID_REGNUM}; 152be691f3bSpatrick static uint32_t g_sve_d8_invalidates[] = {sve_z8, fpu_v8, fpu_s8, 153be691f3bSpatrick LLDB_INVALID_REGNUM}; 154be691f3bSpatrick static uint32_t g_sve_d9_invalidates[] = {sve_z9, fpu_v9, fpu_s9, 155be691f3bSpatrick LLDB_INVALID_REGNUM}; 156be691f3bSpatrick static uint32_t g_sve_d10_invalidates[] = {sve_z10, fpu_v10, fpu_s10, 157be691f3bSpatrick LLDB_INVALID_REGNUM}; 158be691f3bSpatrick static uint32_t g_sve_d11_invalidates[] = {sve_z11, fpu_v11, fpu_s11, 159be691f3bSpatrick LLDB_INVALID_REGNUM}; 160be691f3bSpatrick static uint32_t g_sve_d12_invalidates[] = {sve_z12, fpu_v12, fpu_s12, 161be691f3bSpatrick LLDB_INVALID_REGNUM}; 162be691f3bSpatrick static uint32_t g_sve_d13_invalidates[] = {sve_z13, fpu_v13, fpu_s13, 163be691f3bSpatrick LLDB_INVALID_REGNUM}; 164be691f3bSpatrick static uint32_t g_sve_d14_invalidates[] = {sve_z14, fpu_v14, fpu_s14, 165be691f3bSpatrick LLDB_INVALID_REGNUM}; 166be691f3bSpatrick static uint32_t g_sve_d15_invalidates[] = {sve_z15, fpu_v15, fpu_s15, 167be691f3bSpatrick LLDB_INVALID_REGNUM}; 168be691f3bSpatrick static uint32_t g_sve_d16_invalidates[] = {sve_z16, fpu_v16, fpu_s16, 169be691f3bSpatrick LLDB_INVALID_REGNUM}; 170be691f3bSpatrick static uint32_t g_sve_d17_invalidates[] = {sve_z17, fpu_v17, fpu_s17, 171be691f3bSpatrick LLDB_INVALID_REGNUM}; 172be691f3bSpatrick static uint32_t g_sve_d18_invalidates[] = {sve_z18, fpu_v18, fpu_s18, 173be691f3bSpatrick LLDB_INVALID_REGNUM}; 174be691f3bSpatrick static uint32_t g_sve_d19_invalidates[] = {sve_z19, fpu_v19, fpu_s19, 175be691f3bSpatrick LLDB_INVALID_REGNUM}; 176be691f3bSpatrick static uint32_t g_sve_d20_invalidates[] = {sve_z20, fpu_v20, fpu_s20, 177be691f3bSpatrick LLDB_INVALID_REGNUM}; 178be691f3bSpatrick static uint32_t g_sve_d21_invalidates[] = {sve_z21, fpu_v21, fpu_s21, 179be691f3bSpatrick LLDB_INVALID_REGNUM}; 180be691f3bSpatrick static uint32_t g_sve_d22_invalidates[] = {sve_z22, fpu_v22, fpu_s22, 181be691f3bSpatrick LLDB_INVALID_REGNUM}; 182be691f3bSpatrick static uint32_t g_sve_d23_invalidates[] = {sve_z23, fpu_v23, fpu_s23, 183be691f3bSpatrick LLDB_INVALID_REGNUM}; 184be691f3bSpatrick static uint32_t g_sve_d24_invalidates[] = {sve_z24, fpu_v24, fpu_s24, 185be691f3bSpatrick LLDB_INVALID_REGNUM}; 186be691f3bSpatrick static uint32_t g_sve_d25_invalidates[] = {sve_z25, fpu_v25, fpu_s25, 187be691f3bSpatrick LLDB_INVALID_REGNUM}; 188be691f3bSpatrick static uint32_t g_sve_d26_invalidates[] = {sve_z26, fpu_v26, fpu_s26, 189be691f3bSpatrick LLDB_INVALID_REGNUM}; 190be691f3bSpatrick static uint32_t g_sve_d27_invalidates[] = {sve_z27, fpu_v27, fpu_s27, 191be691f3bSpatrick LLDB_INVALID_REGNUM}; 192be691f3bSpatrick static uint32_t g_sve_d28_invalidates[] = {sve_z28, fpu_v28, fpu_s28, 193be691f3bSpatrick LLDB_INVALID_REGNUM}; 194be691f3bSpatrick static uint32_t g_sve_d29_invalidates[] = {sve_z29, fpu_v29, fpu_s29, 195be691f3bSpatrick LLDB_INVALID_REGNUM}; 196be691f3bSpatrick static uint32_t g_sve_d30_invalidates[] = {sve_z30, fpu_v30, fpu_s30, 197be691f3bSpatrick LLDB_INVALID_REGNUM}; 198be691f3bSpatrick static uint32_t g_sve_d31_invalidates[] = {sve_z31, fpu_v31, fpu_s31, 199be691f3bSpatrick LLDB_INVALID_REGNUM}; 200be691f3bSpatrick 201be691f3bSpatrick static uint32_t g_sve_v0_invalidates[] = {sve_z0, fpu_d0, fpu_s0, 202be691f3bSpatrick LLDB_INVALID_REGNUM}; 203be691f3bSpatrick static uint32_t g_sve_v1_invalidates[] = {sve_z1, fpu_d1, fpu_s1, 204be691f3bSpatrick LLDB_INVALID_REGNUM}; 205be691f3bSpatrick static uint32_t g_sve_v2_invalidates[] = {sve_z2, fpu_d2, fpu_s2, 206be691f3bSpatrick LLDB_INVALID_REGNUM}; 207be691f3bSpatrick static uint32_t g_sve_v3_invalidates[] = {sve_z3, fpu_d3, fpu_s3, 208be691f3bSpatrick LLDB_INVALID_REGNUM}; 209be691f3bSpatrick static uint32_t g_sve_v4_invalidates[] = {sve_z4, fpu_d4, fpu_s4, 210be691f3bSpatrick LLDB_INVALID_REGNUM}; 211be691f3bSpatrick static uint32_t g_sve_v5_invalidates[] = {sve_z5, fpu_d5, fpu_s5, 212be691f3bSpatrick LLDB_INVALID_REGNUM}; 213be691f3bSpatrick static uint32_t g_sve_v6_invalidates[] = {sve_z6, fpu_d6, fpu_s6, 214be691f3bSpatrick LLDB_INVALID_REGNUM}; 215be691f3bSpatrick static uint32_t g_sve_v7_invalidates[] = {sve_z7, fpu_d7, fpu_s7, 216be691f3bSpatrick LLDB_INVALID_REGNUM}; 217be691f3bSpatrick static uint32_t g_sve_v8_invalidates[] = {sve_z8, fpu_d8, fpu_s8, 218be691f3bSpatrick LLDB_INVALID_REGNUM}; 219be691f3bSpatrick static uint32_t g_sve_v9_invalidates[] = {sve_z9, fpu_d9, fpu_s9, 220be691f3bSpatrick LLDB_INVALID_REGNUM}; 221be691f3bSpatrick static uint32_t g_sve_v10_invalidates[] = {sve_z10, fpu_d10, fpu_s10, 222be691f3bSpatrick LLDB_INVALID_REGNUM}; 223be691f3bSpatrick static uint32_t g_sve_v11_invalidates[] = {sve_z11, fpu_d11, fpu_s11, 224be691f3bSpatrick LLDB_INVALID_REGNUM}; 225be691f3bSpatrick static uint32_t g_sve_v12_invalidates[] = {sve_z12, fpu_d12, fpu_s12, 226be691f3bSpatrick LLDB_INVALID_REGNUM}; 227be691f3bSpatrick static uint32_t g_sve_v13_invalidates[] = {sve_z13, fpu_d13, fpu_s13, 228be691f3bSpatrick LLDB_INVALID_REGNUM}; 229be691f3bSpatrick static uint32_t g_sve_v14_invalidates[] = {sve_z14, fpu_d14, fpu_s14, 230be691f3bSpatrick LLDB_INVALID_REGNUM}; 231be691f3bSpatrick static uint32_t g_sve_v15_invalidates[] = {sve_z15, fpu_d15, fpu_s15, 232be691f3bSpatrick LLDB_INVALID_REGNUM}; 233be691f3bSpatrick static uint32_t g_sve_v16_invalidates[] = {sve_z16, fpu_d16, fpu_s16, 234be691f3bSpatrick LLDB_INVALID_REGNUM}; 235be691f3bSpatrick static uint32_t g_sve_v17_invalidates[] = {sve_z17, fpu_d17, fpu_s17, 236be691f3bSpatrick LLDB_INVALID_REGNUM}; 237be691f3bSpatrick static uint32_t g_sve_v18_invalidates[] = {sve_z18, fpu_d18, fpu_s18, 238be691f3bSpatrick LLDB_INVALID_REGNUM}; 239be691f3bSpatrick static uint32_t g_sve_v19_invalidates[] = {sve_z19, fpu_d19, fpu_s19, 240be691f3bSpatrick LLDB_INVALID_REGNUM}; 241be691f3bSpatrick static uint32_t g_sve_v20_invalidates[] = {sve_z20, fpu_d20, fpu_s20, 242be691f3bSpatrick LLDB_INVALID_REGNUM}; 243be691f3bSpatrick static uint32_t g_sve_v21_invalidates[] = {sve_z21, fpu_d21, fpu_s21, 244be691f3bSpatrick LLDB_INVALID_REGNUM}; 245be691f3bSpatrick static uint32_t g_sve_v22_invalidates[] = {sve_z22, fpu_d22, fpu_s22, 246be691f3bSpatrick LLDB_INVALID_REGNUM}; 247be691f3bSpatrick static uint32_t g_sve_v23_invalidates[] = {sve_z23, fpu_d23, fpu_s23, 248be691f3bSpatrick LLDB_INVALID_REGNUM}; 249be691f3bSpatrick static uint32_t g_sve_v24_invalidates[] = {sve_z24, fpu_d24, fpu_s24, 250be691f3bSpatrick LLDB_INVALID_REGNUM}; 251be691f3bSpatrick static uint32_t g_sve_v25_invalidates[] = {sve_z25, fpu_d25, fpu_s25, 252be691f3bSpatrick LLDB_INVALID_REGNUM}; 253be691f3bSpatrick static uint32_t g_sve_v26_invalidates[] = {sve_z26, fpu_d26, fpu_s26, 254be691f3bSpatrick LLDB_INVALID_REGNUM}; 255be691f3bSpatrick static uint32_t g_sve_v27_invalidates[] = {sve_z27, fpu_d27, fpu_s27, 256be691f3bSpatrick LLDB_INVALID_REGNUM}; 257be691f3bSpatrick static uint32_t g_sve_v28_invalidates[] = {sve_z28, fpu_d28, fpu_s28, 258be691f3bSpatrick LLDB_INVALID_REGNUM}; 259be691f3bSpatrick static uint32_t g_sve_v29_invalidates[] = {sve_z29, fpu_d29, fpu_s29, 260be691f3bSpatrick LLDB_INVALID_REGNUM}; 261be691f3bSpatrick static uint32_t g_sve_v30_invalidates[] = {sve_z30, fpu_d30, fpu_s30, 262be691f3bSpatrick LLDB_INVALID_REGNUM}; 263be691f3bSpatrick static uint32_t g_sve_v31_invalidates[] = {sve_z31, fpu_d31, fpu_s31, 264be691f3bSpatrick LLDB_INVALID_REGNUM}; 265be691f3bSpatrick 266be691f3bSpatrick static uint32_t g_contained_z0[] = {sve_z0, LLDB_INVALID_REGNUM}; 267be691f3bSpatrick static uint32_t g_contained_z1[] = {sve_z1, LLDB_INVALID_REGNUM}; 268be691f3bSpatrick static uint32_t g_contained_z2[] = {sve_z2, LLDB_INVALID_REGNUM}; 269be691f3bSpatrick static uint32_t g_contained_z3[] = {sve_z3, LLDB_INVALID_REGNUM}; 270be691f3bSpatrick static uint32_t g_contained_z4[] = {sve_z4, LLDB_INVALID_REGNUM}; 271be691f3bSpatrick static uint32_t g_contained_z5[] = {sve_z5, LLDB_INVALID_REGNUM}; 272be691f3bSpatrick static uint32_t g_contained_z6[] = {sve_z6, LLDB_INVALID_REGNUM}; 273be691f3bSpatrick static uint32_t g_contained_z7[] = {sve_z7, LLDB_INVALID_REGNUM}; 274be691f3bSpatrick static uint32_t g_contained_z8[] = {sve_z8, LLDB_INVALID_REGNUM}; 275be691f3bSpatrick static uint32_t g_contained_z9[] = {sve_z9, LLDB_INVALID_REGNUM}; 276be691f3bSpatrick static uint32_t g_contained_z10[] = {sve_z10, LLDB_INVALID_REGNUM}; 277be691f3bSpatrick static uint32_t g_contained_z11[] = {sve_z11, LLDB_INVALID_REGNUM}; 278be691f3bSpatrick static uint32_t g_contained_z12[] = {sve_z12, LLDB_INVALID_REGNUM}; 279be691f3bSpatrick static uint32_t g_contained_z13[] = {sve_z13, LLDB_INVALID_REGNUM}; 280be691f3bSpatrick static uint32_t g_contained_z14[] = {sve_z14, LLDB_INVALID_REGNUM}; 281be691f3bSpatrick static uint32_t g_contained_z15[] = {sve_z15, LLDB_INVALID_REGNUM}; 282be691f3bSpatrick static uint32_t g_contained_z16[] = {sve_z16, LLDB_INVALID_REGNUM}; 283be691f3bSpatrick static uint32_t g_contained_z17[] = {sve_z17, LLDB_INVALID_REGNUM}; 284be691f3bSpatrick static uint32_t g_contained_z18[] = {sve_z18, LLDB_INVALID_REGNUM}; 285be691f3bSpatrick static uint32_t g_contained_z19[] = {sve_z19, LLDB_INVALID_REGNUM}; 286be691f3bSpatrick static uint32_t g_contained_z20[] = {sve_z20, LLDB_INVALID_REGNUM}; 287be691f3bSpatrick static uint32_t g_contained_z21[] = {sve_z21, LLDB_INVALID_REGNUM}; 288be691f3bSpatrick static uint32_t g_contained_z22[] = {sve_z22, LLDB_INVALID_REGNUM}; 289be691f3bSpatrick static uint32_t g_contained_z23[] = {sve_z23, LLDB_INVALID_REGNUM}; 290be691f3bSpatrick static uint32_t g_contained_z24[] = {sve_z24, LLDB_INVALID_REGNUM}; 291be691f3bSpatrick static uint32_t g_contained_z25[] = {sve_z25, LLDB_INVALID_REGNUM}; 292be691f3bSpatrick static uint32_t g_contained_z26[] = {sve_z26, LLDB_INVALID_REGNUM}; 293be691f3bSpatrick static uint32_t g_contained_z27[] = {sve_z27, LLDB_INVALID_REGNUM}; 294be691f3bSpatrick static uint32_t g_contained_z28[] = {sve_z28, LLDB_INVALID_REGNUM}; 295be691f3bSpatrick static uint32_t g_contained_z29[] = {sve_z29, LLDB_INVALID_REGNUM}; 296be691f3bSpatrick static uint32_t g_contained_z30[] = {sve_z30, LLDB_INVALID_REGNUM}; 297be691f3bSpatrick static uint32_t g_contained_z31[] = {sve_z31, LLDB_INVALID_REGNUM}; 298be691f3bSpatrick 299be691f3bSpatrick #define VG_OFFSET_NAME(reg) SVE_OFFSET_VG 300be691f3bSpatrick 301be691f3bSpatrick #define SVE_REG_KIND(reg) MISC_KIND(reg, sve, LLDB_INVALID_REGNUM) 302be691f3bSpatrick #define MISC_VG_KIND(lldb_kind) MISC_KIND(vg, sve, LLDB_INVALID_REGNUM) 303be691f3bSpatrick 304be691f3bSpatrick // Default offset SVE Z registers and all corresponding pseudo registers 305be691f3bSpatrick // ( S, D and V registers) is zero and will be configured during execution. 306be691f3bSpatrick 307*f6aab3d8Srobert // clang-format off 308*f6aab3d8Srobert 309be691f3bSpatrick // Defines sve pseudo vector (V) register with 16-byte size 310be691f3bSpatrick #define DEFINE_VREG_SVE(vreg, zreg) \ 311be691f3bSpatrick { \ 312be691f3bSpatrick #vreg, nullptr, 16, 0, lldb::eEncodingVector, lldb::eFormatVectorOfUInt8, \ 313be691f3bSpatrick VREG_KIND(vreg), g_contained_##zreg, g_sve_##vreg##_invalidates, \ 314be691f3bSpatrick } 315be691f3bSpatrick 316be691f3bSpatrick // Defines S and D pseudo registers mapping over corresponding vector register 317be691f3bSpatrick #define DEFINE_FPU_PSEUDO_SVE(reg, size, zreg) \ 318be691f3bSpatrick { \ 319be691f3bSpatrick #reg, nullptr, size, 0, lldb::eEncodingIEEE754, lldb::eFormatFloat, \ 320be691f3bSpatrick LLDB_KIND(fpu_##reg), g_contained_##zreg, g_sve_##reg##_invalidates, \ 321be691f3bSpatrick } 322be691f3bSpatrick 323be691f3bSpatrick // Defines a Z vector register with 16-byte default size 324be691f3bSpatrick #define DEFINE_ZREG(reg) \ 325be691f3bSpatrick { \ 326be691f3bSpatrick #reg, nullptr, 16, 0, lldb::eEncodingVector, lldb::eFormatVectorOfUInt8, \ 327*f6aab3d8Srobert SVE_REG_KIND(reg), nullptr, nullptr, \ 328be691f3bSpatrick } 329be691f3bSpatrick 330be691f3bSpatrick // Defines a P vector register with 2-byte default size 331be691f3bSpatrick #define DEFINE_PREG(reg) \ 332be691f3bSpatrick { \ 333be691f3bSpatrick #reg, nullptr, 2, 0, lldb::eEncodingVector, lldb::eFormatVectorOfUInt8, \ 334*f6aab3d8Srobert SVE_REG_KIND(reg), nullptr, nullptr, \ 335be691f3bSpatrick } 336be691f3bSpatrick 337be691f3bSpatrick static lldb_private::RegisterInfo g_register_infos_arm64_sve_le[] = { 338be691f3bSpatrick // DEFINE_GPR64(name, GENERIC KIND) 339be691f3bSpatrick DEFINE_GPR64(x0, LLDB_REGNUM_GENERIC_ARG1), 340be691f3bSpatrick DEFINE_GPR64(x1, LLDB_REGNUM_GENERIC_ARG2), 341be691f3bSpatrick DEFINE_GPR64(x2, LLDB_REGNUM_GENERIC_ARG3), 342be691f3bSpatrick DEFINE_GPR64(x3, LLDB_REGNUM_GENERIC_ARG4), 343be691f3bSpatrick DEFINE_GPR64(x4, LLDB_REGNUM_GENERIC_ARG5), 344be691f3bSpatrick DEFINE_GPR64(x5, LLDB_REGNUM_GENERIC_ARG6), 345be691f3bSpatrick DEFINE_GPR64(x6, LLDB_REGNUM_GENERIC_ARG7), 346be691f3bSpatrick DEFINE_GPR64(x7, LLDB_REGNUM_GENERIC_ARG8), 347be691f3bSpatrick DEFINE_GPR64(x8, LLDB_INVALID_REGNUM), 348be691f3bSpatrick DEFINE_GPR64(x9, LLDB_INVALID_REGNUM), 349be691f3bSpatrick DEFINE_GPR64(x10, LLDB_INVALID_REGNUM), 350be691f3bSpatrick DEFINE_GPR64(x11, LLDB_INVALID_REGNUM), 351be691f3bSpatrick DEFINE_GPR64(x12, LLDB_INVALID_REGNUM), 352be691f3bSpatrick DEFINE_GPR64(x13, LLDB_INVALID_REGNUM), 353be691f3bSpatrick DEFINE_GPR64(x14, LLDB_INVALID_REGNUM), 354be691f3bSpatrick DEFINE_GPR64(x15, LLDB_INVALID_REGNUM), 355be691f3bSpatrick DEFINE_GPR64(x16, LLDB_INVALID_REGNUM), 356be691f3bSpatrick DEFINE_GPR64(x17, LLDB_INVALID_REGNUM), 357be691f3bSpatrick DEFINE_GPR64(x18, LLDB_INVALID_REGNUM), 358be691f3bSpatrick DEFINE_GPR64(x19, LLDB_INVALID_REGNUM), 359be691f3bSpatrick DEFINE_GPR64(x20, LLDB_INVALID_REGNUM), 360be691f3bSpatrick DEFINE_GPR64(x21, LLDB_INVALID_REGNUM), 361be691f3bSpatrick DEFINE_GPR64(x22, LLDB_INVALID_REGNUM), 362be691f3bSpatrick DEFINE_GPR64(x23, LLDB_INVALID_REGNUM), 363be691f3bSpatrick DEFINE_GPR64(x24, LLDB_INVALID_REGNUM), 364be691f3bSpatrick DEFINE_GPR64(x25, LLDB_INVALID_REGNUM), 365be691f3bSpatrick DEFINE_GPR64(x26, LLDB_INVALID_REGNUM), 366be691f3bSpatrick DEFINE_GPR64(x27, LLDB_INVALID_REGNUM), 367be691f3bSpatrick DEFINE_GPR64(x28, LLDB_INVALID_REGNUM), 368be691f3bSpatrick // DEFINE_GPR64(name, GENERIC KIND) 369be691f3bSpatrick DEFINE_GPR64_ALT(fp, x29, LLDB_REGNUM_GENERIC_FP), 370be691f3bSpatrick DEFINE_GPR64_ALT(lr, x30, LLDB_REGNUM_GENERIC_RA), 371be691f3bSpatrick DEFINE_GPR64_ALT(sp, x31, LLDB_REGNUM_GENERIC_SP), 372be691f3bSpatrick DEFINE_GPR64(pc, LLDB_REGNUM_GENERIC_PC), 373be691f3bSpatrick 374be691f3bSpatrick // DEFINE_MISC_REGS(name, size, TYPE, lldb kind) 375be691f3bSpatrick DEFINE_MISC_REGS(cpsr, 4, GPR, gpr_cpsr), 376be691f3bSpatrick 377be691f3bSpatrick // DEFINE_GPR32(name, parent name) 378be691f3bSpatrick DEFINE_GPR32(w0, x0), 379be691f3bSpatrick DEFINE_GPR32(w1, x1), 380be691f3bSpatrick DEFINE_GPR32(w2, x2), 381be691f3bSpatrick DEFINE_GPR32(w3, x3), 382be691f3bSpatrick DEFINE_GPR32(w4, x4), 383be691f3bSpatrick DEFINE_GPR32(w5, x5), 384be691f3bSpatrick DEFINE_GPR32(w6, x6), 385be691f3bSpatrick DEFINE_GPR32(w7, x7), 386be691f3bSpatrick DEFINE_GPR32(w8, x8), 387be691f3bSpatrick DEFINE_GPR32(w9, x9), 388be691f3bSpatrick DEFINE_GPR32(w10, x10), 389be691f3bSpatrick DEFINE_GPR32(w11, x11), 390be691f3bSpatrick DEFINE_GPR32(w12, x12), 391be691f3bSpatrick DEFINE_GPR32(w13, x13), 392be691f3bSpatrick DEFINE_GPR32(w14, x14), 393be691f3bSpatrick DEFINE_GPR32(w15, x15), 394be691f3bSpatrick DEFINE_GPR32(w16, x16), 395be691f3bSpatrick DEFINE_GPR32(w17, x17), 396be691f3bSpatrick DEFINE_GPR32(w18, x18), 397be691f3bSpatrick DEFINE_GPR32(w19, x19), 398be691f3bSpatrick DEFINE_GPR32(w20, x20), 399be691f3bSpatrick DEFINE_GPR32(w21, x21), 400be691f3bSpatrick DEFINE_GPR32(w22, x22), 401be691f3bSpatrick DEFINE_GPR32(w23, x23), 402be691f3bSpatrick DEFINE_GPR32(w24, x24), 403be691f3bSpatrick DEFINE_GPR32(w25, x25), 404be691f3bSpatrick DEFINE_GPR32(w26, x26), 405be691f3bSpatrick DEFINE_GPR32(w27, x27), 406be691f3bSpatrick DEFINE_GPR32(w28, x28), 407be691f3bSpatrick 408be691f3bSpatrick // DEFINE_VREG_SVE(v register, z register) 409be691f3bSpatrick DEFINE_VREG_SVE(v0, z0), 410be691f3bSpatrick DEFINE_VREG_SVE(v1, z1), 411be691f3bSpatrick DEFINE_VREG_SVE(v2, z2), 412be691f3bSpatrick DEFINE_VREG_SVE(v3, z3), 413be691f3bSpatrick DEFINE_VREG_SVE(v4, z4), 414be691f3bSpatrick DEFINE_VREG_SVE(v5, z5), 415be691f3bSpatrick DEFINE_VREG_SVE(v6, z6), 416be691f3bSpatrick DEFINE_VREG_SVE(v7, z7), 417be691f3bSpatrick DEFINE_VREG_SVE(v8, z8), 418be691f3bSpatrick DEFINE_VREG_SVE(v9, z9), 419be691f3bSpatrick DEFINE_VREG_SVE(v10, z10), 420be691f3bSpatrick DEFINE_VREG_SVE(v11, z11), 421be691f3bSpatrick DEFINE_VREG_SVE(v12, z12), 422be691f3bSpatrick DEFINE_VREG_SVE(v13, z13), 423be691f3bSpatrick DEFINE_VREG_SVE(v14, z14), 424be691f3bSpatrick DEFINE_VREG_SVE(v15, z15), 425be691f3bSpatrick DEFINE_VREG_SVE(v16, z16), 426be691f3bSpatrick DEFINE_VREG_SVE(v17, z17), 427be691f3bSpatrick DEFINE_VREG_SVE(v18, z18), 428be691f3bSpatrick DEFINE_VREG_SVE(v19, z19), 429be691f3bSpatrick DEFINE_VREG_SVE(v20, z20), 430be691f3bSpatrick DEFINE_VREG_SVE(v21, z21), 431be691f3bSpatrick DEFINE_VREG_SVE(v22, z22), 432be691f3bSpatrick DEFINE_VREG_SVE(v23, z23), 433be691f3bSpatrick DEFINE_VREG_SVE(v24, z24), 434be691f3bSpatrick DEFINE_VREG_SVE(v25, z25), 435be691f3bSpatrick DEFINE_VREG_SVE(v26, z26), 436be691f3bSpatrick DEFINE_VREG_SVE(v27, z27), 437be691f3bSpatrick DEFINE_VREG_SVE(v28, z28), 438be691f3bSpatrick DEFINE_VREG_SVE(v29, z29), 439be691f3bSpatrick DEFINE_VREG_SVE(v30, z30), 440be691f3bSpatrick DEFINE_VREG_SVE(v31, z31), 441be691f3bSpatrick 442be691f3bSpatrick // DEFINE_FPU_PSEUDO(name, size, ENDIAN OFFSET, parent register) 443be691f3bSpatrick DEFINE_FPU_PSEUDO_SVE(s0, 4, z0), 444be691f3bSpatrick DEFINE_FPU_PSEUDO_SVE(s1, 4, z1), 445be691f3bSpatrick DEFINE_FPU_PSEUDO_SVE(s2, 4, z2), 446be691f3bSpatrick DEFINE_FPU_PSEUDO_SVE(s3, 4, z3), 447be691f3bSpatrick DEFINE_FPU_PSEUDO_SVE(s4, 4, z4), 448be691f3bSpatrick DEFINE_FPU_PSEUDO_SVE(s5, 4, z5), 449be691f3bSpatrick DEFINE_FPU_PSEUDO_SVE(s6, 4, z6), 450be691f3bSpatrick DEFINE_FPU_PSEUDO_SVE(s7, 4, z7), 451be691f3bSpatrick DEFINE_FPU_PSEUDO_SVE(s8, 4, z8), 452be691f3bSpatrick DEFINE_FPU_PSEUDO_SVE(s9, 4, z9), 453be691f3bSpatrick DEFINE_FPU_PSEUDO_SVE(s10, 4, z10), 454be691f3bSpatrick DEFINE_FPU_PSEUDO_SVE(s11, 4, z11), 455be691f3bSpatrick DEFINE_FPU_PSEUDO_SVE(s12, 4, z12), 456be691f3bSpatrick DEFINE_FPU_PSEUDO_SVE(s13, 4, z13), 457be691f3bSpatrick DEFINE_FPU_PSEUDO_SVE(s14, 4, z14), 458be691f3bSpatrick DEFINE_FPU_PSEUDO_SVE(s15, 4, z15), 459be691f3bSpatrick DEFINE_FPU_PSEUDO_SVE(s16, 4, z16), 460be691f3bSpatrick DEFINE_FPU_PSEUDO_SVE(s17, 4, z17), 461be691f3bSpatrick DEFINE_FPU_PSEUDO_SVE(s18, 4, z18), 462be691f3bSpatrick DEFINE_FPU_PSEUDO_SVE(s19, 4, z19), 463be691f3bSpatrick DEFINE_FPU_PSEUDO_SVE(s20, 4, z20), 464be691f3bSpatrick DEFINE_FPU_PSEUDO_SVE(s21, 4, z21), 465be691f3bSpatrick DEFINE_FPU_PSEUDO_SVE(s22, 4, z22), 466be691f3bSpatrick DEFINE_FPU_PSEUDO_SVE(s23, 4, z23), 467be691f3bSpatrick DEFINE_FPU_PSEUDO_SVE(s24, 4, z24), 468be691f3bSpatrick DEFINE_FPU_PSEUDO_SVE(s25, 4, z25), 469be691f3bSpatrick DEFINE_FPU_PSEUDO_SVE(s26, 4, z26), 470be691f3bSpatrick DEFINE_FPU_PSEUDO_SVE(s27, 4, z27), 471be691f3bSpatrick DEFINE_FPU_PSEUDO_SVE(s28, 4, z28), 472be691f3bSpatrick DEFINE_FPU_PSEUDO_SVE(s29, 4, z29), 473be691f3bSpatrick DEFINE_FPU_PSEUDO_SVE(s30, 4, z30), 474be691f3bSpatrick DEFINE_FPU_PSEUDO_SVE(s31, 4, z31), 475be691f3bSpatrick 476be691f3bSpatrick DEFINE_FPU_PSEUDO_SVE(d0, 8, z0), 477be691f3bSpatrick DEFINE_FPU_PSEUDO_SVE(d1, 8, z1), 478be691f3bSpatrick DEFINE_FPU_PSEUDO_SVE(d2, 8, z2), 479be691f3bSpatrick DEFINE_FPU_PSEUDO_SVE(d3, 8, z3), 480be691f3bSpatrick DEFINE_FPU_PSEUDO_SVE(d4, 8, z4), 481be691f3bSpatrick DEFINE_FPU_PSEUDO_SVE(d5, 8, z5), 482be691f3bSpatrick DEFINE_FPU_PSEUDO_SVE(d6, 8, z6), 483be691f3bSpatrick DEFINE_FPU_PSEUDO_SVE(d7, 8, z7), 484be691f3bSpatrick DEFINE_FPU_PSEUDO_SVE(d8, 8, z8), 485be691f3bSpatrick DEFINE_FPU_PSEUDO_SVE(d9, 8, z9), 486be691f3bSpatrick DEFINE_FPU_PSEUDO_SVE(d10, 8, z10), 487be691f3bSpatrick DEFINE_FPU_PSEUDO_SVE(d11, 8, z11), 488be691f3bSpatrick DEFINE_FPU_PSEUDO_SVE(d12, 8, z12), 489be691f3bSpatrick DEFINE_FPU_PSEUDO_SVE(d13, 8, z13), 490be691f3bSpatrick DEFINE_FPU_PSEUDO_SVE(d14, 8, z14), 491be691f3bSpatrick DEFINE_FPU_PSEUDO_SVE(d15, 8, z15), 492be691f3bSpatrick DEFINE_FPU_PSEUDO_SVE(d16, 8, z16), 493be691f3bSpatrick DEFINE_FPU_PSEUDO_SVE(d17, 8, z17), 494be691f3bSpatrick DEFINE_FPU_PSEUDO_SVE(d18, 8, z18), 495be691f3bSpatrick DEFINE_FPU_PSEUDO_SVE(d19, 8, z19), 496be691f3bSpatrick DEFINE_FPU_PSEUDO_SVE(d20, 8, z20), 497be691f3bSpatrick DEFINE_FPU_PSEUDO_SVE(d21, 8, z21), 498be691f3bSpatrick DEFINE_FPU_PSEUDO_SVE(d22, 8, z22), 499be691f3bSpatrick DEFINE_FPU_PSEUDO_SVE(d23, 8, z23), 500be691f3bSpatrick DEFINE_FPU_PSEUDO_SVE(d24, 8, z24), 501be691f3bSpatrick DEFINE_FPU_PSEUDO_SVE(d25, 8, z25), 502be691f3bSpatrick DEFINE_FPU_PSEUDO_SVE(d26, 8, z26), 503be691f3bSpatrick DEFINE_FPU_PSEUDO_SVE(d27, 8, z27), 504be691f3bSpatrick DEFINE_FPU_PSEUDO_SVE(d28, 8, z28), 505be691f3bSpatrick DEFINE_FPU_PSEUDO_SVE(d29, 8, z29), 506be691f3bSpatrick DEFINE_FPU_PSEUDO_SVE(d30, 8, z30), 507be691f3bSpatrick DEFINE_FPU_PSEUDO_SVE(d31, 8, z31), 508be691f3bSpatrick 509be691f3bSpatrick // DEFINE_MISC_REGS(name, size, TYPE, lldb kind) 510be691f3bSpatrick DEFINE_MISC_REGS(fpsr, 4, FPU, fpu_fpsr), 511be691f3bSpatrick DEFINE_MISC_REGS(fpcr, 4, FPU, fpu_fpcr), 512be691f3bSpatrick 513be691f3bSpatrick DEFINE_MISC_REGS(vg, 8, VG, sve_vg), 514be691f3bSpatrick // DEFINE_ZREG(name) 515be691f3bSpatrick DEFINE_ZREG(z0), 516be691f3bSpatrick DEFINE_ZREG(z1), 517be691f3bSpatrick DEFINE_ZREG(z2), 518be691f3bSpatrick DEFINE_ZREG(z3), 519be691f3bSpatrick DEFINE_ZREG(z4), 520be691f3bSpatrick DEFINE_ZREG(z5), 521be691f3bSpatrick DEFINE_ZREG(z6), 522be691f3bSpatrick DEFINE_ZREG(z7), 523be691f3bSpatrick DEFINE_ZREG(z8), 524be691f3bSpatrick DEFINE_ZREG(z9), 525be691f3bSpatrick DEFINE_ZREG(z10), 526be691f3bSpatrick DEFINE_ZREG(z11), 527be691f3bSpatrick DEFINE_ZREG(z12), 528be691f3bSpatrick DEFINE_ZREG(z13), 529be691f3bSpatrick DEFINE_ZREG(z14), 530be691f3bSpatrick DEFINE_ZREG(z15), 531be691f3bSpatrick DEFINE_ZREG(z16), 532be691f3bSpatrick DEFINE_ZREG(z17), 533be691f3bSpatrick DEFINE_ZREG(z18), 534be691f3bSpatrick DEFINE_ZREG(z19), 535be691f3bSpatrick DEFINE_ZREG(z20), 536be691f3bSpatrick DEFINE_ZREG(z21), 537be691f3bSpatrick DEFINE_ZREG(z22), 538be691f3bSpatrick DEFINE_ZREG(z23), 539be691f3bSpatrick DEFINE_ZREG(z24), 540be691f3bSpatrick DEFINE_ZREG(z25), 541be691f3bSpatrick DEFINE_ZREG(z26), 542be691f3bSpatrick DEFINE_ZREG(z27), 543be691f3bSpatrick DEFINE_ZREG(z28), 544be691f3bSpatrick DEFINE_ZREG(z29), 545be691f3bSpatrick DEFINE_ZREG(z30), 546be691f3bSpatrick DEFINE_ZREG(z31), 547be691f3bSpatrick 548be691f3bSpatrick // DEFINE_PREG(name) 549be691f3bSpatrick DEFINE_PREG(p0), 550be691f3bSpatrick DEFINE_PREG(p1), 551be691f3bSpatrick DEFINE_PREG(p2), 552be691f3bSpatrick DEFINE_PREG(p3), 553be691f3bSpatrick DEFINE_PREG(p4), 554be691f3bSpatrick DEFINE_PREG(p5), 555be691f3bSpatrick DEFINE_PREG(p6), 556be691f3bSpatrick DEFINE_PREG(p7), 557be691f3bSpatrick DEFINE_PREG(p8), 558be691f3bSpatrick DEFINE_PREG(p9), 559be691f3bSpatrick DEFINE_PREG(p10), 560be691f3bSpatrick DEFINE_PREG(p11), 561be691f3bSpatrick DEFINE_PREG(p12), 562be691f3bSpatrick DEFINE_PREG(p13), 563be691f3bSpatrick DEFINE_PREG(p14), 564be691f3bSpatrick DEFINE_PREG(p15), 565be691f3bSpatrick 566be691f3bSpatrick // DEFINE FFR 567be691f3bSpatrick DEFINE_PREG(ffr) 568be691f3bSpatrick // clang-format on 569be691f3bSpatrick }; 570be691f3bSpatrick 571be691f3bSpatrick #endif // DECLARE_REGISTER_INFOS_ARM64_SVE_STRUCT 572