1061da546Spatrick //===-- RegisterContext_mips.h --------------------------------*- C++ -*-===// 2061da546Spatrick // 3061da546Spatrick // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4061da546Spatrick // See https://llvm.org/LICENSE.txt for license information. 5061da546Spatrick // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6061da546Spatrick // 7061da546Spatrick //===----------------------------------------------------------------------===// 8061da546Spatrick 9*dda28197Spatrick #ifndef LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_REGISTERCONTEXT_MIPS_H 10*dda28197Spatrick #define LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_REGISTERCONTEXT_MIPS_H 11061da546Spatrick 12061da546Spatrick #include <cstddef> 13061da546Spatrick #include <cstdint> 14061da546Spatrick 15061da546Spatrick // eh_frame and DWARF Register numbers (eRegisterKindEHFrame & 16061da546Spatrick // eRegisterKindDWARF) 17061da546Spatrick 18061da546Spatrick enum { 19061da546Spatrick // GP Registers 20061da546Spatrick dwarf_zero_mips = 0, 21061da546Spatrick dwarf_r1_mips, 22061da546Spatrick dwarf_r2_mips, 23061da546Spatrick dwarf_r3_mips, 24061da546Spatrick dwarf_r4_mips, 25061da546Spatrick dwarf_r5_mips, 26061da546Spatrick dwarf_r6_mips, 27061da546Spatrick dwarf_r7_mips, 28061da546Spatrick dwarf_r8_mips, 29061da546Spatrick dwarf_r9_mips, 30061da546Spatrick dwarf_r10_mips, 31061da546Spatrick dwarf_r11_mips, 32061da546Spatrick dwarf_r12_mips, 33061da546Spatrick dwarf_r13_mips, 34061da546Spatrick dwarf_r14_mips, 35061da546Spatrick dwarf_r15_mips, 36061da546Spatrick dwarf_r16_mips, 37061da546Spatrick dwarf_r17_mips, 38061da546Spatrick dwarf_r18_mips, 39061da546Spatrick dwarf_r19_mips, 40061da546Spatrick dwarf_r20_mips, 41061da546Spatrick dwarf_r21_mips, 42061da546Spatrick dwarf_r22_mips, 43061da546Spatrick dwarf_r23_mips, 44061da546Spatrick dwarf_r24_mips, 45061da546Spatrick dwarf_r25_mips, 46061da546Spatrick dwarf_r26_mips, 47061da546Spatrick dwarf_r27_mips, 48061da546Spatrick dwarf_gp_mips, 49061da546Spatrick dwarf_sp_mips, 50061da546Spatrick dwarf_r30_mips, 51061da546Spatrick dwarf_ra_mips, 52061da546Spatrick dwarf_sr_mips, 53061da546Spatrick dwarf_lo_mips, 54061da546Spatrick dwarf_hi_mips, 55061da546Spatrick dwarf_bad_mips, 56061da546Spatrick dwarf_cause_mips, 57061da546Spatrick dwarf_pc_mips, 58061da546Spatrick dwarf_f0_mips, 59061da546Spatrick dwarf_f1_mips, 60061da546Spatrick dwarf_f2_mips, 61061da546Spatrick dwarf_f3_mips, 62061da546Spatrick dwarf_f4_mips, 63061da546Spatrick dwarf_f5_mips, 64061da546Spatrick dwarf_f6_mips, 65061da546Spatrick dwarf_f7_mips, 66061da546Spatrick dwarf_f8_mips, 67061da546Spatrick dwarf_f9_mips, 68061da546Spatrick dwarf_f10_mips, 69061da546Spatrick dwarf_f11_mips, 70061da546Spatrick dwarf_f12_mips, 71061da546Spatrick dwarf_f13_mips, 72061da546Spatrick dwarf_f14_mips, 73061da546Spatrick dwarf_f15_mips, 74061da546Spatrick dwarf_f16_mips, 75061da546Spatrick dwarf_f17_mips, 76061da546Spatrick dwarf_f18_mips, 77061da546Spatrick dwarf_f19_mips, 78061da546Spatrick dwarf_f20_mips, 79061da546Spatrick dwarf_f21_mips, 80061da546Spatrick dwarf_f22_mips, 81061da546Spatrick dwarf_f23_mips, 82061da546Spatrick dwarf_f24_mips, 83061da546Spatrick dwarf_f25_mips, 84061da546Spatrick dwarf_f26_mips, 85061da546Spatrick dwarf_f27_mips, 86061da546Spatrick dwarf_f28_mips, 87061da546Spatrick dwarf_f29_mips, 88061da546Spatrick dwarf_f30_mips, 89061da546Spatrick dwarf_f31_mips, 90061da546Spatrick dwarf_fcsr_mips, 91061da546Spatrick dwarf_fir_mips, 92061da546Spatrick dwarf_w0_mips, 93061da546Spatrick dwarf_w1_mips, 94061da546Spatrick dwarf_w2_mips, 95061da546Spatrick dwarf_w3_mips, 96061da546Spatrick dwarf_w4_mips, 97061da546Spatrick dwarf_w5_mips, 98061da546Spatrick dwarf_w6_mips, 99061da546Spatrick dwarf_w7_mips, 100061da546Spatrick dwarf_w8_mips, 101061da546Spatrick dwarf_w9_mips, 102061da546Spatrick dwarf_w10_mips, 103061da546Spatrick dwarf_w11_mips, 104061da546Spatrick dwarf_w12_mips, 105061da546Spatrick dwarf_w13_mips, 106061da546Spatrick dwarf_w14_mips, 107061da546Spatrick dwarf_w15_mips, 108061da546Spatrick dwarf_w16_mips, 109061da546Spatrick dwarf_w17_mips, 110061da546Spatrick dwarf_w18_mips, 111061da546Spatrick dwarf_w19_mips, 112061da546Spatrick dwarf_w20_mips, 113061da546Spatrick dwarf_w21_mips, 114061da546Spatrick dwarf_w22_mips, 115061da546Spatrick dwarf_w23_mips, 116061da546Spatrick dwarf_w24_mips, 117061da546Spatrick dwarf_w25_mips, 118061da546Spatrick dwarf_w26_mips, 119061da546Spatrick dwarf_w27_mips, 120061da546Spatrick dwarf_w28_mips, 121061da546Spatrick dwarf_w29_mips, 122061da546Spatrick dwarf_w30_mips, 123061da546Spatrick dwarf_w31_mips, 124061da546Spatrick dwarf_mcsr_mips, 125061da546Spatrick dwarf_mir_mips, 126061da546Spatrick dwarf_config5_mips, 127061da546Spatrick dwarf_ic_mips, 128061da546Spatrick dwarf_dummy_mips 129061da546Spatrick }; 130061da546Spatrick 131061da546Spatrick enum { 132061da546Spatrick dwarf_zero_mips64 = 0, 133061da546Spatrick dwarf_r1_mips64, 134061da546Spatrick dwarf_r2_mips64, 135061da546Spatrick dwarf_r3_mips64, 136061da546Spatrick dwarf_r4_mips64, 137061da546Spatrick dwarf_r5_mips64, 138061da546Spatrick dwarf_r6_mips64, 139061da546Spatrick dwarf_r7_mips64, 140061da546Spatrick dwarf_r8_mips64, 141061da546Spatrick dwarf_r9_mips64, 142061da546Spatrick dwarf_r10_mips64, 143061da546Spatrick dwarf_r11_mips64, 144061da546Spatrick dwarf_r12_mips64, 145061da546Spatrick dwarf_r13_mips64, 146061da546Spatrick dwarf_r14_mips64, 147061da546Spatrick dwarf_r15_mips64, 148061da546Spatrick dwarf_r16_mips64, 149061da546Spatrick dwarf_r17_mips64, 150061da546Spatrick dwarf_r18_mips64, 151061da546Spatrick dwarf_r19_mips64, 152061da546Spatrick dwarf_r20_mips64, 153061da546Spatrick dwarf_r21_mips64, 154061da546Spatrick dwarf_r22_mips64, 155061da546Spatrick dwarf_r23_mips64, 156061da546Spatrick dwarf_r24_mips64, 157061da546Spatrick dwarf_r25_mips64, 158061da546Spatrick dwarf_r26_mips64, 159061da546Spatrick dwarf_r27_mips64, 160061da546Spatrick dwarf_gp_mips64, 161061da546Spatrick dwarf_sp_mips64, 162061da546Spatrick dwarf_r30_mips64, 163061da546Spatrick dwarf_ra_mips64, 164061da546Spatrick dwarf_sr_mips64, 165061da546Spatrick dwarf_lo_mips64, 166061da546Spatrick dwarf_hi_mips64, 167061da546Spatrick dwarf_bad_mips64, 168061da546Spatrick dwarf_cause_mips64, 169061da546Spatrick dwarf_pc_mips64, 170061da546Spatrick dwarf_f0_mips64, 171061da546Spatrick dwarf_f1_mips64, 172061da546Spatrick dwarf_f2_mips64, 173061da546Spatrick dwarf_f3_mips64, 174061da546Spatrick dwarf_f4_mips64, 175061da546Spatrick dwarf_f5_mips64, 176061da546Spatrick dwarf_f6_mips64, 177061da546Spatrick dwarf_f7_mips64, 178061da546Spatrick dwarf_f8_mips64, 179061da546Spatrick dwarf_f9_mips64, 180061da546Spatrick dwarf_f10_mips64, 181061da546Spatrick dwarf_f11_mips64, 182061da546Spatrick dwarf_f12_mips64, 183061da546Spatrick dwarf_f13_mips64, 184061da546Spatrick dwarf_f14_mips64, 185061da546Spatrick dwarf_f15_mips64, 186061da546Spatrick dwarf_f16_mips64, 187061da546Spatrick dwarf_f17_mips64, 188061da546Spatrick dwarf_f18_mips64, 189061da546Spatrick dwarf_f19_mips64, 190061da546Spatrick dwarf_f20_mips64, 191061da546Spatrick dwarf_f21_mips64, 192061da546Spatrick dwarf_f22_mips64, 193061da546Spatrick dwarf_f23_mips64, 194061da546Spatrick dwarf_f24_mips64, 195061da546Spatrick dwarf_f25_mips64, 196061da546Spatrick dwarf_f26_mips64, 197061da546Spatrick dwarf_f27_mips64, 198061da546Spatrick dwarf_f28_mips64, 199061da546Spatrick dwarf_f29_mips64, 200061da546Spatrick dwarf_f30_mips64, 201061da546Spatrick dwarf_f31_mips64, 202061da546Spatrick dwarf_fcsr_mips64, 203061da546Spatrick dwarf_fir_mips64, 204061da546Spatrick dwarf_ic_mips64, 205061da546Spatrick dwarf_dummy_mips64, 206061da546Spatrick dwarf_w0_mips64, 207061da546Spatrick dwarf_w1_mips64, 208061da546Spatrick dwarf_w2_mips64, 209061da546Spatrick dwarf_w3_mips64, 210061da546Spatrick dwarf_w4_mips64, 211061da546Spatrick dwarf_w5_mips64, 212061da546Spatrick dwarf_w6_mips64, 213061da546Spatrick dwarf_w7_mips64, 214061da546Spatrick dwarf_w8_mips64, 215061da546Spatrick dwarf_w9_mips64, 216061da546Spatrick dwarf_w10_mips64, 217061da546Spatrick dwarf_w11_mips64, 218061da546Spatrick dwarf_w12_mips64, 219061da546Spatrick dwarf_w13_mips64, 220061da546Spatrick dwarf_w14_mips64, 221061da546Spatrick dwarf_w15_mips64, 222061da546Spatrick dwarf_w16_mips64, 223061da546Spatrick dwarf_w17_mips64, 224061da546Spatrick dwarf_w18_mips64, 225061da546Spatrick dwarf_w19_mips64, 226061da546Spatrick dwarf_w20_mips64, 227061da546Spatrick dwarf_w21_mips64, 228061da546Spatrick dwarf_w22_mips64, 229061da546Spatrick dwarf_w23_mips64, 230061da546Spatrick dwarf_w24_mips64, 231061da546Spatrick dwarf_w25_mips64, 232061da546Spatrick dwarf_w26_mips64, 233061da546Spatrick dwarf_w27_mips64, 234061da546Spatrick dwarf_w28_mips64, 235061da546Spatrick dwarf_w29_mips64, 236061da546Spatrick dwarf_w30_mips64, 237061da546Spatrick dwarf_w31_mips64, 238061da546Spatrick dwarf_mcsr_mips64, 239061da546Spatrick dwarf_mir_mips64, 240061da546Spatrick dwarf_config5_mips64, 241061da546Spatrick }; 242061da546Spatrick 243061da546Spatrick // GP registers 244061da546Spatrick struct GPR_linux_mips { 245061da546Spatrick uint64_t zero; 246061da546Spatrick uint64_t r1; 247061da546Spatrick uint64_t r2; 248061da546Spatrick uint64_t r3; 249061da546Spatrick uint64_t r4; 250061da546Spatrick uint64_t r5; 251061da546Spatrick uint64_t r6; 252061da546Spatrick uint64_t r7; 253061da546Spatrick uint64_t r8; 254061da546Spatrick uint64_t r9; 255061da546Spatrick uint64_t r10; 256061da546Spatrick uint64_t r11; 257061da546Spatrick uint64_t r12; 258061da546Spatrick uint64_t r13; 259061da546Spatrick uint64_t r14; 260061da546Spatrick uint64_t r15; 261061da546Spatrick uint64_t r16; 262061da546Spatrick uint64_t r17; 263061da546Spatrick uint64_t r18; 264061da546Spatrick uint64_t r19; 265061da546Spatrick uint64_t r20; 266061da546Spatrick uint64_t r21; 267061da546Spatrick uint64_t r22; 268061da546Spatrick uint64_t r23; 269061da546Spatrick uint64_t r24; 270061da546Spatrick uint64_t r25; 271061da546Spatrick uint64_t r26; 272061da546Spatrick uint64_t r27; 273061da546Spatrick uint64_t gp; 274061da546Spatrick uint64_t sp; 275061da546Spatrick uint64_t r30; 276061da546Spatrick uint64_t ra; 277061da546Spatrick uint64_t mullo; 278061da546Spatrick uint64_t mulhi; 279061da546Spatrick uint64_t pc; 280061da546Spatrick uint64_t badvaddr; 281061da546Spatrick uint64_t sr; 282061da546Spatrick uint64_t cause; 283061da546Spatrick uint64_t config5; 284061da546Spatrick }; 285061da546Spatrick 286061da546Spatrick struct FPR_linux_mips { 287061da546Spatrick uint64_t f0; 288061da546Spatrick uint64_t f1; 289061da546Spatrick uint64_t f2; 290061da546Spatrick uint64_t f3; 291061da546Spatrick uint64_t f4; 292061da546Spatrick uint64_t f5; 293061da546Spatrick uint64_t f6; 294061da546Spatrick uint64_t f7; 295061da546Spatrick uint64_t f8; 296061da546Spatrick uint64_t f9; 297061da546Spatrick uint64_t f10; 298061da546Spatrick uint64_t f11; 299061da546Spatrick uint64_t f12; 300061da546Spatrick uint64_t f13; 301061da546Spatrick uint64_t f14; 302061da546Spatrick uint64_t f15; 303061da546Spatrick uint64_t f16; 304061da546Spatrick uint64_t f17; 305061da546Spatrick uint64_t f18; 306061da546Spatrick uint64_t f19; 307061da546Spatrick uint64_t f20; 308061da546Spatrick uint64_t f21; 309061da546Spatrick uint64_t f22; 310061da546Spatrick uint64_t f23; 311061da546Spatrick uint64_t f24; 312061da546Spatrick uint64_t f25; 313061da546Spatrick uint64_t f26; 314061da546Spatrick uint64_t f27; 315061da546Spatrick uint64_t f28; 316061da546Spatrick uint64_t f29; 317061da546Spatrick uint64_t f30; 318061da546Spatrick uint64_t f31; 319061da546Spatrick uint32_t fcsr; 320061da546Spatrick uint32_t fir; 321061da546Spatrick uint32_t config5; 322061da546Spatrick }; 323061da546Spatrick 324061da546Spatrick struct MSAReg { 325061da546Spatrick uint8_t byte[16]; 326061da546Spatrick }; 327061da546Spatrick 328061da546Spatrick struct MSA_linux_mips { 329061da546Spatrick MSAReg w0; 330061da546Spatrick MSAReg w1; 331061da546Spatrick MSAReg w2; 332061da546Spatrick MSAReg w3; 333061da546Spatrick MSAReg w4; 334061da546Spatrick MSAReg w5; 335061da546Spatrick MSAReg w6; 336061da546Spatrick MSAReg w7; 337061da546Spatrick MSAReg w8; 338061da546Spatrick MSAReg w9; 339061da546Spatrick MSAReg w10; 340061da546Spatrick MSAReg w11; 341061da546Spatrick MSAReg w12; 342061da546Spatrick MSAReg w13; 343061da546Spatrick MSAReg w14; 344061da546Spatrick MSAReg w15; 345061da546Spatrick MSAReg w16; 346061da546Spatrick MSAReg w17; 347061da546Spatrick MSAReg w18; 348061da546Spatrick MSAReg w19; 349061da546Spatrick MSAReg w20; 350061da546Spatrick MSAReg w21; 351061da546Spatrick MSAReg w22; 352061da546Spatrick MSAReg w23; 353061da546Spatrick MSAReg w24; 354061da546Spatrick MSAReg w25; 355061da546Spatrick MSAReg w26; 356061da546Spatrick MSAReg w27; 357061da546Spatrick MSAReg w28; 358061da546Spatrick MSAReg w29; 359061da546Spatrick MSAReg w30; 360061da546Spatrick MSAReg w31; 361061da546Spatrick uint32_t fcsr; /* FPU control status register */ 362061da546Spatrick uint32_t fir; /* FPU implementaion revision */ 363061da546Spatrick uint32_t mcsr; /* MSA control status register */ 364061da546Spatrick uint32_t mir; /* MSA implementation revision */ 365061da546Spatrick uint32_t config5; /* Config5 register */ 366061da546Spatrick }; 367061da546Spatrick 368061da546Spatrick struct UserArea { 369061da546Spatrick GPR_linux_mips gpr; // General purpose registers. 370061da546Spatrick FPR_linux_mips fpr; // Floating point registers. 371061da546Spatrick MSA_linux_mips msa; // MSA registers. 372061da546Spatrick }; 373061da546Spatrick 374*dda28197Spatrick #endif // LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_REGISTERCONTEXT_MIPS_H 375