xref: /openbsd-src/gnu/llvm/lldb/source/Plugins/Architecture/Arm/ArchitectureArm.cpp (revision f6aab3d83b51b91c24247ad2c2573574de475a82)
1*dda28197Spatrick //===-- ArchitectureArm.cpp -----------------------------------------------===//
2061da546Spatrick //
3061da546Spatrick // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4061da546Spatrick // See https://llvm.org/LICENSE.txt for license information.
5061da546Spatrick // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6061da546Spatrick //
7061da546Spatrick //===----------------------------------------------------------------------===//
8061da546Spatrick 
9061da546Spatrick #include "Plugins/Architecture/Arm/ArchitectureArm.h"
10061da546Spatrick #include "Plugins/Process/Utility/ARMDefines.h"
11061da546Spatrick #include "Plugins/Process/Utility/InstructionUtils.h"
12061da546Spatrick #include "lldb/Core/PluginManager.h"
13061da546Spatrick #include "lldb/Target/RegisterContext.h"
14061da546Spatrick #include "lldb/Target/Thread.h"
15061da546Spatrick #include "lldb/Utility/ArchSpec.h"
16061da546Spatrick 
17061da546Spatrick using namespace lldb_private;
18061da546Spatrick using namespace lldb;
19061da546Spatrick 
LLDB_PLUGIN_DEFINE(ArchitectureArm)20*dda28197Spatrick LLDB_PLUGIN_DEFINE(ArchitectureArm)
21*dda28197Spatrick 
22061da546Spatrick void ArchitectureArm::Initialize() {
23061da546Spatrick   PluginManager::RegisterPlugin(GetPluginNameStatic(),
24061da546Spatrick                                 "Arm-specific algorithms",
25061da546Spatrick                                 &ArchitectureArm::Create);
26061da546Spatrick }
27061da546Spatrick 
Terminate()28061da546Spatrick void ArchitectureArm::Terminate() {
29061da546Spatrick   PluginManager::UnregisterPlugin(&ArchitectureArm::Create);
30061da546Spatrick }
31061da546Spatrick 
Create(const ArchSpec & arch)32061da546Spatrick std::unique_ptr<Architecture> ArchitectureArm::Create(const ArchSpec &arch) {
33061da546Spatrick   if (arch.GetMachine() != llvm::Triple::arm)
34061da546Spatrick     return nullptr;
35061da546Spatrick   return std::unique_ptr<Architecture>(new ArchitectureArm());
36061da546Spatrick }
37061da546Spatrick 
OverrideStopInfo(Thread & thread) const38061da546Spatrick void ArchitectureArm::OverrideStopInfo(Thread &thread) const {
39061da546Spatrick   // We need to check if we are stopped in Thumb mode in a IT instruction and
40061da546Spatrick   // detect if the condition doesn't pass. If this is the case it means we
41061da546Spatrick   // won't actually execute this instruction. If this happens we need to clear
42061da546Spatrick   // the stop reason to no thread plans think we are stopped for a reason and
43061da546Spatrick   // the plans should keep going.
44061da546Spatrick   //
45061da546Spatrick   // We do this because when single stepping many ARM processes, debuggers
46061da546Spatrick   // often use the BVR/BCR registers that says "stop when the PC is not equal
47061da546Spatrick   // to its current value". This method of stepping means we can end up
48061da546Spatrick   // stopping on instructions inside an if/then block that wouldn't get
49061da546Spatrick   // executed. By fixing this we can stop the debugger from seeming like you
50061da546Spatrick   // stepped through both the "if" _and_ the "else" clause when source level
51061da546Spatrick   // stepping because the debugger stops regardless due to the BVR/BCR
52061da546Spatrick   // triggering a stop.
53061da546Spatrick   //
54061da546Spatrick   // It also means we can set breakpoints on instructions inside an an if/then
55061da546Spatrick   // block and correctly skip them if we use the BKPT instruction. The ARM and
56061da546Spatrick   // Thumb BKPT instructions are unconditional even when executed in a Thumb IT
57061da546Spatrick   // block.
58061da546Spatrick   //
59061da546Spatrick   // If your debugger inserts software traps in ARM/Thumb code, it will need to
60061da546Spatrick   // use 16 and 32 bit instruction for 16 and 32 bit thumb instructions
61061da546Spatrick   // respectively. If your debugger inserts a 16 bit thumb trap on top of a 32
62061da546Spatrick   // bit thumb instruction for an opcode that is inside an if/then, it will
63061da546Spatrick   // change the it/then to conditionally execute your
64061da546Spatrick   // 16 bit trap and then cause your program to crash if it executes the
65061da546Spatrick   // trailing 16 bits (the second half of the 32 bit thumb instruction you
66061da546Spatrick   // partially overwrote).
67061da546Spatrick 
68061da546Spatrick   RegisterContextSP reg_ctx_sp(thread.GetRegisterContext());
69061da546Spatrick   if (!reg_ctx_sp)
70061da546Spatrick     return;
71061da546Spatrick 
72061da546Spatrick   const uint32_t cpsr = reg_ctx_sp->GetFlags(0);
73061da546Spatrick   if (cpsr == 0)
74061da546Spatrick     return;
75061da546Spatrick 
76061da546Spatrick   // Read the J and T bits to get the ISETSTATE
77061da546Spatrick   const uint32_t J = Bit32(cpsr, 24);
78061da546Spatrick   const uint32_t T = Bit32(cpsr, 5);
79061da546Spatrick   const uint32_t ISETSTATE = J << 1 | T;
80061da546Spatrick   if (ISETSTATE == 0) {
81061da546Spatrick // NOTE: I am pretty sure we want to enable the code below
82061da546Spatrick // that detects when we stop on an instruction in ARM mode that is conditional
83061da546Spatrick // and the condition doesn't pass. This can happen if you set a breakpoint on
84061da546Spatrick // an instruction that is conditional. We currently will _always_ stop on the
85061da546Spatrick // instruction which is bad. You can also run into this while single stepping
86061da546Spatrick // and you could appear to run code in the "if" and in the "else" clause
87061da546Spatrick // because it would stop at all of the conditional instructions in both. In
88061da546Spatrick // such cases, we really don't want to stop at this location.
89061da546Spatrick // I will check with the lldb-dev list first before I enable this.
90061da546Spatrick #if 0
91061da546Spatrick     // ARM mode: check for condition on instruction
92061da546Spatrick     const addr_t pc = reg_ctx_sp->GetPC();
93061da546Spatrick     Status error;
94061da546Spatrick     // If we fail to read the opcode we will get UINT64_MAX as the result in
95061da546Spatrick     // "opcode" which we can use to detect if we read a valid opcode.
96061da546Spatrick     const uint64_t opcode = thread.GetProcess()->ReadUnsignedIntegerFromMemory(pc, 4, UINT64_MAX, error);
97061da546Spatrick     if (opcode <= UINT32_MAX)
98061da546Spatrick     {
99061da546Spatrick         const uint32_t condition = Bits32((uint32_t)opcode, 31, 28);
100061da546Spatrick         if (!ARMConditionPassed(condition, cpsr))
101061da546Spatrick         {
102061da546Spatrick             // We ARE stopped on an ARM instruction whose condition doesn't
103061da546Spatrick             // pass so this instruction won't get executed. Regardless of why
104061da546Spatrick             // it stopped, we need to clear the stop info
105061da546Spatrick             thread.SetStopInfo (StopInfoSP());
106061da546Spatrick         }
107061da546Spatrick     }
108061da546Spatrick #endif
109061da546Spatrick   } else if (ISETSTATE == 1) {
110061da546Spatrick     // Thumb mode
111061da546Spatrick     const uint32_t ITSTATE = Bits32(cpsr, 15, 10) << 2 | Bits32(cpsr, 26, 25);
112061da546Spatrick     if (ITSTATE != 0) {
113061da546Spatrick       const uint32_t condition = Bits32(ITSTATE, 7, 4);
114061da546Spatrick       if (!ARMConditionPassed(condition, cpsr)) {
115061da546Spatrick         // We ARE stopped in a Thumb IT instruction on an instruction whose
116061da546Spatrick         // condition doesn't pass so this instruction won't get executed.
117061da546Spatrick         // Regardless of why it stopped, we need to clear the stop info
118061da546Spatrick         thread.SetStopInfo(StopInfoSP());
119061da546Spatrick       }
120061da546Spatrick     }
121061da546Spatrick   }
122061da546Spatrick }
123061da546Spatrick 
GetCallableLoadAddress(addr_t code_addr,AddressClass addr_class) const124061da546Spatrick addr_t ArchitectureArm::GetCallableLoadAddress(addr_t code_addr,
125061da546Spatrick                                                AddressClass addr_class) const {
126061da546Spatrick   bool is_alternate_isa = false;
127061da546Spatrick 
128061da546Spatrick   switch (addr_class) {
129061da546Spatrick   case AddressClass::eData:
130061da546Spatrick   case AddressClass::eDebug:
131061da546Spatrick     return LLDB_INVALID_ADDRESS;
132061da546Spatrick   case AddressClass::eCodeAlternateISA:
133061da546Spatrick     is_alternate_isa = true;
134061da546Spatrick     break;
135061da546Spatrick   default: break;
136061da546Spatrick   }
137061da546Spatrick 
138061da546Spatrick   if ((code_addr & 2u) || is_alternate_isa)
139061da546Spatrick     return code_addr | 1u;
140061da546Spatrick   return code_addr;
141061da546Spatrick }
142061da546Spatrick 
GetOpcodeLoadAddress(addr_t opcode_addr,AddressClass addr_class) const143061da546Spatrick addr_t ArchitectureArm::GetOpcodeLoadAddress(addr_t opcode_addr,
144061da546Spatrick                                              AddressClass addr_class) const {
145061da546Spatrick   switch (addr_class) {
146061da546Spatrick   case AddressClass::eData:
147061da546Spatrick   case AddressClass::eDebug:
148061da546Spatrick     return LLDB_INVALID_ADDRESS;
149061da546Spatrick   default: break;
150061da546Spatrick   }
151061da546Spatrick   return opcode_addr & ~(1ull);
152061da546Spatrick }
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