1*3cab2bb3Spatrick//===-- fixunsdfsivfp.S - Implement fixunsdfsivfp -------------------------===// 2*3cab2bb3Spatrick// 3*3cab2bb3Spatrick// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4*3cab2bb3Spatrick// See https://llvm.org/LICENSE.txt for license information. 5*3cab2bb3Spatrick// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6*3cab2bb3Spatrick// 7*3cab2bb3Spatrick//===----------------------------------------------------------------------===// 8*3cab2bb3Spatrick 9*3cab2bb3Spatrick#include "../assembly.h" 10*3cab2bb3Spatrick 11*3cab2bb3Spatrick// 12*3cab2bb3Spatrick// extern unsigned int __fixunsdfsivfp(double a); 13*3cab2bb3Spatrick// 14*3cab2bb3Spatrick// Converts double precision float to a 32-bit unsigned int rounding towards 15*3cab2bb3Spatrick// zero. All negative values become zero. 16*3cab2bb3Spatrick// Uses Darwin calling convention where a double precision parameter is 17*3cab2bb3Spatrick// passed in GPR register pair. 18*3cab2bb3Spatrick// 19*3cab2bb3Spatrick .syntax unified 20*3cab2bb3Spatrick .p2align 2 21*3cab2bb3SpatrickDEFINE_COMPILERRT_FUNCTION(__fixunsdfsivfp) 22*3cab2bb3Spatrick#if defined(COMPILER_RT_ARMHF_TARGET) 23*3cab2bb3Spatrick vcvt.u32.f64 s0, d0 24*3cab2bb3Spatrick vmov r0, s0 25*3cab2bb3Spatrick#else 26*3cab2bb3Spatrick vmov d7, r0, r1 // load double register from R0/R1 27*3cab2bb3Spatrick vcvt.u32.f64 s15, d7 // convert double to 32-bit int into s15 28*3cab2bb3Spatrick vmov r0, s15 // move s15 to result register 29*3cab2bb3Spatrick#endif 30*3cab2bb3Spatrick bx lr 31*3cab2bb3SpatrickEND_COMPILERRT_FUNCTION(__fixunsdfsivfp) 32*3cab2bb3Spatrick 33*3cab2bb3SpatrickNO_EXEC_STACK_DIRECTIVE 34*3cab2bb3Spatrick 35