1 //===--- X86.cpp - Implement X86 target feature support -------------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file implements X86 TargetInfo objects. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "X86.h" 14 #include "clang/Basic/Builtins.h" 15 #include "clang/Basic/Diagnostic.h" 16 #include "clang/Basic/TargetBuiltins.h" 17 #include "llvm/ADT/StringExtras.h" 18 #include "llvm/ADT/StringRef.h" 19 #include "llvm/ADT/StringSwitch.h" 20 #include "llvm/Support/X86TargetParser.h" 21 22 namespace clang { 23 namespace targets { 24 25 const Builtin::Info BuiltinInfoX86[] = { 26 #define BUILTIN(ID, TYPE, ATTRS) \ 27 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr}, 28 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 29 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE}, 30 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \ 31 {#ID, TYPE, ATTRS, HEADER, LANGS, FEATURE}, 32 #include "clang/Basic/BuiltinsX86.def" 33 34 #define BUILTIN(ID, TYPE, ATTRS) \ 35 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr}, 36 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 37 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE}, 38 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \ 39 {#ID, TYPE, ATTRS, HEADER, LANGS, FEATURE}, 40 #include "clang/Basic/BuiltinsX86_64.def" 41 }; 42 43 static const char *const GCCRegNames[] = { 44 "ax", "dx", "cx", "bx", "si", "di", "bp", "sp", 45 "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)", 46 "argp", "flags", "fpcr", "fpsr", "dirflag", "frame", "xmm0", "xmm1", 47 "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", "mm0", "mm1", 48 "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", "r8", "r9", 49 "r10", "r11", "r12", "r13", "r14", "r15", "xmm8", "xmm9", 50 "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", "ymm0", "ymm1", 51 "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7", "ymm8", "ymm9", 52 "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15", "xmm16", "xmm17", 53 "xmm18", "xmm19", "xmm20", "xmm21", "xmm22", "xmm23", "xmm24", "xmm25", 54 "xmm26", "xmm27", "xmm28", "xmm29", "xmm30", "xmm31", "ymm16", "ymm17", 55 "ymm18", "ymm19", "ymm20", "ymm21", "ymm22", "ymm23", "ymm24", "ymm25", 56 "ymm26", "ymm27", "ymm28", "ymm29", "ymm30", "ymm31", "zmm0", "zmm1", 57 "zmm2", "zmm3", "zmm4", "zmm5", "zmm6", "zmm7", "zmm8", "zmm9", 58 "zmm10", "zmm11", "zmm12", "zmm13", "zmm14", "zmm15", "zmm16", "zmm17", 59 "zmm18", "zmm19", "zmm20", "zmm21", "zmm22", "zmm23", "zmm24", "zmm25", 60 "zmm26", "zmm27", "zmm28", "zmm29", "zmm30", "zmm31", "k0", "k1", 61 "k2", "k3", "k4", "k5", "k6", "k7", 62 "cr0", "cr2", "cr3", "cr4", "cr8", 63 "dr0", "dr1", "dr2", "dr3", "dr6", "dr7", 64 "bnd0", "bnd1", "bnd2", "bnd3", 65 "tmm0", "tmm1", "tmm2", "tmm3", "tmm4", "tmm5", "tmm6", "tmm7", 66 }; 67 68 const TargetInfo::AddlRegName AddlRegNames[] = { 69 {{"al", "ah", "eax", "rax"}, 0}, 70 {{"bl", "bh", "ebx", "rbx"}, 3}, 71 {{"cl", "ch", "ecx", "rcx"}, 2}, 72 {{"dl", "dh", "edx", "rdx"}, 1}, 73 {{"esi", "rsi"}, 4}, 74 {{"edi", "rdi"}, 5}, 75 {{"esp", "rsp"}, 7}, 76 {{"ebp", "rbp"}, 6}, 77 {{"r8d", "r8w", "r8b"}, 38}, 78 {{"r9d", "r9w", "r9b"}, 39}, 79 {{"r10d", "r10w", "r10b"}, 40}, 80 {{"r11d", "r11w", "r11b"}, 41}, 81 {{"r12d", "r12w", "r12b"}, 42}, 82 {{"r13d", "r13w", "r13b"}, 43}, 83 {{"r14d", "r14w", "r14b"}, 44}, 84 {{"r15d", "r15w", "r15b"}, 45}, 85 }; 86 87 } // namespace targets 88 } // namespace clang 89 90 using namespace clang; 91 using namespace clang::targets; 92 93 bool X86TargetInfo::setFPMath(StringRef Name) { 94 if (Name == "387") { 95 FPMath = FP_387; 96 return true; 97 } 98 if (Name == "sse") { 99 FPMath = FP_SSE; 100 return true; 101 } 102 return false; 103 } 104 105 bool X86TargetInfo::initFeatureMap( 106 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU, 107 const std::vector<std::string> &FeaturesVec) const { 108 // FIXME: This *really* should not be here. 109 // X86_64 always has SSE2. 110 if (getTriple().getArch() == llvm::Triple::x86_64) 111 setFeatureEnabled(Features, "sse2", true); 112 113 using namespace llvm::X86; 114 115 SmallVector<StringRef, 16> CPUFeatures; 116 getFeaturesForCPU(CPU, CPUFeatures); 117 for (auto &F : CPUFeatures) 118 setFeatureEnabled(Features, F, true); 119 120 std::vector<std::string> UpdatedFeaturesVec; 121 for (const auto &Feature : FeaturesVec) { 122 // Expand general-regs-only to -x86, -mmx and -sse 123 if (Feature == "+general-regs-only") { 124 UpdatedFeaturesVec.push_back("-x87"); 125 UpdatedFeaturesVec.push_back("-mmx"); 126 UpdatedFeaturesVec.push_back("-sse"); 127 continue; 128 } 129 130 UpdatedFeaturesVec.push_back(Feature); 131 } 132 133 if (!TargetInfo::initFeatureMap(Features, Diags, CPU, UpdatedFeaturesVec)) 134 return false; 135 136 // Can't do this earlier because we need to be able to explicitly enable 137 // or disable these features and the things that they depend upon. 138 139 // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled. 140 auto I = Features.find("sse4.2"); 141 if (I != Features.end() && I->getValue() && 142 llvm::find(UpdatedFeaturesVec, "-popcnt") == UpdatedFeaturesVec.end()) 143 Features["popcnt"] = true; 144 145 // Additionally, if SSE is enabled and mmx is not explicitly disabled, 146 // then enable MMX. 147 I = Features.find("sse"); 148 if (I != Features.end() && I->getValue() && 149 llvm::find(UpdatedFeaturesVec, "-mmx") == UpdatedFeaturesVec.end()) 150 Features["mmx"] = true; 151 152 // Enable xsave if avx is enabled and xsave is not explicitly disabled. 153 I = Features.find("avx"); 154 if (I != Features.end() && I->getValue() && 155 llvm::find(UpdatedFeaturesVec, "-xsave") == UpdatedFeaturesVec.end()) 156 Features["xsave"] = true; 157 158 return true; 159 } 160 161 void X86TargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features, 162 StringRef Name, bool Enabled) const { 163 if (Name == "sse4") { 164 // We can get here via the __target__ attribute since that's not controlled 165 // via the -msse4/-mno-sse4 command line alias. Handle this the same way 166 // here - turn on the sse4.2 if enabled, turn off the sse4.1 level if 167 // disabled. 168 if (Enabled) 169 Name = "sse4.2"; 170 else 171 Name = "sse4.1"; 172 } 173 174 Features[Name] = Enabled; 175 llvm::X86::updateImpliedFeatures(Name, Enabled, Features); 176 } 177 178 /// handleTargetFeatures - Perform initialization based on the user 179 /// configured set of features. 180 bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 181 DiagnosticsEngine &Diags) { 182 for (const auto &Feature : Features) { 183 if (Feature[0] != '+') 184 continue; 185 186 if (Feature == "+aes") { 187 HasAES = true; 188 } else if (Feature == "+vaes") { 189 HasVAES = true; 190 } else if (Feature == "+pclmul") { 191 HasPCLMUL = true; 192 } else if (Feature == "+vpclmulqdq") { 193 HasVPCLMULQDQ = true; 194 } else if (Feature == "+lzcnt") { 195 HasLZCNT = true; 196 } else if (Feature == "+rdrnd") { 197 HasRDRND = true; 198 } else if (Feature == "+fsgsbase") { 199 HasFSGSBASE = true; 200 } else if (Feature == "+bmi") { 201 HasBMI = true; 202 } else if (Feature == "+bmi2") { 203 HasBMI2 = true; 204 } else if (Feature == "+popcnt") { 205 HasPOPCNT = true; 206 } else if (Feature == "+rtm") { 207 HasRTM = true; 208 } else if (Feature == "+prfchw") { 209 HasPRFCHW = true; 210 } else if (Feature == "+rdseed") { 211 HasRDSEED = true; 212 } else if (Feature == "+adx") { 213 HasADX = true; 214 } else if (Feature == "+tbm") { 215 HasTBM = true; 216 } else if (Feature == "+lwp") { 217 HasLWP = true; 218 } else if (Feature == "+fma") { 219 HasFMA = true; 220 } else if (Feature == "+f16c") { 221 HasF16C = true; 222 } else if (Feature == "+gfni") { 223 HasGFNI = true; 224 } else if (Feature == "+avx512cd") { 225 HasAVX512CD = true; 226 } else if (Feature == "+avx512vpopcntdq") { 227 HasAVX512VPOPCNTDQ = true; 228 } else if (Feature == "+avx512vnni") { 229 HasAVX512VNNI = true; 230 } else if (Feature == "+avx512bf16") { 231 HasAVX512BF16 = true; 232 } else if (Feature == "+avx512er") { 233 HasAVX512ER = true; 234 } else if (Feature == "+avx512pf") { 235 HasAVX512PF = true; 236 } else if (Feature == "+avx512dq") { 237 HasAVX512DQ = true; 238 } else if (Feature == "+avx512bitalg") { 239 HasAVX512BITALG = true; 240 } else if (Feature == "+avx512bw") { 241 HasAVX512BW = true; 242 } else if (Feature == "+avx512vl") { 243 HasAVX512VL = true; 244 } else if (Feature == "+avx512vbmi") { 245 HasAVX512VBMI = true; 246 } else if (Feature == "+avx512vbmi2") { 247 HasAVX512VBMI2 = true; 248 } else if (Feature == "+avx512ifma") { 249 HasAVX512IFMA = true; 250 } else if (Feature == "+avx512vp2intersect") { 251 HasAVX512VP2INTERSECT = true; 252 } else if (Feature == "+sha") { 253 HasSHA = true; 254 } else if (Feature == "+shstk") { 255 HasSHSTK = true; 256 } else if (Feature == "+movbe") { 257 HasMOVBE = true; 258 } else if (Feature == "+sgx") { 259 HasSGX = true; 260 } else if (Feature == "+cx8") { 261 HasCX8 = true; 262 } else if (Feature == "+cx16") { 263 HasCX16 = true; 264 } else if (Feature == "+fxsr") { 265 HasFXSR = true; 266 } else if (Feature == "+xsave") { 267 HasXSAVE = true; 268 } else if (Feature == "+xsaveopt") { 269 HasXSAVEOPT = true; 270 } else if (Feature == "+xsavec") { 271 HasXSAVEC = true; 272 } else if (Feature == "+xsaves") { 273 HasXSAVES = true; 274 } else if (Feature == "+mwaitx") { 275 HasMWAITX = true; 276 } else if (Feature == "+pku") { 277 HasPKU = true; 278 } else if (Feature == "+clflushopt") { 279 HasCLFLUSHOPT = true; 280 } else if (Feature == "+clwb") { 281 HasCLWB = true; 282 } else if (Feature == "+wbnoinvd") { 283 HasWBNOINVD = true; 284 } else if (Feature == "+prefetchwt1") { 285 HasPREFETCHWT1 = true; 286 } else if (Feature == "+clzero") { 287 HasCLZERO = true; 288 } else if (Feature == "+cldemote") { 289 HasCLDEMOTE = true; 290 } else if (Feature == "+rdpid") { 291 HasRDPID = true; 292 } else if (Feature == "+kl") { 293 HasKL = true; 294 } else if (Feature == "+widekl") { 295 HasWIDEKL = true; 296 } else if (Feature == "+retpoline-external-thunk") { 297 HasRetpolineExternalThunk = true; 298 } else if (Feature == "+sahf") { 299 HasLAHFSAHF = true; 300 } else if (Feature == "+waitpkg") { 301 HasWAITPKG = true; 302 } else if (Feature == "+movdiri") { 303 HasMOVDIRI = true; 304 } else if (Feature == "+movdir64b") { 305 HasMOVDIR64B = true; 306 } else if (Feature == "+pconfig") { 307 HasPCONFIG = true; 308 } else if (Feature == "+ptwrite") { 309 HasPTWRITE = true; 310 } else if (Feature == "+invpcid") { 311 HasINVPCID = true; 312 } else if (Feature == "+save-args") { 313 HasSaveArgs = true; 314 } else if (Feature == "+enqcmd") { 315 HasENQCMD = true; 316 } else if (Feature == "+hreset") { 317 HasHRESET = true; 318 } else if (Feature == "+amx-bf16") { 319 HasAMXBF16 = true; 320 } else if (Feature == "+amx-int8") { 321 HasAMXINT8 = true; 322 } else if (Feature == "+amx-tile") { 323 HasAMXTILE = true; 324 } else if (Feature == "+avxvnni") { 325 HasAVXVNNI = true; 326 } else if (Feature == "+serialize") { 327 HasSERIALIZE = true; 328 } else if (Feature == "+tsxldtrk") { 329 HasTSXLDTRK = true; 330 } else if (Feature == "+uintr") { 331 HasUINTR = true; 332 } 333 334 X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature) 335 .Case("+avx512f", AVX512F) 336 .Case("+avx2", AVX2) 337 .Case("+avx", AVX) 338 .Case("+sse4.2", SSE42) 339 .Case("+sse4.1", SSE41) 340 .Case("+ssse3", SSSE3) 341 .Case("+sse3", SSE3) 342 .Case("+sse2", SSE2) 343 .Case("+sse", SSE1) 344 .Default(NoSSE); 345 SSELevel = std::max(SSELevel, Level); 346 347 MMX3DNowEnum ThreeDNowLevel = llvm::StringSwitch<MMX3DNowEnum>(Feature) 348 .Case("+3dnowa", AMD3DNowAthlon) 349 .Case("+3dnow", AMD3DNow) 350 .Case("+mmx", MMX) 351 .Default(NoMMX3DNow); 352 MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel); 353 354 XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature) 355 .Case("+xop", XOP) 356 .Case("+fma4", FMA4) 357 .Case("+sse4a", SSE4A) 358 .Default(NoXOP); 359 XOPLevel = std::max(XOPLevel, XLevel); 360 } 361 362 // LLVM doesn't have a separate switch for fpmath, so only accept it if it 363 // matches the selected sse level. 364 if ((FPMath == FP_SSE && SSELevel < SSE1) || 365 (FPMath == FP_387 && SSELevel >= SSE1)) { 366 Diags.Report(diag::err_target_unsupported_fpmath) 367 << (FPMath == FP_SSE ? "sse" : "387"); 368 return false; 369 } 370 371 SimdDefaultAlign = 372 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 373 return true; 374 } 375 376 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro 377 /// definitions for this particular subtarget. 378 void X86TargetInfo::getTargetDefines(const LangOptions &Opts, 379 MacroBuilder &Builder) const { 380 // Inline assembly supports X86 flag outputs. 381 Builder.defineMacro("__GCC_ASM_FLAG_OUTPUTS__"); 382 383 std::string CodeModel = getTargetOpts().CodeModel; 384 if (CodeModel == "default") 385 CodeModel = "small"; 386 Builder.defineMacro("__code_model_" + CodeModel + "__"); 387 388 // Target identification. 389 if (getTriple().getArch() == llvm::Triple::x86_64) { 390 Builder.defineMacro("__amd64__"); 391 Builder.defineMacro("__amd64"); 392 Builder.defineMacro("__x86_64"); 393 Builder.defineMacro("__x86_64__"); 394 if (getTriple().getArchName() == "x86_64h") { 395 Builder.defineMacro("__x86_64h"); 396 Builder.defineMacro("__x86_64h__"); 397 } 398 } else { 399 DefineStd(Builder, "i386", Opts); 400 } 401 402 Builder.defineMacro("__SEG_GS"); 403 Builder.defineMacro("__SEG_FS"); 404 Builder.defineMacro("__seg_gs", "__attribute__((address_space(256)))"); 405 Builder.defineMacro("__seg_fs", "__attribute__((address_space(257)))"); 406 407 // Subtarget options. 408 // FIXME: We are hard-coding the tune parameters based on the CPU, but they 409 // truly should be based on -mtune options. 410 using namespace llvm::X86; 411 switch (CPU) { 412 case CK_None: 413 break; 414 case CK_i386: 415 // The rest are coming from the i386 define above. 416 Builder.defineMacro("__tune_i386__"); 417 break; 418 case CK_i486: 419 case CK_WinChipC6: 420 case CK_WinChip2: 421 case CK_C3: 422 defineCPUMacros(Builder, "i486"); 423 break; 424 case CK_PentiumMMX: 425 Builder.defineMacro("__pentium_mmx__"); 426 Builder.defineMacro("__tune_pentium_mmx__"); 427 LLVM_FALLTHROUGH; 428 case CK_i586: 429 case CK_Pentium: 430 defineCPUMacros(Builder, "i586"); 431 defineCPUMacros(Builder, "pentium"); 432 break; 433 case CK_Pentium3: 434 case CK_PentiumM: 435 Builder.defineMacro("__tune_pentium3__"); 436 LLVM_FALLTHROUGH; 437 case CK_Pentium2: 438 case CK_C3_2: 439 Builder.defineMacro("__tune_pentium2__"); 440 LLVM_FALLTHROUGH; 441 case CK_PentiumPro: 442 case CK_i686: 443 defineCPUMacros(Builder, "i686"); 444 defineCPUMacros(Builder, "pentiumpro"); 445 break; 446 case CK_Pentium4: 447 defineCPUMacros(Builder, "pentium4"); 448 break; 449 case CK_Yonah: 450 case CK_Prescott: 451 case CK_Nocona: 452 defineCPUMacros(Builder, "nocona"); 453 break; 454 case CK_Core2: 455 case CK_Penryn: 456 defineCPUMacros(Builder, "core2"); 457 break; 458 case CK_Bonnell: 459 defineCPUMacros(Builder, "atom"); 460 break; 461 case CK_Silvermont: 462 defineCPUMacros(Builder, "slm"); 463 break; 464 case CK_Goldmont: 465 defineCPUMacros(Builder, "goldmont"); 466 break; 467 case CK_GoldmontPlus: 468 defineCPUMacros(Builder, "goldmont_plus"); 469 break; 470 case CK_Tremont: 471 defineCPUMacros(Builder, "tremont"); 472 break; 473 case CK_Nehalem: 474 case CK_Westmere: 475 case CK_SandyBridge: 476 case CK_IvyBridge: 477 case CK_Haswell: 478 case CK_Broadwell: 479 case CK_SkylakeClient: 480 case CK_SkylakeServer: 481 case CK_Cascadelake: 482 case CK_Cooperlake: 483 case CK_Cannonlake: 484 case CK_IcelakeClient: 485 case CK_Rocketlake: 486 case CK_IcelakeServer: 487 case CK_Tigerlake: 488 case CK_SapphireRapids: 489 case CK_Alderlake: 490 // FIXME: Historically, we defined this legacy name, it would be nice to 491 // remove it at some point. We've never exposed fine-grained names for 492 // recent primary x86 CPUs, and we should keep it that way. 493 defineCPUMacros(Builder, "corei7"); 494 break; 495 case CK_KNL: 496 defineCPUMacros(Builder, "knl"); 497 break; 498 case CK_KNM: 499 break; 500 case CK_Lakemont: 501 defineCPUMacros(Builder, "i586", /*Tuning*/false); 502 defineCPUMacros(Builder, "pentium", /*Tuning*/false); 503 Builder.defineMacro("__tune_lakemont__"); 504 break; 505 case CK_K6_2: 506 Builder.defineMacro("__k6_2__"); 507 Builder.defineMacro("__tune_k6_2__"); 508 LLVM_FALLTHROUGH; 509 case CK_K6_3: 510 if (CPU != CK_K6_2) { // In case of fallthrough 511 // FIXME: GCC may be enabling these in cases where some other k6 512 // architecture is specified but -m3dnow is explicitly provided. The 513 // exact semantics need to be determined and emulated here. 514 Builder.defineMacro("__k6_3__"); 515 Builder.defineMacro("__tune_k6_3__"); 516 } 517 LLVM_FALLTHROUGH; 518 case CK_K6: 519 defineCPUMacros(Builder, "k6"); 520 break; 521 case CK_Athlon: 522 case CK_AthlonXP: 523 defineCPUMacros(Builder, "athlon"); 524 if (SSELevel != NoSSE) { 525 Builder.defineMacro("__athlon_sse__"); 526 Builder.defineMacro("__tune_athlon_sse__"); 527 } 528 break; 529 case CK_K8: 530 case CK_K8SSE3: 531 case CK_x86_64: 532 defineCPUMacros(Builder, "k8"); 533 break; 534 case CK_x86_64_v2: 535 case CK_x86_64_v3: 536 case CK_x86_64_v4: 537 break; 538 case CK_AMDFAM10: 539 defineCPUMacros(Builder, "amdfam10"); 540 break; 541 case CK_BTVER1: 542 defineCPUMacros(Builder, "btver1"); 543 break; 544 case CK_BTVER2: 545 defineCPUMacros(Builder, "btver2"); 546 break; 547 case CK_BDVER1: 548 defineCPUMacros(Builder, "bdver1"); 549 break; 550 case CK_BDVER2: 551 defineCPUMacros(Builder, "bdver2"); 552 break; 553 case CK_BDVER3: 554 defineCPUMacros(Builder, "bdver3"); 555 break; 556 case CK_BDVER4: 557 defineCPUMacros(Builder, "bdver4"); 558 break; 559 case CK_ZNVER1: 560 defineCPUMacros(Builder, "znver1"); 561 break; 562 case CK_ZNVER2: 563 defineCPUMacros(Builder, "znver2"); 564 break; 565 case CK_ZNVER3: 566 defineCPUMacros(Builder, "znver3"); 567 break; 568 case CK_Geode: 569 defineCPUMacros(Builder, "geode"); 570 break; 571 } 572 573 // Target properties. 574 Builder.defineMacro("__REGISTER_PREFIX__", ""); 575 576 // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline 577 // functions in glibc header files that use FP Stack inline asm which the 578 // backend can't deal with (PR879). 579 Builder.defineMacro("__NO_MATH_INLINES"); 580 581 if (HasAES) 582 Builder.defineMacro("__AES__"); 583 584 if (HasVAES) 585 Builder.defineMacro("__VAES__"); 586 587 if (HasPCLMUL) 588 Builder.defineMacro("__PCLMUL__"); 589 590 if (HasVPCLMULQDQ) 591 Builder.defineMacro("__VPCLMULQDQ__"); 592 593 // Note, in 32-bit mode, GCC does not define the macro if -mno-sahf. In LLVM, 594 // the feature flag only applies to 64-bit mode. 595 if (HasLAHFSAHF || getTriple().getArch() == llvm::Triple::x86) 596 Builder.defineMacro("__LAHF_SAHF__"); 597 598 if (HasLZCNT) 599 Builder.defineMacro("__LZCNT__"); 600 601 if (HasRDRND) 602 Builder.defineMacro("__RDRND__"); 603 604 if (HasFSGSBASE) 605 Builder.defineMacro("__FSGSBASE__"); 606 607 if (HasBMI) 608 Builder.defineMacro("__BMI__"); 609 610 if (HasBMI2) 611 Builder.defineMacro("__BMI2__"); 612 613 if (HasPOPCNT) 614 Builder.defineMacro("__POPCNT__"); 615 616 if (HasRTM) 617 Builder.defineMacro("__RTM__"); 618 619 if (HasPRFCHW) 620 Builder.defineMacro("__PRFCHW__"); 621 622 if (HasRDSEED) 623 Builder.defineMacro("__RDSEED__"); 624 625 if (HasADX) 626 Builder.defineMacro("__ADX__"); 627 628 if (HasTBM) 629 Builder.defineMacro("__TBM__"); 630 631 if (HasLWP) 632 Builder.defineMacro("__LWP__"); 633 634 if (HasMWAITX) 635 Builder.defineMacro("__MWAITX__"); 636 637 if (HasMOVBE) 638 Builder.defineMacro("__MOVBE__"); 639 640 switch (XOPLevel) { 641 case XOP: 642 Builder.defineMacro("__XOP__"); 643 LLVM_FALLTHROUGH; 644 case FMA4: 645 Builder.defineMacro("__FMA4__"); 646 LLVM_FALLTHROUGH; 647 case SSE4A: 648 Builder.defineMacro("__SSE4A__"); 649 LLVM_FALLTHROUGH; 650 case NoXOP: 651 break; 652 } 653 654 if (HasFMA) 655 Builder.defineMacro("__FMA__"); 656 657 if (HasF16C) 658 Builder.defineMacro("__F16C__"); 659 660 if (HasGFNI) 661 Builder.defineMacro("__GFNI__"); 662 663 if (HasAVX512CD) 664 Builder.defineMacro("__AVX512CD__"); 665 if (HasAVX512VPOPCNTDQ) 666 Builder.defineMacro("__AVX512VPOPCNTDQ__"); 667 if (HasAVX512VNNI) 668 Builder.defineMacro("__AVX512VNNI__"); 669 if (HasAVX512BF16) 670 Builder.defineMacro("__AVX512BF16__"); 671 if (HasAVX512ER) 672 Builder.defineMacro("__AVX512ER__"); 673 if (HasAVX512PF) 674 Builder.defineMacro("__AVX512PF__"); 675 if (HasAVX512DQ) 676 Builder.defineMacro("__AVX512DQ__"); 677 if (HasAVX512BITALG) 678 Builder.defineMacro("__AVX512BITALG__"); 679 if (HasAVX512BW) 680 Builder.defineMacro("__AVX512BW__"); 681 if (HasAVX512VL) 682 Builder.defineMacro("__AVX512VL__"); 683 if (HasAVX512VBMI) 684 Builder.defineMacro("__AVX512VBMI__"); 685 if (HasAVX512VBMI2) 686 Builder.defineMacro("__AVX512VBMI2__"); 687 if (HasAVX512IFMA) 688 Builder.defineMacro("__AVX512IFMA__"); 689 if (HasAVX512VP2INTERSECT) 690 Builder.defineMacro("__AVX512VP2INTERSECT__"); 691 if (HasSHA) 692 Builder.defineMacro("__SHA__"); 693 694 if (HasFXSR) 695 Builder.defineMacro("__FXSR__"); 696 if (HasXSAVE) 697 Builder.defineMacro("__XSAVE__"); 698 if (HasXSAVEOPT) 699 Builder.defineMacro("__XSAVEOPT__"); 700 if (HasXSAVEC) 701 Builder.defineMacro("__XSAVEC__"); 702 if (HasXSAVES) 703 Builder.defineMacro("__XSAVES__"); 704 if (HasPKU) 705 Builder.defineMacro("__PKU__"); 706 if (HasCLFLUSHOPT) 707 Builder.defineMacro("__CLFLUSHOPT__"); 708 if (HasCLWB) 709 Builder.defineMacro("__CLWB__"); 710 if (HasWBNOINVD) 711 Builder.defineMacro("__WBNOINVD__"); 712 if (HasSHSTK) 713 Builder.defineMacro("__SHSTK__"); 714 if (HasSGX) 715 Builder.defineMacro("__SGX__"); 716 if (HasPREFETCHWT1) 717 Builder.defineMacro("__PREFETCHWT1__"); 718 if (HasCLZERO) 719 Builder.defineMacro("__CLZERO__"); 720 if (HasKL) 721 Builder.defineMacro("__KL__"); 722 if (HasWIDEKL) 723 Builder.defineMacro("__WIDEKL__"); 724 if (HasRDPID) 725 Builder.defineMacro("__RDPID__"); 726 if (HasCLDEMOTE) 727 Builder.defineMacro("__CLDEMOTE__"); 728 if (HasWAITPKG) 729 Builder.defineMacro("__WAITPKG__"); 730 if (HasMOVDIRI) 731 Builder.defineMacro("__MOVDIRI__"); 732 if (HasMOVDIR64B) 733 Builder.defineMacro("__MOVDIR64B__"); 734 if (HasPCONFIG) 735 Builder.defineMacro("__PCONFIG__"); 736 if (HasPTWRITE) 737 Builder.defineMacro("__PTWRITE__"); 738 if (HasINVPCID) 739 Builder.defineMacro("__INVPCID__"); 740 if (HasENQCMD) 741 Builder.defineMacro("__ENQCMD__"); 742 if (HasHRESET) 743 Builder.defineMacro("__HRESET__"); 744 if (HasAMXTILE) 745 Builder.defineMacro("__AMXTILE__"); 746 if (HasAMXINT8) 747 Builder.defineMacro("__AMXINT8__"); 748 if (HasAMXBF16) 749 Builder.defineMacro("__AMXBF16__"); 750 if (HasAVXVNNI) 751 Builder.defineMacro("__AVXVNNI__"); 752 if (HasSERIALIZE) 753 Builder.defineMacro("__SERIALIZE__"); 754 if (HasTSXLDTRK) 755 Builder.defineMacro("__TSXLDTRK__"); 756 if (HasUINTR) 757 Builder.defineMacro("__UINTR__"); 758 759 // Each case falls through to the previous one here. 760 switch (SSELevel) { 761 case AVX512F: 762 Builder.defineMacro("__AVX512F__"); 763 LLVM_FALLTHROUGH; 764 case AVX2: 765 Builder.defineMacro("__AVX2__"); 766 LLVM_FALLTHROUGH; 767 case AVX: 768 Builder.defineMacro("__AVX__"); 769 LLVM_FALLTHROUGH; 770 case SSE42: 771 Builder.defineMacro("__SSE4_2__"); 772 LLVM_FALLTHROUGH; 773 case SSE41: 774 Builder.defineMacro("__SSE4_1__"); 775 LLVM_FALLTHROUGH; 776 case SSSE3: 777 Builder.defineMacro("__SSSE3__"); 778 LLVM_FALLTHROUGH; 779 case SSE3: 780 Builder.defineMacro("__SSE3__"); 781 LLVM_FALLTHROUGH; 782 case SSE2: 783 Builder.defineMacro("__SSE2__"); 784 Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied. 785 LLVM_FALLTHROUGH; 786 case SSE1: 787 Builder.defineMacro("__SSE__"); 788 Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied. 789 LLVM_FALLTHROUGH; 790 case NoSSE: 791 break; 792 } 793 794 if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) { 795 switch (SSELevel) { 796 case AVX512F: 797 case AVX2: 798 case AVX: 799 case SSE42: 800 case SSE41: 801 case SSSE3: 802 case SSE3: 803 case SSE2: 804 Builder.defineMacro("_M_IX86_FP", Twine(2)); 805 break; 806 case SSE1: 807 Builder.defineMacro("_M_IX86_FP", Twine(1)); 808 break; 809 default: 810 Builder.defineMacro("_M_IX86_FP", Twine(0)); 811 break; 812 } 813 } 814 815 // Each case falls through to the previous one here. 816 switch (MMX3DNowLevel) { 817 case AMD3DNowAthlon: 818 Builder.defineMacro("__3dNOW_A__"); 819 LLVM_FALLTHROUGH; 820 case AMD3DNow: 821 Builder.defineMacro("__3dNOW__"); 822 LLVM_FALLTHROUGH; 823 case MMX: 824 Builder.defineMacro("__MMX__"); 825 LLVM_FALLTHROUGH; 826 case NoMMX3DNow: 827 break; 828 } 829 830 if (CPU >= CK_i486 || CPU == CK_None) { 831 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 832 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 833 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 834 } 835 if (HasCX8) 836 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 837 if (HasCX16 && getTriple().getArch() == llvm::Triple::x86_64) 838 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16"); 839 840 if (HasFloat128) 841 Builder.defineMacro("__SIZEOF_FLOAT128__", "16"); 842 } 843 844 bool X86TargetInfo::isValidFeatureName(StringRef Name) const { 845 return llvm::StringSwitch<bool>(Name) 846 .Case("3dnow", true) 847 .Case("3dnowa", true) 848 .Case("adx", true) 849 .Case("aes", true) 850 .Case("amx-bf16", true) 851 .Case("amx-int8", true) 852 .Case("amx-tile", true) 853 .Case("avx", true) 854 .Case("avx2", true) 855 .Case("avx512f", true) 856 .Case("avx512cd", true) 857 .Case("avx512vpopcntdq", true) 858 .Case("avx512vnni", true) 859 .Case("avx512bf16", true) 860 .Case("avx512er", true) 861 .Case("avx512pf", true) 862 .Case("avx512dq", true) 863 .Case("avx512bitalg", true) 864 .Case("avx512bw", true) 865 .Case("avx512vl", true) 866 .Case("avx512vbmi", true) 867 .Case("avx512vbmi2", true) 868 .Case("avx512ifma", true) 869 .Case("avx512vp2intersect", true) 870 .Case("avxvnni", true) 871 .Case("bmi", true) 872 .Case("bmi2", true) 873 .Case("cldemote", true) 874 .Case("clflushopt", true) 875 .Case("clwb", true) 876 .Case("clzero", true) 877 .Case("cx16", true) 878 .Case("enqcmd", true) 879 .Case("f16c", true) 880 .Case("fma", true) 881 .Case("fma4", true) 882 .Case("fsgsbase", true) 883 .Case("fxsr", true) 884 .Case("general-regs-only", true) 885 .Case("gfni", true) 886 .Case("hreset", true) 887 .Case("invpcid", true) 888 .Case("kl", true) 889 .Case("widekl", true) 890 .Case("lwp", true) 891 .Case("lzcnt", true) 892 .Case("mmx", true) 893 .Case("movbe", true) 894 .Case("movdiri", true) 895 .Case("movdir64b", true) 896 .Case("mwaitx", true) 897 .Case("pclmul", true) 898 .Case("pconfig", true) 899 .Case("pku", true) 900 .Case("popcnt", true) 901 .Case("prefetchwt1", true) 902 .Case("prfchw", true) 903 .Case("ptwrite", true) 904 .Case("rdpid", true) 905 .Case("rdrnd", true) 906 .Case("rdseed", true) 907 .Case("rtm", true) 908 .Case("sahf", true) 909 .Case("serialize", true) 910 .Case("sgx", true) 911 .Case("sha", true) 912 .Case("shstk", true) 913 .Case("sse", true) 914 .Case("sse2", true) 915 .Case("sse3", true) 916 .Case("ssse3", true) 917 .Case("sse4", true) 918 .Case("sse4.1", true) 919 .Case("sse4.2", true) 920 .Case("sse4a", true) 921 .Case("tbm", true) 922 .Case("tsxldtrk", true) 923 .Case("uintr", true) 924 .Case("vaes", true) 925 .Case("vpclmulqdq", true) 926 .Case("wbnoinvd", true) 927 .Case("waitpkg", true) 928 .Case("x87", true) 929 .Case("xop", true) 930 .Case("xsave", true) 931 .Case("xsavec", true) 932 .Case("xsaves", true) 933 .Case("xsaveopt", true) 934 .Default(false); 935 } 936 937 bool X86TargetInfo::hasFeature(StringRef Feature) const { 938 return llvm::StringSwitch<bool>(Feature) 939 .Case("adx", HasADX) 940 .Case("aes", HasAES) 941 .Case("amx-bf16", HasAMXBF16) 942 .Case("amx-int8", HasAMXINT8) 943 .Case("amx-tile", HasAMXTILE) 944 .Case("avxvnni", HasAVXVNNI) 945 .Case("avx", SSELevel >= AVX) 946 .Case("avx2", SSELevel >= AVX2) 947 .Case("avx512f", SSELevel >= AVX512F) 948 .Case("avx512cd", HasAVX512CD) 949 .Case("avx512vpopcntdq", HasAVX512VPOPCNTDQ) 950 .Case("avx512vnni", HasAVX512VNNI) 951 .Case("avx512bf16", HasAVX512BF16) 952 .Case("avx512er", HasAVX512ER) 953 .Case("avx512pf", HasAVX512PF) 954 .Case("avx512dq", HasAVX512DQ) 955 .Case("avx512bitalg", HasAVX512BITALG) 956 .Case("avx512bw", HasAVX512BW) 957 .Case("avx512vl", HasAVX512VL) 958 .Case("avx512vbmi", HasAVX512VBMI) 959 .Case("avx512vbmi2", HasAVX512VBMI2) 960 .Case("avx512ifma", HasAVX512IFMA) 961 .Case("avx512vp2intersect", HasAVX512VP2INTERSECT) 962 .Case("bmi", HasBMI) 963 .Case("bmi2", HasBMI2) 964 .Case("cldemote", HasCLDEMOTE) 965 .Case("clflushopt", HasCLFLUSHOPT) 966 .Case("clwb", HasCLWB) 967 .Case("clzero", HasCLZERO) 968 .Case("cx8", HasCX8) 969 .Case("cx16", HasCX16) 970 .Case("enqcmd", HasENQCMD) 971 .Case("f16c", HasF16C) 972 .Case("fma", HasFMA) 973 .Case("fma4", XOPLevel >= FMA4) 974 .Case("fsgsbase", HasFSGSBASE) 975 .Case("fxsr", HasFXSR) 976 .Case("gfni", HasGFNI) 977 .Case("hreset", HasHRESET) 978 .Case("invpcid", HasINVPCID) 979 .Case("kl", HasKL) 980 .Case("widekl", HasWIDEKL) 981 .Case("lwp", HasLWP) 982 .Case("lzcnt", HasLZCNT) 983 .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow) 984 .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon) 985 .Case("mmx", MMX3DNowLevel >= MMX) 986 .Case("movbe", HasMOVBE) 987 .Case("movdiri", HasMOVDIRI) 988 .Case("movdir64b", HasMOVDIR64B) 989 .Case("save-args", HasSaveArgs) 990 .Case("mwaitx", HasMWAITX) 991 .Case("pclmul", HasPCLMUL) 992 .Case("pconfig", HasPCONFIG) 993 .Case("pku", HasPKU) 994 .Case("popcnt", HasPOPCNT) 995 .Case("prefetchwt1", HasPREFETCHWT1) 996 .Case("prfchw", HasPRFCHW) 997 .Case("ptwrite", HasPTWRITE) 998 .Case("rdpid", HasRDPID) 999 .Case("rdrnd", HasRDRND) 1000 .Case("rdseed", HasRDSEED) 1001 .Case("retpoline-external-thunk", HasRetpolineExternalThunk) 1002 .Case("rtm", HasRTM) 1003 .Case("sahf", HasLAHFSAHF) 1004 .Case("serialize", HasSERIALIZE) 1005 .Case("sgx", HasSGX) 1006 .Case("sha", HasSHA) 1007 .Case("shstk", HasSHSTK) 1008 .Case("sse", SSELevel >= SSE1) 1009 .Case("sse2", SSELevel >= SSE2) 1010 .Case("sse3", SSELevel >= SSE3) 1011 .Case("ssse3", SSELevel >= SSSE3) 1012 .Case("sse4.1", SSELevel >= SSE41) 1013 .Case("sse4.2", SSELevel >= SSE42) 1014 .Case("sse4a", XOPLevel >= SSE4A) 1015 .Case("tbm", HasTBM) 1016 .Case("tsxldtrk", HasTSXLDTRK) 1017 .Case("uintr", HasUINTR) 1018 .Case("vaes", HasVAES) 1019 .Case("vpclmulqdq", HasVPCLMULQDQ) 1020 .Case("wbnoinvd", HasWBNOINVD) 1021 .Case("waitpkg", HasWAITPKG) 1022 .Case("x86", true) 1023 .Case("x86_32", getTriple().getArch() == llvm::Triple::x86) 1024 .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64) 1025 .Case("xop", XOPLevel >= XOP) 1026 .Case("xsave", HasXSAVE) 1027 .Case("xsavec", HasXSAVEC) 1028 .Case("xsaves", HasXSAVES) 1029 .Case("xsaveopt", HasXSAVEOPT) 1030 .Default(false); 1031 } 1032 1033 // We can't use a generic validation scheme for the features accepted here 1034 // versus subtarget features accepted in the target attribute because the 1035 // bitfield structure that's initialized in the runtime only supports the 1036 // below currently rather than the full range of subtarget features. (See 1037 // X86TargetInfo::hasFeature for a somewhat comprehensive list). 1038 bool X86TargetInfo::validateCpuSupports(StringRef FeatureStr) const { 1039 return llvm::StringSwitch<bool>(FeatureStr) 1040 #define X86_FEATURE_COMPAT(ENUM, STR) .Case(STR, true) 1041 #include "llvm/Support/X86TargetParser.def" 1042 .Default(false); 1043 } 1044 1045 static llvm::X86::ProcessorFeatures getFeature(StringRef Name) { 1046 return llvm::StringSwitch<llvm::X86::ProcessorFeatures>(Name) 1047 #define X86_FEATURE_COMPAT(ENUM, STR) .Case(STR, llvm::X86::FEATURE_##ENUM) 1048 #include "llvm/Support/X86TargetParser.def" 1049 ; 1050 // Note, this function should only be used after ensuring the value is 1051 // correct, so it asserts if the value is out of range. 1052 } 1053 1054 static unsigned getFeaturePriority(llvm::X86::ProcessorFeatures Feat) { 1055 enum class FeatPriority { 1056 #define FEATURE(FEAT) FEAT, 1057 #include "clang/Basic/X86Target.def" 1058 }; 1059 switch (Feat) { 1060 #define FEATURE(FEAT) \ 1061 case llvm::X86::FEAT: \ 1062 return static_cast<unsigned>(FeatPriority::FEAT); 1063 #include "clang/Basic/X86Target.def" 1064 default: 1065 llvm_unreachable("No Feature Priority for non-CPUSupports Features"); 1066 } 1067 } 1068 1069 unsigned X86TargetInfo::multiVersionSortPriority(StringRef Name) const { 1070 // Valid CPUs have a 'key feature' that compares just better than its key 1071 // feature. 1072 using namespace llvm::X86; 1073 CPUKind Kind = parseArchX86(Name); 1074 if (Kind != CK_None) { 1075 ProcessorFeatures KeyFeature = getKeyFeature(Kind); 1076 return (getFeaturePriority(KeyFeature) << 1) + 1; 1077 } 1078 1079 // Now we know we have a feature, so get its priority and shift it a few so 1080 // that we have sufficient room for the CPUs (above). 1081 return getFeaturePriority(getFeature(Name)) << 1; 1082 } 1083 1084 bool X86TargetInfo::validateCPUSpecificCPUDispatch(StringRef Name) const { 1085 return llvm::StringSwitch<bool>(Name) 1086 #define CPU_SPECIFIC(NAME, MANGLING, FEATURES) .Case(NAME, true) 1087 #define CPU_SPECIFIC_ALIAS(NEW_NAME, NAME) .Case(NEW_NAME, true) 1088 #include "clang/Basic/X86Target.def" 1089 .Default(false); 1090 } 1091 1092 static StringRef CPUSpecificCPUDispatchNameDealias(StringRef Name) { 1093 return llvm::StringSwitch<StringRef>(Name) 1094 #define CPU_SPECIFIC_ALIAS(NEW_NAME, NAME) .Case(NEW_NAME, NAME) 1095 #include "clang/Basic/X86Target.def" 1096 .Default(Name); 1097 } 1098 1099 char X86TargetInfo::CPUSpecificManglingCharacter(StringRef Name) const { 1100 return llvm::StringSwitch<char>(CPUSpecificCPUDispatchNameDealias(Name)) 1101 #define CPU_SPECIFIC(NAME, MANGLING, FEATURES) .Case(NAME, MANGLING) 1102 #include "clang/Basic/X86Target.def" 1103 .Default(0); 1104 } 1105 1106 void X86TargetInfo::getCPUSpecificCPUDispatchFeatures( 1107 StringRef Name, llvm::SmallVectorImpl<StringRef> &Features) const { 1108 StringRef WholeList = 1109 llvm::StringSwitch<StringRef>(CPUSpecificCPUDispatchNameDealias(Name)) 1110 #define CPU_SPECIFIC(NAME, MANGLING, FEATURES) .Case(NAME, FEATURES) 1111 #include "clang/Basic/X86Target.def" 1112 .Default(""); 1113 WholeList.split(Features, ',', /*MaxSplit=*/-1, /*KeepEmpty=*/false); 1114 } 1115 1116 // We can't use a generic validation scheme for the cpus accepted here 1117 // versus subtarget cpus accepted in the target attribute because the 1118 // variables intitialized by the runtime only support the below currently 1119 // rather than the full range of cpus. 1120 bool X86TargetInfo::validateCpuIs(StringRef FeatureStr) const { 1121 return llvm::StringSwitch<bool>(FeatureStr) 1122 #define X86_VENDOR(ENUM, STRING) .Case(STRING, true) 1123 #define X86_CPU_TYPE_ALIAS(ENUM, ALIAS) .Case(ALIAS, true) 1124 #define X86_CPU_TYPE(ENUM, STR) .Case(STR, true) 1125 #define X86_CPU_SUBTYPE(ENUM, STR) .Case(STR, true) 1126 #include "llvm/Support/X86TargetParser.def" 1127 .Default(false); 1128 } 1129 1130 static unsigned matchAsmCCConstraint(const char *&Name) { 1131 auto RV = llvm::StringSwitch<unsigned>(Name) 1132 .Case("@cca", 4) 1133 .Case("@ccae", 5) 1134 .Case("@ccb", 4) 1135 .Case("@ccbe", 5) 1136 .Case("@ccc", 4) 1137 .Case("@cce", 4) 1138 .Case("@ccz", 4) 1139 .Case("@ccg", 4) 1140 .Case("@ccge", 5) 1141 .Case("@ccl", 4) 1142 .Case("@ccle", 5) 1143 .Case("@ccna", 5) 1144 .Case("@ccnae", 6) 1145 .Case("@ccnb", 5) 1146 .Case("@ccnbe", 6) 1147 .Case("@ccnc", 5) 1148 .Case("@ccne", 5) 1149 .Case("@ccnz", 5) 1150 .Case("@ccng", 5) 1151 .Case("@ccnge", 6) 1152 .Case("@ccnl", 5) 1153 .Case("@ccnle", 6) 1154 .Case("@ccno", 5) 1155 .Case("@ccnp", 5) 1156 .Case("@ccns", 5) 1157 .Case("@cco", 4) 1158 .Case("@ccp", 4) 1159 .Case("@ccs", 4) 1160 .Default(0); 1161 return RV; 1162 } 1163 1164 bool X86TargetInfo::validateAsmConstraint( 1165 const char *&Name, TargetInfo::ConstraintInfo &Info) const { 1166 switch (*Name) { 1167 default: 1168 return false; 1169 // Constant constraints. 1170 case 'e': // 32-bit signed integer constant for use with sign-extending x86_64 1171 // instructions. 1172 case 'Z': // 32-bit unsigned integer constant for use with zero-extending 1173 // x86_64 instructions. 1174 case 's': 1175 Info.setRequiresImmediate(); 1176 return true; 1177 case 'I': 1178 Info.setRequiresImmediate(0, 31); 1179 return true; 1180 case 'J': 1181 Info.setRequiresImmediate(0, 63); 1182 return true; 1183 case 'K': 1184 Info.setRequiresImmediate(-128, 127); 1185 return true; 1186 case 'L': 1187 Info.setRequiresImmediate({int(0xff), int(0xffff), int(0xffffffff)}); 1188 return true; 1189 case 'M': 1190 Info.setRequiresImmediate(0, 3); 1191 return true; 1192 case 'N': 1193 Info.setRequiresImmediate(0, 255); 1194 return true; 1195 case 'O': 1196 Info.setRequiresImmediate(0, 127); 1197 return true; 1198 // Register constraints. 1199 case 'Y': // 'Y' is the first character for several 2-character constraints. 1200 // Shift the pointer to the second character of the constraint. 1201 Name++; 1202 switch (*Name) { 1203 default: 1204 return false; 1205 case 'z': // First SSE register. 1206 case '2': 1207 case 't': // Any SSE register, when SSE2 is enabled. 1208 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled. 1209 case 'm': // Any MMX register, when inter-unit moves enabled. 1210 case 'k': // AVX512 arch mask registers: k1-k7. 1211 Info.setAllowsRegister(); 1212 return true; 1213 } 1214 case 'f': // Any x87 floating point stack register. 1215 // Constraint 'f' cannot be used for output operands. 1216 if (Info.ConstraintStr[0] == '=') 1217 return false; 1218 Info.setAllowsRegister(); 1219 return true; 1220 case 'a': // eax. 1221 case 'b': // ebx. 1222 case 'c': // ecx. 1223 case 'd': // edx. 1224 case 'S': // esi. 1225 case 'D': // edi. 1226 case 'A': // edx:eax. 1227 case 't': // Top of floating point stack. 1228 case 'u': // Second from top of floating point stack. 1229 case 'q': // Any register accessible as [r]l: a, b, c, and d. 1230 case 'y': // Any MMX register. 1231 case 'v': // Any {X,Y,Z}MM register (Arch & context dependent) 1232 case 'x': // Any SSE register. 1233 case 'k': // Any AVX512 mask register (same as Yk, additionally allows k0 1234 // for intermideate k reg operations). 1235 case 'Q': // Any register accessible as [r]h: a, b, c, and d. 1236 case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp. 1237 case 'l': // "Index" registers: any general register that can be used as an 1238 // index in a base+index memory access. 1239 Info.setAllowsRegister(); 1240 return true; 1241 // Floating point constant constraints. 1242 case 'C': // SSE floating point constant. 1243 case 'G': // x87 floating point constant. 1244 return true; 1245 case '@': 1246 // CC condition changes. 1247 if (auto Len = matchAsmCCConstraint(Name)) { 1248 Name += Len - 1; 1249 Info.setAllowsRegister(); 1250 return true; 1251 } 1252 return false; 1253 } 1254 } 1255 1256 // Below is based on the following information: 1257 // +------------------------------------+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ 1258 // | Processor Name | Cache Line Size (Bytes) | Source | 1259 // +------------------------------------+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ 1260 // | i386 | 64 | https://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-optimization-manual.pdf | 1261 // | i486 | 16 | "four doublewords" (doubleword = 32 bits, 4 bits * 32 bits = 16 bytes) https://en.wikichip.org/w/images/d/d3/i486_MICROPROCESSOR_HARDWARE_REFERENCE_MANUAL_%281990%29.pdf and http://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.126.4216&rep=rep1&type=pdf (page 29) | 1262 // | i586/Pentium MMX | 32 | https://www.7-cpu.com/cpu/P-MMX.html | 1263 // | i686/Pentium | 32 | https://www.7-cpu.com/cpu/P6.html | 1264 // | Netburst/Pentium4 | 64 | https://www.7-cpu.com/cpu/P4-180.html | 1265 // | Atom | 64 | https://www.7-cpu.com/cpu/Atom.html | 1266 // | Westmere | 64 | https://en.wikichip.org/wiki/intel/microarchitectures/sandy_bridge_(client) "Cache Architecture" | 1267 // | Sandy Bridge | 64 | https://en.wikipedia.org/wiki/Sandy_Bridge and https://www.7-cpu.com/cpu/SandyBridge.html | 1268 // | Ivy Bridge | 64 | https://blog.stuffedcow.net/2013/01/ivb-cache-replacement/ and https://www.7-cpu.com/cpu/IvyBridge.html | 1269 // | Haswell | 64 | https://www.7-cpu.com/cpu/Haswell.html | 1270 // | Boadwell | 64 | https://www.7-cpu.com/cpu/Broadwell.html | 1271 // | Skylake (including skylake-avx512) | 64 | https://www.nas.nasa.gov/hecc/support/kb/skylake-processors_550.html "Cache Hierarchy" | 1272 // | Cascade Lake | 64 | https://www.nas.nasa.gov/hecc/support/kb/cascade-lake-processors_579.html "Cache Hierarchy" | 1273 // | Skylake | 64 | https://en.wikichip.org/wiki/intel/microarchitectures/kaby_lake "Memory Hierarchy" | 1274 // | Ice Lake | 64 | https://www.7-cpu.com/cpu/Ice_Lake.html | 1275 // | Knights Landing | 64 | https://software.intel.com/en-us/articles/intel-xeon-phi-processor-7200-family-memory-management-optimizations "The Intel® Xeon Phi™ Processor Architecture" | 1276 // | Knights Mill | 64 | https://software.intel.com/sites/default/files/managed/9e/bc/64-ia-32-architectures-optimization-manual.pdf?countrylabel=Colombia "2.5.5.2 L1 DCache " | 1277 // +------------------------------------+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ 1278 Optional<unsigned> X86TargetInfo::getCPUCacheLineSize() const { 1279 using namespace llvm::X86; 1280 switch (CPU) { 1281 // i386 1282 case CK_i386: 1283 // i486 1284 case CK_i486: 1285 case CK_WinChipC6: 1286 case CK_WinChip2: 1287 case CK_C3: 1288 // Lakemont 1289 case CK_Lakemont: 1290 return 16; 1291 1292 // i586 1293 case CK_i586: 1294 case CK_Pentium: 1295 case CK_PentiumMMX: 1296 // i686 1297 case CK_PentiumPro: 1298 case CK_i686: 1299 case CK_Pentium2: 1300 case CK_Pentium3: 1301 case CK_PentiumM: 1302 case CK_C3_2: 1303 // K6 1304 case CK_K6: 1305 case CK_K6_2: 1306 case CK_K6_3: 1307 // Geode 1308 case CK_Geode: 1309 return 32; 1310 1311 // Netburst 1312 case CK_Pentium4: 1313 case CK_Prescott: 1314 case CK_Nocona: 1315 // Atom 1316 case CK_Bonnell: 1317 case CK_Silvermont: 1318 case CK_Goldmont: 1319 case CK_GoldmontPlus: 1320 case CK_Tremont: 1321 1322 case CK_Westmere: 1323 case CK_SandyBridge: 1324 case CK_IvyBridge: 1325 case CK_Haswell: 1326 case CK_Broadwell: 1327 case CK_SkylakeClient: 1328 case CK_SkylakeServer: 1329 case CK_Cascadelake: 1330 case CK_Nehalem: 1331 case CK_Cooperlake: 1332 case CK_Cannonlake: 1333 case CK_Tigerlake: 1334 case CK_SapphireRapids: 1335 case CK_IcelakeClient: 1336 case CK_Rocketlake: 1337 case CK_IcelakeServer: 1338 case CK_Alderlake: 1339 case CK_KNL: 1340 case CK_KNM: 1341 // K7 1342 case CK_Athlon: 1343 case CK_AthlonXP: 1344 // K8 1345 case CK_K8: 1346 case CK_K8SSE3: 1347 case CK_AMDFAM10: 1348 // Bobcat 1349 case CK_BTVER1: 1350 case CK_BTVER2: 1351 // Bulldozer 1352 case CK_BDVER1: 1353 case CK_BDVER2: 1354 case CK_BDVER3: 1355 case CK_BDVER4: 1356 // Zen 1357 case CK_ZNVER1: 1358 case CK_ZNVER2: 1359 case CK_ZNVER3: 1360 // Deprecated 1361 case CK_x86_64: 1362 case CK_x86_64_v2: 1363 case CK_x86_64_v3: 1364 case CK_x86_64_v4: 1365 case CK_Yonah: 1366 case CK_Penryn: 1367 case CK_Core2: 1368 return 64; 1369 1370 // The following currently have unknown cache line sizes (but they are probably all 64): 1371 // Core 1372 case CK_None: 1373 return None; 1374 } 1375 llvm_unreachable("Unknown CPU kind"); 1376 } 1377 1378 bool X86TargetInfo::validateOutputSize(const llvm::StringMap<bool> &FeatureMap, 1379 StringRef Constraint, 1380 unsigned Size) const { 1381 // Strip off constraint modifiers. 1382 while (Constraint[0] == '=' || Constraint[0] == '+' || Constraint[0] == '&') 1383 Constraint = Constraint.substr(1); 1384 1385 return validateOperandSize(FeatureMap, Constraint, Size); 1386 } 1387 1388 bool X86TargetInfo::validateInputSize(const llvm::StringMap<bool> &FeatureMap, 1389 StringRef Constraint, 1390 unsigned Size) const { 1391 return validateOperandSize(FeatureMap, Constraint, Size); 1392 } 1393 1394 bool X86TargetInfo::validateOperandSize(const llvm::StringMap<bool> &FeatureMap, 1395 StringRef Constraint, 1396 unsigned Size) const { 1397 switch (Constraint[0]) { 1398 default: 1399 break; 1400 case 'k': 1401 // Registers k0-k7 (AVX512) size limit is 64 bit. 1402 case 'y': 1403 return Size <= 64; 1404 case 'f': 1405 case 't': 1406 case 'u': 1407 return Size <= 128; 1408 case 'Y': 1409 // 'Y' is the first character for several 2-character constraints. 1410 switch (Constraint[1]) { 1411 default: 1412 return false; 1413 case 'm': 1414 // 'Ym' is synonymous with 'y'. 1415 case 'k': 1416 return Size <= 64; 1417 case 'z': 1418 // XMM0/YMM/ZMM0 1419 if (hasFeatureEnabled(FeatureMap, "avx512f")) 1420 // ZMM0 can be used if target supports AVX512F. 1421 return Size <= 512U; 1422 else if (hasFeatureEnabled(FeatureMap, "avx")) 1423 // YMM0 can be used if target supports AVX. 1424 return Size <= 256U; 1425 else if (hasFeatureEnabled(FeatureMap, "sse")) 1426 return Size <= 128U; 1427 return false; 1428 case 'i': 1429 case 't': 1430 case '2': 1431 // 'Yi','Yt','Y2' are synonymous with 'x' when SSE2 is enabled. 1432 if (SSELevel < SSE2) 1433 return false; 1434 break; 1435 } 1436 break; 1437 case 'v': 1438 case 'x': 1439 if (hasFeatureEnabled(FeatureMap, "avx512f")) 1440 // 512-bit zmm registers can be used if target supports AVX512F. 1441 return Size <= 512U; 1442 else if (hasFeatureEnabled(FeatureMap, "avx")) 1443 // 256-bit ymm registers can be used if target supports AVX. 1444 return Size <= 256U; 1445 return Size <= 128U; 1446 1447 } 1448 1449 return true; 1450 } 1451 1452 std::string X86TargetInfo::convertConstraint(const char *&Constraint) const { 1453 switch (*Constraint) { 1454 case '@': 1455 if (auto Len = matchAsmCCConstraint(Constraint)) { 1456 std::string Converted = "{" + std::string(Constraint, Len) + "}"; 1457 Constraint += Len - 1; 1458 return Converted; 1459 } 1460 return std::string(1, *Constraint); 1461 case 'a': 1462 return std::string("{ax}"); 1463 case 'b': 1464 return std::string("{bx}"); 1465 case 'c': 1466 return std::string("{cx}"); 1467 case 'd': 1468 return std::string("{dx}"); 1469 case 'S': 1470 return std::string("{si}"); 1471 case 'D': 1472 return std::string("{di}"); 1473 case 'p': // address 1474 return std::string("im"); 1475 case 't': // top of floating point stack. 1476 return std::string("{st}"); 1477 case 'u': // second from top of floating point stack. 1478 return std::string("{st(1)}"); // second from top of floating point stack. 1479 case 'Y': 1480 switch (Constraint[1]) { 1481 default: 1482 // Break from inner switch and fall through (copy single char), 1483 // continue parsing after copying the current constraint into 1484 // the return string. 1485 break; 1486 case 'k': 1487 case 'm': 1488 case 'i': 1489 case 't': 1490 case 'z': 1491 case '2': 1492 // "^" hints llvm that this is a 2 letter constraint. 1493 // "Constraint++" is used to promote the string iterator 1494 // to the next constraint. 1495 return std::string("^") + std::string(Constraint++, 2); 1496 } 1497 LLVM_FALLTHROUGH; 1498 default: 1499 return std::string(1, *Constraint); 1500 } 1501 } 1502 1503 void X86TargetInfo::fillValidCPUList(SmallVectorImpl<StringRef> &Values) const { 1504 bool Only64Bit = getTriple().getArch() != llvm::Triple::x86; 1505 llvm::X86::fillValidCPUArchList(Values, Only64Bit); 1506 } 1507 1508 void X86TargetInfo::fillValidTuneCPUList(SmallVectorImpl<StringRef> &Values) const { 1509 llvm::X86::fillValidTuneCPUList(Values); 1510 } 1511 1512 ArrayRef<const char *> X86TargetInfo::getGCCRegNames() const { 1513 return llvm::makeArrayRef(GCCRegNames); 1514 } 1515 1516 ArrayRef<TargetInfo::AddlRegName> X86TargetInfo::getGCCAddlRegNames() const { 1517 return llvm::makeArrayRef(AddlRegNames); 1518 } 1519 1520 ArrayRef<Builtin::Info> X86_32TargetInfo::getTargetBuiltins() const { 1521 return llvm::makeArrayRef(BuiltinInfoX86, clang::X86::LastX86CommonBuiltin - 1522 Builtin::FirstTSBuiltin + 1); 1523 } 1524 1525 ArrayRef<Builtin::Info> X86_64TargetInfo::getTargetBuiltins() const { 1526 return llvm::makeArrayRef(BuiltinInfoX86, 1527 X86::LastTSBuiltin - Builtin::FirstTSBuiltin); 1528 } 1529