1 //===--- X86.cpp - Implement X86 target feature support -------------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file implements X86 TargetInfo objects. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "X86.h" 14 #include "clang/Basic/Builtins.h" 15 #include "clang/Basic/Diagnostic.h" 16 #include "clang/Basic/TargetBuiltins.h" 17 #include "llvm/ADT/StringExtras.h" 18 #include "llvm/ADT/StringRef.h" 19 #include "llvm/ADT/StringSwitch.h" 20 #include "llvm/Support/X86TargetParser.h" 21 22 namespace clang { 23 namespace targets { 24 25 const Builtin::Info BuiltinInfoX86[] = { 26 #define BUILTIN(ID, TYPE, ATTRS) \ 27 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr}, 28 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 29 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE}, 30 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \ 31 {#ID, TYPE, ATTRS, HEADER, LANGS, FEATURE}, 32 #include "clang/Basic/BuiltinsX86.def" 33 34 #define BUILTIN(ID, TYPE, ATTRS) \ 35 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr}, 36 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 37 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE}, 38 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \ 39 {#ID, TYPE, ATTRS, HEADER, LANGS, FEATURE}, 40 #include "clang/Basic/BuiltinsX86_64.def" 41 }; 42 43 static const char *const GCCRegNames[] = { 44 "ax", "dx", "cx", "bx", "si", "di", "bp", "sp", 45 "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)", 46 "argp", "flags", "fpcr", "fpsr", "dirflag", "frame", "xmm0", "xmm1", 47 "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", "mm0", "mm1", 48 "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", "r8", "r9", 49 "r10", "r11", "r12", "r13", "r14", "r15", "xmm8", "xmm9", 50 "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", "ymm0", "ymm1", 51 "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7", "ymm8", "ymm9", 52 "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15", "xmm16", "xmm17", 53 "xmm18", "xmm19", "xmm20", "xmm21", "xmm22", "xmm23", "xmm24", "xmm25", 54 "xmm26", "xmm27", "xmm28", "xmm29", "xmm30", "xmm31", "ymm16", "ymm17", 55 "ymm18", "ymm19", "ymm20", "ymm21", "ymm22", "ymm23", "ymm24", "ymm25", 56 "ymm26", "ymm27", "ymm28", "ymm29", "ymm30", "ymm31", "zmm0", "zmm1", 57 "zmm2", "zmm3", "zmm4", "zmm5", "zmm6", "zmm7", "zmm8", "zmm9", 58 "zmm10", "zmm11", "zmm12", "zmm13", "zmm14", "zmm15", "zmm16", "zmm17", 59 "zmm18", "zmm19", "zmm20", "zmm21", "zmm22", "zmm23", "zmm24", "zmm25", 60 "zmm26", "zmm27", "zmm28", "zmm29", "zmm30", "zmm31", "k0", "k1", 61 "k2", "k3", "k4", "k5", "k6", "k7", 62 "cr0", "cr2", "cr3", "cr4", "cr8", 63 "dr0", "dr1", "dr2", "dr3", "dr6", "dr7", 64 "bnd0", "bnd1", "bnd2", "bnd3", 65 "tmm0", "tmm1", "tmm2", "tmm3", "tmm4", "tmm5", "tmm6", "tmm7", 66 }; 67 68 const TargetInfo::AddlRegName AddlRegNames[] = { 69 {{"al", "ah", "eax", "rax"}, 0}, 70 {{"bl", "bh", "ebx", "rbx"}, 3}, 71 {{"cl", "ch", "ecx", "rcx"}, 2}, 72 {{"dl", "dh", "edx", "rdx"}, 1}, 73 {{"esi", "rsi"}, 4}, 74 {{"edi", "rdi"}, 5}, 75 {{"esp", "rsp"}, 7}, 76 {{"ebp", "rbp"}, 6}, 77 {{"r8d", "r8w", "r8b"}, 38}, 78 {{"r9d", "r9w", "r9b"}, 39}, 79 {{"r10d", "r10w", "r10b"}, 40}, 80 {{"r11d", "r11w", "r11b"}, 41}, 81 {{"r12d", "r12w", "r12b"}, 42}, 82 {{"r13d", "r13w", "r13b"}, 43}, 83 {{"r14d", "r14w", "r14b"}, 44}, 84 {{"r15d", "r15w", "r15b"}, 45}, 85 }; 86 87 } // namespace targets 88 } // namespace clang 89 90 using namespace clang; 91 using namespace clang::targets; 92 93 bool X86TargetInfo::setFPMath(StringRef Name) { 94 if (Name == "387") { 95 FPMath = FP_387; 96 return true; 97 } 98 if (Name == "sse") { 99 FPMath = FP_SSE; 100 return true; 101 } 102 return false; 103 } 104 105 bool X86TargetInfo::initFeatureMap( 106 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU, 107 const std::vector<std::string> &FeaturesVec) const { 108 // FIXME: This *really* should not be here. 109 // X86_64 always has SSE2. 110 if (getTriple().getArch() == llvm::Triple::x86_64) 111 setFeatureEnabled(Features, "sse2", true); 112 113 using namespace llvm::X86; 114 115 SmallVector<StringRef, 16> CPUFeatures; 116 getFeaturesForCPU(CPU, CPUFeatures); 117 for (auto &F : CPUFeatures) 118 setFeatureEnabled(Features, F, true); 119 120 if (!TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec)) 121 return false; 122 123 // Can't do this earlier because we need to be able to explicitly enable 124 // or disable these features and the things that they depend upon. 125 126 // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled. 127 auto I = Features.find("sse4.2"); 128 if (I != Features.end() && I->getValue() && 129 llvm::find(FeaturesVec, "-popcnt") == FeaturesVec.end()) 130 Features["popcnt"] = true; 131 132 // Additionally, if SSE is enabled and mmx is not explicitly disabled, 133 // then enable MMX. 134 I = Features.find("sse"); 135 if (I != Features.end() && I->getValue() && 136 llvm::find(FeaturesVec, "-mmx") == FeaturesVec.end()) 137 Features["mmx"] = true; 138 139 // Enable xsave if avx is enabled and xsave is not explicitly disabled. 140 I = Features.find("avx"); 141 if (I != Features.end() && I->getValue() && 142 llvm::find(FeaturesVec, "-xsave") == FeaturesVec.end()) 143 Features["xsave"] = true; 144 145 return true; 146 } 147 148 void X86TargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features, 149 StringRef Name, bool Enabled) const { 150 if (Name == "sse4") { 151 // We can get here via the __target__ attribute since that's not controlled 152 // via the -msse4/-mno-sse4 command line alias. Handle this the same way 153 // here - turn on the sse4.2 if enabled, turn off the sse4.1 level if 154 // disabled. 155 if (Enabled) 156 Name = "sse4.2"; 157 else 158 Name = "sse4.1"; 159 } 160 161 Features[Name] = Enabled; 162 163 SmallVector<StringRef, 8> ImpliedFeatures; 164 llvm::X86::getImpliedFeatures(Name, Enabled, ImpliedFeatures); 165 for (const auto &F : ImpliedFeatures) 166 Features[F] = Enabled; 167 } 168 169 /// handleTargetFeatures - Perform initialization based on the user 170 /// configured set of features. 171 bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 172 DiagnosticsEngine &Diags) { 173 for (const auto &Feature : Features) { 174 if (Feature[0] != '+') 175 continue; 176 177 if (Feature == "+aes") { 178 HasAES = true; 179 } else if (Feature == "+vaes") { 180 HasVAES = true; 181 } else if (Feature == "+pclmul") { 182 HasPCLMUL = true; 183 } else if (Feature == "+vpclmulqdq") { 184 HasVPCLMULQDQ = true; 185 } else if (Feature == "+lzcnt") { 186 HasLZCNT = true; 187 } else if (Feature == "+rdrnd") { 188 HasRDRND = true; 189 } else if (Feature == "+fsgsbase") { 190 HasFSGSBASE = true; 191 } else if (Feature == "+bmi") { 192 HasBMI = true; 193 } else if (Feature == "+bmi2") { 194 HasBMI2 = true; 195 } else if (Feature == "+popcnt") { 196 HasPOPCNT = true; 197 } else if (Feature == "+rtm") { 198 HasRTM = true; 199 } else if (Feature == "+prfchw") { 200 HasPRFCHW = true; 201 } else if (Feature == "+rdseed") { 202 HasRDSEED = true; 203 } else if (Feature == "+adx") { 204 HasADX = true; 205 } else if (Feature == "+tbm") { 206 HasTBM = true; 207 } else if (Feature == "+lwp") { 208 HasLWP = true; 209 } else if (Feature == "+fma") { 210 HasFMA = true; 211 } else if (Feature == "+f16c") { 212 HasF16C = true; 213 } else if (Feature == "+gfni") { 214 HasGFNI = true; 215 } else if (Feature == "+avx512cd") { 216 HasAVX512CD = true; 217 } else if (Feature == "+avx512vpopcntdq") { 218 HasAVX512VPOPCNTDQ = true; 219 } else if (Feature == "+avx512vnni") { 220 HasAVX512VNNI = true; 221 } else if (Feature == "+avx512bf16") { 222 HasAVX512BF16 = true; 223 } else if (Feature == "+avx512er") { 224 HasAVX512ER = true; 225 } else if (Feature == "+avx512pf") { 226 HasAVX512PF = true; 227 } else if (Feature == "+avx512dq") { 228 HasAVX512DQ = true; 229 } else if (Feature == "+avx512bitalg") { 230 HasAVX512BITALG = true; 231 } else if (Feature == "+avx512bw") { 232 HasAVX512BW = true; 233 } else if (Feature == "+avx512vl") { 234 HasAVX512VL = true; 235 } else if (Feature == "+avx512vbmi") { 236 HasAVX512VBMI = true; 237 } else if (Feature == "+avx512vbmi2") { 238 HasAVX512VBMI2 = true; 239 } else if (Feature == "+avx512ifma") { 240 HasAVX512IFMA = true; 241 } else if (Feature == "+avx512vp2intersect") { 242 HasAVX512VP2INTERSECT = true; 243 } else if (Feature == "+sha") { 244 HasSHA = true; 245 } else if (Feature == "+shstk") { 246 HasSHSTK = true; 247 } else if (Feature == "+movbe") { 248 HasMOVBE = true; 249 } else if (Feature == "+sgx") { 250 HasSGX = true; 251 } else if (Feature == "+cx8") { 252 HasCX8 = true; 253 } else if (Feature == "+cx16") { 254 HasCX16 = true; 255 } else if (Feature == "+fxsr") { 256 HasFXSR = true; 257 } else if (Feature == "+xsave") { 258 HasXSAVE = true; 259 } else if (Feature == "+xsaveopt") { 260 HasXSAVEOPT = true; 261 } else if (Feature == "+xsavec") { 262 HasXSAVEC = true; 263 } else if (Feature == "+xsaves") { 264 HasXSAVES = true; 265 } else if (Feature == "+mwaitx") { 266 HasMWAITX = true; 267 } else if (Feature == "+pku") { 268 HasPKU = true; 269 } else if (Feature == "+clflushopt") { 270 HasCLFLUSHOPT = true; 271 } else if (Feature == "+clwb") { 272 HasCLWB = true; 273 } else if (Feature == "+wbnoinvd") { 274 HasWBNOINVD = true; 275 } else if (Feature == "+prefetchwt1") { 276 HasPREFETCHWT1 = true; 277 } else if (Feature == "+clzero") { 278 HasCLZERO = true; 279 } else if (Feature == "+cldemote") { 280 HasCLDEMOTE = true; 281 } else if (Feature == "+rdpid") { 282 HasRDPID = true; 283 } else if (Feature == "+retpoline-external-thunk") { 284 HasRetpolineExternalThunk = true; 285 } else if (Feature == "+sahf") { 286 HasLAHFSAHF = true; 287 } else if (Feature == "+waitpkg") { 288 HasWAITPKG = true; 289 } else if (Feature == "+movdiri") { 290 HasMOVDIRI = true; 291 } else if (Feature == "+movdir64b") { 292 HasMOVDIR64B = true; 293 } else if (Feature == "+pconfig") { 294 HasPCONFIG = true; 295 } else if (Feature == "+ptwrite") { 296 HasPTWRITE = true; 297 } else if (Feature == "+invpcid") { 298 HasINVPCID = true; 299 } else if (Feature == "+save-args") { 300 HasSaveArgs = true; 301 } else if (Feature == "+enqcmd") { 302 HasENQCMD = true; 303 } else if (Feature == "+amx-bf16") { 304 HasAMXBF16 = true; 305 } else if (Feature == "+amx-int8") { 306 HasAMXINT8 = true; 307 } else if (Feature == "+amx-tile") { 308 HasAMXTILE = true; 309 } else if (Feature == "+serialize") { 310 HasSERIALIZE = true; 311 } else if (Feature == "+tsxldtrk") { 312 HasTSXLDTRK = true; 313 } 314 315 X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature) 316 .Case("+avx512f", AVX512F) 317 .Case("+avx2", AVX2) 318 .Case("+avx", AVX) 319 .Case("+sse4.2", SSE42) 320 .Case("+sse4.1", SSE41) 321 .Case("+ssse3", SSSE3) 322 .Case("+sse3", SSE3) 323 .Case("+sse2", SSE2) 324 .Case("+sse", SSE1) 325 .Default(NoSSE); 326 SSELevel = std::max(SSELevel, Level); 327 328 MMX3DNowEnum ThreeDNowLevel = llvm::StringSwitch<MMX3DNowEnum>(Feature) 329 .Case("+3dnowa", AMD3DNowAthlon) 330 .Case("+3dnow", AMD3DNow) 331 .Case("+mmx", MMX) 332 .Default(NoMMX3DNow); 333 MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel); 334 335 XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature) 336 .Case("+xop", XOP) 337 .Case("+fma4", FMA4) 338 .Case("+sse4a", SSE4A) 339 .Default(NoXOP); 340 XOPLevel = std::max(XOPLevel, XLevel); 341 } 342 343 // LLVM doesn't have a separate switch for fpmath, so only accept it if it 344 // matches the selected sse level. 345 if ((FPMath == FP_SSE && SSELevel < SSE1) || 346 (FPMath == FP_387 && SSELevel >= SSE1)) { 347 Diags.Report(diag::err_target_unsupported_fpmath) 348 << (FPMath == FP_SSE ? "sse" : "387"); 349 return false; 350 } 351 352 SimdDefaultAlign = 353 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 354 return true; 355 } 356 357 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro 358 /// definitions for this particular subtarget. 359 void X86TargetInfo::getTargetDefines(const LangOptions &Opts, 360 MacroBuilder &Builder) const { 361 // Inline assembly supports X86 flag outputs. 362 Builder.defineMacro("__GCC_ASM_FLAG_OUTPUTS__"); 363 364 std::string CodeModel = getTargetOpts().CodeModel; 365 if (CodeModel == "default") 366 CodeModel = "small"; 367 Builder.defineMacro("__code_model_" + CodeModel + "__"); 368 369 // Target identification. 370 if (getTriple().getArch() == llvm::Triple::x86_64) { 371 Builder.defineMacro("__amd64__"); 372 Builder.defineMacro("__amd64"); 373 Builder.defineMacro("__x86_64"); 374 Builder.defineMacro("__x86_64__"); 375 if (getTriple().getArchName() == "x86_64h") { 376 Builder.defineMacro("__x86_64h"); 377 Builder.defineMacro("__x86_64h__"); 378 } 379 } else { 380 DefineStd(Builder, "i386", Opts); 381 } 382 383 Builder.defineMacro("__SEG_GS"); 384 Builder.defineMacro("__SEG_FS"); 385 Builder.defineMacro("__seg_gs", "__attribute__((address_space(256)))"); 386 Builder.defineMacro("__seg_fs", "__attribute__((address_space(257)))"); 387 388 // Subtarget options. 389 // FIXME: We are hard-coding the tune parameters based on the CPU, but they 390 // truly should be based on -mtune options. 391 using namespace llvm::X86; 392 switch (CPU) { 393 case CK_None: 394 break; 395 case CK_i386: 396 // The rest are coming from the i386 define above. 397 Builder.defineMacro("__tune_i386__"); 398 break; 399 case CK_i486: 400 case CK_WinChipC6: 401 case CK_WinChip2: 402 case CK_C3: 403 defineCPUMacros(Builder, "i486"); 404 break; 405 case CK_PentiumMMX: 406 Builder.defineMacro("__pentium_mmx__"); 407 Builder.defineMacro("__tune_pentium_mmx__"); 408 LLVM_FALLTHROUGH; 409 case CK_i586: 410 case CK_Pentium: 411 defineCPUMacros(Builder, "i586"); 412 defineCPUMacros(Builder, "pentium"); 413 break; 414 case CK_Pentium3: 415 case CK_PentiumM: 416 Builder.defineMacro("__tune_pentium3__"); 417 LLVM_FALLTHROUGH; 418 case CK_Pentium2: 419 case CK_C3_2: 420 Builder.defineMacro("__tune_pentium2__"); 421 LLVM_FALLTHROUGH; 422 case CK_PentiumPro: 423 case CK_i686: 424 defineCPUMacros(Builder, "i686"); 425 defineCPUMacros(Builder, "pentiumpro"); 426 break; 427 case CK_Pentium4: 428 defineCPUMacros(Builder, "pentium4"); 429 break; 430 case CK_Yonah: 431 case CK_Prescott: 432 case CK_Nocona: 433 defineCPUMacros(Builder, "nocona"); 434 break; 435 case CK_Core2: 436 case CK_Penryn: 437 defineCPUMacros(Builder, "core2"); 438 break; 439 case CK_Bonnell: 440 defineCPUMacros(Builder, "atom"); 441 break; 442 case CK_Silvermont: 443 defineCPUMacros(Builder, "slm"); 444 break; 445 case CK_Goldmont: 446 defineCPUMacros(Builder, "goldmont"); 447 break; 448 case CK_GoldmontPlus: 449 defineCPUMacros(Builder, "goldmont_plus"); 450 break; 451 case CK_Tremont: 452 defineCPUMacros(Builder, "tremont"); 453 break; 454 case CK_Nehalem: 455 case CK_Westmere: 456 case CK_SandyBridge: 457 case CK_IvyBridge: 458 case CK_Haswell: 459 case CK_Broadwell: 460 case CK_SkylakeClient: 461 case CK_SkylakeServer: 462 case CK_Cascadelake: 463 case CK_Cooperlake: 464 case CK_Cannonlake: 465 case CK_IcelakeClient: 466 case CK_IcelakeServer: 467 case CK_Tigerlake: 468 // FIXME: Historically, we defined this legacy name, it would be nice to 469 // remove it at some point. We've never exposed fine-grained names for 470 // recent primary x86 CPUs, and we should keep it that way. 471 defineCPUMacros(Builder, "corei7"); 472 break; 473 case CK_KNL: 474 defineCPUMacros(Builder, "knl"); 475 break; 476 case CK_KNM: 477 break; 478 case CK_Lakemont: 479 defineCPUMacros(Builder, "i586", /*Tuning*/false); 480 defineCPUMacros(Builder, "pentium", /*Tuning*/false); 481 Builder.defineMacro("__tune_lakemont__"); 482 break; 483 case CK_K6_2: 484 Builder.defineMacro("__k6_2__"); 485 Builder.defineMacro("__tune_k6_2__"); 486 LLVM_FALLTHROUGH; 487 case CK_K6_3: 488 if (CPU != CK_K6_2) { // In case of fallthrough 489 // FIXME: GCC may be enabling these in cases where some other k6 490 // architecture is specified but -m3dnow is explicitly provided. The 491 // exact semantics need to be determined and emulated here. 492 Builder.defineMacro("__k6_3__"); 493 Builder.defineMacro("__tune_k6_3__"); 494 } 495 LLVM_FALLTHROUGH; 496 case CK_K6: 497 defineCPUMacros(Builder, "k6"); 498 break; 499 case CK_Athlon: 500 case CK_AthlonXP: 501 defineCPUMacros(Builder, "athlon"); 502 if (SSELevel != NoSSE) { 503 Builder.defineMacro("__athlon_sse__"); 504 Builder.defineMacro("__tune_athlon_sse__"); 505 } 506 break; 507 case CK_K8: 508 case CK_K8SSE3: 509 case CK_x86_64: 510 defineCPUMacros(Builder, "k8"); 511 break; 512 case CK_AMDFAM10: 513 defineCPUMacros(Builder, "amdfam10"); 514 break; 515 case CK_BTVER1: 516 defineCPUMacros(Builder, "btver1"); 517 break; 518 case CK_BTVER2: 519 defineCPUMacros(Builder, "btver2"); 520 break; 521 case CK_BDVER1: 522 defineCPUMacros(Builder, "bdver1"); 523 break; 524 case CK_BDVER2: 525 defineCPUMacros(Builder, "bdver2"); 526 break; 527 case CK_BDVER3: 528 defineCPUMacros(Builder, "bdver3"); 529 break; 530 case CK_BDVER4: 531 defineCPUMacros(Builder, "bdver4"); 532 break; 533 case CK_ZNVER1: 534 defineCPUMacros(Builder, "znver1"); 535 break; 536 case CK_ZNVER2: 537 defineCPUMacros(Builder, "znver2"); 538 break; 539 case CK_Geode: 540 defineCPUMacros(Builder, "geode"); 541 break; 542 } 543 544 // Target properties. 545 Builder.defineMacro("__REGISTER_PREFIX__", ""); 546 547 // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline 548 // functions in glibc header files that use FP Stack inline asm which the 549 // backend can't deal with (PR879). 550 Builder.defineMacro("__NO_MATH_INLINES"); 551 552 if (HasAES) 553 Builder.defineMacro("__AES__"); 554 555 if (HasVAES) 556 Builder.defineMacro("__VAES__"); 557 558 if (HasPCLMUL) 559 Builder.defineMacro("__PCLMUL__"); 560 561 if (HasVPCLMULQDQ) 562 Builder.defineMacro("__VPCLMULQDQ__"); 563 564 if (HasLZCNT) 565 Builder.defineMacro("__LZCNT__"); 566 567 if (HasRDRND) 568 Builder.defineMacro("__RDRND__"); 569 570 if (HasFSGSBASE) 571 Builder.defineMacro("__FSGSBASE__"); 572 573 if (HasBMI) 574 Builder.defineMacro("__BMI__"); 575 576 if (HasBMI2) 577 Builder.defineMacro("__BMI2__"); 578 579 if (HasPOPCNT) 580 Builder.defineMacro("__POPCNT__"); 581 582 if (HasRTM) 583 Builder.defineMacro("__RTM__"); 584 585 if (HasPRFCHW) 586 Builder.defineMacro("__PRFCHW__"); 587 588 if (HasRDSEED) 589 Builder.defineMacro("__RDSEED__"); 590 591 if (HasADX) 592 Builder.defineMacro("__ADX__"); 593 594 if (HasTBM) 595 Builder.defineMacro("__TBM__"); 596 597 if (HasLWP) 598 Builder.defineMacro("__LWP__"); 599 600 if (HasMWAITX) 601 Builder.defineMacro("__MWAITX__"); 602 603 if (HasMOVBE) 604 Builder.defineMacro("__MOVBE__"); 605 606 switch (XOPLevel) { 607 case XOP: 608 Builder.defineMacro("__XOP__"); 609 LLVM_FALLTHROUGH; 610 case FMA4: 611 Builder.defineMacro("__FMA4__"); 612 LLVM_FALLTHROUGH; 613 case SSE4A: 614 Builder.defineMacro("__SSE4A__"); 615 LLVM_FALLTHROUGH; 616 case NoXOP: 617 break; 618 } 619 620 if (HasFMA) 621 Builder.defineMacro("__FMA__"); 622 623 if (HasF16C) 624 Builder.defineMacro("__F16C__"); 625 626 if (HasGFNI) 627 Builder.defineMacro("__GFNI__"); 628 629 if (HasAVX512CD) 630 Builder.defineMacro("__AVX512CD__"); 631 if (HasAVX512VPOPCNTDQ) 632 Builder.defineMacro("__AVX512VPOPCNTDQ__"); 633 if (HasAVX512VNNI) 634 Builder.defineMacro("__AVX512VNNI__"); 635 if (HasAVX512BF16) 636 Builder.defineMacro("__AVX512BF16__"); 637 if (HasAVX512ER) 638 Builder.defineMacro("__AVX512ER__"); 639 if (HasAVX512PF) 640 Builder.defineMacro("__AVX512PF__"); 641 if (HasAVX512DQ) 642 Builder.defineMacro("__AVX512DQ__"); 643 if (HasAVX512BITALG) 644 Builder.defineMacro("__AVX512BITALG__"); 645 if (HasAVX512BW) 646 Builder.defineMacro("__AVX512BW__"); 647 if (HasAVX512VL) 648 Builder.defineMacro("__AVX512VL__"); 649 if (HasAVX512VBMI) 650 Builder.defineMacro("__AVX512VBMI__"); 651 if (HasAVX512VBMI2) 652 Builder.defineMacro("__AVX512VBMI2__"); 653 if (HasAVX512IFMA) 654 Builder.defineMacro("__AVX512IFMA__"); 655 if (HasAVX512VP2INTERSECT) 656 Builder.defineMacro("__AVX512VP2INTERSECT__"); 657 if (HasSHA) 658 Builder.defineMacro("__SHA__"); 659 660 if (HasFXSR) 661 Builder.defineMacro("__FXSR__"); 662 if (HasXSAVE) 663 Builder.defineMacro("__XSAVE__"); 664 if (HasXSAVEOPT) 665 Builder.defineMacro("__XSAVEOPT__"); 666 if (HasXSAVEC) 667 Builder.defineMacro("__XSAVEC__"); 668 if (HasXSAVES) 669 Builder.defineMacro("__XSAVES__"); 670 if (HasPKU) 671 Builder.defineMacro("__PKU__"); 672 if (HasCLFLUSHOPT) 673 Builder.defineMacro("__CLFLUSHOPT__"); 674 if (HasCLWB) 675 Builder.defineMacro("__CLWB__"); 676 if (HasWBNOINVD) 677 Builder.defineMacro("__WBNOINVD__"); 678 if (HasSHSTK) 679 Builder.defineMacro("__SHSTK__"); 680 if (HasSGX) 681 Builder.defineMacro("__SGX__"); 682 if (HasPREFETCHWT1) 683 Builder.defineMacro("__PREFETCHWT1__"); 684 if (HasCLZERO) 685 Builder.defineMacro("__CLZERO__"); 686 if (HasRDPID) 687 Builder.defineMacro("__RDPID__"); 688 if (HasCLDEMOTE) 689 Builder.defineMacro("__CLDEMOTE__"); 690 if (HasWAITPKG) 691 Builder.defineMacro("__WAITPKG__"); 692 if (HasMOVDIRI) 693 Builder.defineMacro("__MOVDIRI__"); 694 if (HasMOVDIR64B) 695 Builder.defineMacro("__MOVDIR64B__"); 696 if (HasPCONFIG) 697 Builder.defineMacro("__PCONFIG__"); 698 if (HasPTWRITE) 699 Builder.defineMacro("__PTWRITE__"); 700 if (HasINVPCID) 701 Builder.defineMacro("__INVPCID__"); 702 if (HasENQCMD) 703 Builder.defineMacro("__ENQCMD__"); 704 if (HasAMXTILE) 705 Builder.defineMacro("__AMXTILE__"); 706 if (HasAMXINT8) 707 Builder.defineMacro("__AMXINT8__"); 708 if (HasAMXBF16) 709 Builder.defineMacro("__AMXBF16__"); 710 if (HasSERIALIZE) 711 Builder.defineMacro("__SERIALIZE__"); 712 if (HasTSXLDTRK) 713 Builder.defineMacro("__TSXLDTRK__"); 714 715 // Each case falls through to the previous one here. 716 switch (SSELevel) { 717 case AVX512F: 718 Builder.defineMacro("__AVX512F__"); 719 LLVM_FALLTHROUGH; 720 case AVX2: 721 Builder.defineMacro("__AVX2__"); 722 LLVM_FALLTHROUGH; 723 case AVX: 724 Builder.defineMacro("__AVX__"); 725 LLVM_FALLTHROUGH; 726 case SSE42: 727 Builder.defineMacro("__SSE4_2__"); 728 LLVM_FALLTHROUGH; 729 case SSE41: 730 Builder.defineMacro("__SSE4_1__"); 731 LLVM_FALLTHROUGH; 732 case SSSE3: 733 Builder.defineMacro("__SSSE3__"); 734 LLVM_FALLTHROUGH; 735 case SSE3: 736 Builder.defineMacro("__SSE3__"); 737 LLVM_FALLTHROUGH; 738 case SSE2: 739 Builder.defineMacro("__SSE2__"); 740 Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied. 741 LLVM_FALLTHROUGH; 742 case SSE1: 743 Builder.defineMacro("__SSE__"); 744 Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied. 745 LLVM_FALLTHROUGH; 746 case NoSSE: 747 break; 748 } 749 750 if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) { 751 switch (SSELevel) { 752 case AVX512F: 753 case AVX2: 754 case AVX: 755 case SSE42: 756 case SSE41: 757 case SSSE3: 758 case SSE3: 759 case SSE2: 760 Builder.defineMacro("_M_IX86_FP", Twine(2)); 761 break; 762 case SSE1: 763 Builder.defineMacro("_M_IX86_FP", Twine(1)); 764 break; 765 default: 766 Builder.defineMacro("_M_IX86_FP", Twine(0)); 767 break; 768 } 769 } 770 771 // Each case falls through to the previous one here. 772 switch (MMX3DNowLevel) { 773 case AMD3DNowAthlon: 774 Builder.defineMacro("__3dNOW_A__"); 775 LLVM_FALLTHROUGH; 776 case AMD3DNow: 777 Builder.defineMacro("__3dNOW__"); 778 LLVM_FALLTHROUGH; 779 case MMX: 780 Builder.defineMacro("__MMX__"); 781 LLVM_FALLTHROUGH; 782 case NoMMX3DNow: 783 break; 784 } 785 786 if (CPU >= CK_i486 || CPU == CK_None) { 787 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 788 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 789 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 790 } 791 if (HasCX8) 792 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 793 if (HasCX16 && getTriple().getArch() == llvm::Triple::x86_64) 794 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16"); 795 796 if (HasFloat128) 797 Builder.defineMacro("__SIZEOF_FLOAT128__", "16"); 798 } 799 800 bool X86TargetInfo::isValidFeatureName(StringRef Name) const { 801 return llvm::StringSwitch<bool>(Name) 802 .Case("3dnow", true) 803 .Case("3dnowa", true) 804 .Case("adx", true) 805 .Case("aes", true) 806 .Case("amx-bf16", true) 807 .Case("amx-int8", true) 808 .Case("amx-tile", true) 809 .Case("avx", true) 810 .Case("avx2", true) 811 .Case("avx512f", true) 812 .Case("avx512cd", true) 813 .Case("avx512vpopcntdq", true) 814 .Case("avx512vnni", true) 815 .Case("avx512bf16", true) 816 .Case("avx512er", true) 817 .Case("avx512pf", true) 818 .Case("avx512dq", true) 819 .Case("avx512bitalg", true) 820 .Case("avx512bw", true) 821 .Case("avx512vl", true) 822 .Case("avx512vbmi", true) 823 .Case("avx512vbmi2", true) 824 .Case("avx512ifma", true) 825 .Case("avx512vp2intersect", true) 826 .Case("bmi", true) 827 .Case("bmi2", true) 828 .Case("cldemote", true) 829 .Case("clflushopt", true) 830 .Case("clwb", true) 831 .Case("clzero", true) 832 .Case("cx16", true) 833 .Case("enqcmd", true) 834 .Case("f16c", true) 835 .Case("fma", true) 836 .Case("fma4", true) 837 .Case("fsgsbase", true) 838 .Case("fxsr", true) 839 .Case("gfni", true) 840 .Case("invpcid", true) 841 .Case("lwp", true) 842 .Case("lzcnt", true) 843 .Case("mmx", true) 844 .Case("movbe", true) 845 .Case("movdiri", true) 846 .Case("movdir64b", true) 847 .Case("mwaitx", true) 848 .Case("pclmul", true) 849 .Case("pconfig", true) 850 .Case("pku", true) 851 .Case("popcnt", true) 852 .Case("prefetchwt1", true) 853 .Case("prfchw", true) 854 .Case("ptwrite", true) 855 .Case("rdpid", true) 856 .Case("rdrnd", true) 857 .Case("rdseed", true) 858 .Case("rtm", true) 859 .Case("sahf", true) 860 .Case("serialize", true) 861 .Case("sgx", true) 862 .Case("sha", true) 863 .Case("shstk", true) 864 .Case("sse", true) 865 .Case("sse2", true) 866 .Case("sse3", true) 867 .Case("ssse3", true) 868 .Case("sse4", true) 869 .Case("sse4.1", true) 870 .Case("sse4.2", true) 871 .Case("sse4a", true) 872 .Case("tbm", true) 873 .Case("tsxldtrk", true) 874 .Case("vaes", true) 875 .Case("vpclmulqdq", true) 876 .Case("wbnoinvd", true) 877 .Case("waitpkg", true) 878 .Case("x87", true) 879 .Case("xop", true) 880 .Case("xsave", true) 881 .Case("xsavec", true) 882 .Case("xsaves", true) 883 .Case("xsaveopt", true) 884 .Default(false); 885 } 886 887 bool X86TargetInfo::hasFeature(StringRef Feature) const { 888 return llvm::StringSwitch<bool>(Feature) 889 .Case("adx", HasADX) 890 .Case("aes", HasAES) 891 .Case("amx-bf16", HasAMXBF16) 892 .Case("amx-int8", HasAMXINT8) 893 .Case("amx-tile", HasAMXTILE) 894 .Case("avx", SSELevel >= AVX) 895 .Case("avx2", SSELevel >= AVX2) 896 .Case("avx512f", SSELevel >= AVX512F) 897 .Case("avx512cd", HasAVX512CD) 898 .Case("avx512vpopcntdq", HasAVX512VPOPCNTDQ) 899 .Case("avx512vnni", HasAVX512VNNI) 900 .Case("avx512bf16", HasAVX512BF16) 901 .Case("avx512er", HasAVX512ER) 902 .Case("avx512pf", HasAVX512PF) 903 .Case("avx512dq", HasAVX512DQ) 904 .Case("avx512bitalg", HasAVX512BITALG) 905 .Case("avx512bw", HasAVX512BW) 906 .Case("avx512vl", HasAVX512VL) 907 .Case("avx512vbmi", HasAVX512VBMI) 908 .Case("avx512vbmi2", HasAVX512VBMI2) 909 .Case("avx512ifma", HasAVX512IFMA) 910 .Case("avx512vp2intersect", HasAVX512VP2INTERSECT) 911 .Case("bmi", HasBMI) 912 .Case("bmi2", HasBMI2) 913 .Case("cldemote", HasCLDEMOTE) 914 .Case("clflushopt", HasCLFLUSHOPT) 915 .Case("clwb", HasCLWB) 916 .Case("clzero", HasCLZERO) 917 .Case("cx8", HasCX8) 918 .Case("cx16", HasCX16) 919 .Case("enqcmd", HasENQCMD) 920 .Case("f16c", HasF16C) 921 .Case("fma", HasFMA) 922 .Case("fma4", XOPLevel >= FMA4) 923 .Case("fsgsbase", HasFSGSBASE) 924 .Case("fxsr", HasFXSR) 925 .Case("gfni", HasGFNI) 926 .Case("invpcid", HasINVPCID) 927 .Case("lwp", HasLWP) 928 .Case("lzcnt", HasLZCNT) 929 .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow) 930 .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon) 931 .Case("mmx", MMX3DNowLevel >= MMX) 932 .Case("movbe", HasMOVBE) 933 .Case("movdiri", HasMOVDIRI) 934 .Case("movdir64b", HasMOVDIR64B) 935 .Case("save-args", HasSaveArgs) 936 .Case("mwaitx", HasMWAITX) 937 .Case("pclmul", HasPCLMUL) 938 .Case("pconfig", HasPCONFIG) 939 .Case("pku", HasPKU) 940 .Case("popcnt", HasPOPCNT) 941 .Case("prefetchwt1", HasPREFETCHWT1) 942 .Case("prfchw", HasPRFCHW) 943 .Case("ptwrite", HasPTWRITE) 944 .Case("rdpid", HasRDPID) 945 .Case("rdrnd", HasRDRND) 946 .Case("rdseed", HasRDSEED) 947 .Case("retpoline-external-thunk", HasRetpolineExternalThunk) 948 .Case("rtm", HasRTM) 949 .Case("sahf", HasLAHFSAHF) 950 .Case("serialize", HasSERIALIZE) 951 .Case("sgx", HasSGX) 952 .Case("sha", HasSHA) 953 .Case("shstk", HasSHSTK) 954 .Case("sse", SSELevel >= SSE1) 955 .Case("sse2", SSELevel >= SSE2) 956 .Case("sse3", SSELevel >= SSE3) 957 .Case("ssse3", SSELevel >= SSSE3) 958 .Case("sse4.1", SSELevel >= SSE41) 959 .Case("sse4.2", SSELevel >= SSE42) 960 .Case("sse4a", XOPLevel >= SSE4A) 961 .Case("tbm", HasTBM) 962 .Case("tsxldtrk", HasTSXLDTRK) 963 .Case("vaes", HasVAES) 964 .Case("vpclmulqdq", HasVPCLMULQDQ) 965 .Case("wbnoinvd", HasWBNOINVD) 966 .Case("waitpkg", HasWAITPKG) 967 .Case("x86", true) 968 .Case("x86_32", getTriple().getArch() == llvm::Triple::x86) 969 .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64) 970 .Case("xop", XOPLevel >= XOP) 971 .Case("xsave", HasXSAVE) 972 .Case("xsavec", HasXSAVEC) 973 .Case("xsaves", HasXSAVES) 974 .Case("xsaveopt", HasXSAVEOPT) 975 .Default(false); 976 } 977 978 // We can't use a generic validation scheme for the features accepted here 979 // versus subtarget features accepted in the target attribute because the 980 // bitfield structure that's initialized in the runtime only supports the 981 // below currently rather than the full range of subtarget features. (See 982 // X86TargetInfo::hasFeature for a somewhat comprehensive list). 983 bool X86TargetInfo::validateCpuSupports(StringRef FeatureStr) const { 984 return llvm::StringSwitch<bool>(FeatureStr) 985 #define X86_FEATURE_COMPAT(ENUM, STR) .Case(STR, true) 986 #include "llvm/Support/X86TargetParser.def" 987 .Default(false); 988 } 989 990 static llvm::X86::ProcessorFeatures getFeature(StringRef Name) { 991 return llvm::StringSwitch<llvm::X86::ProcessorFeatures>(Name) 992 #define X86_FEATURE_COMPAT(ENUM, STR) .Case(STR, llvm::X86::FEATURE_##ENUM) 993 #include "llvm/Support/X86TargetParser.def" 994 ; 995 // Note, this function should only be used after ensuring the value is 996 // correct, so it asserts if the value is out of range. 997 } 998 999 static unsigned getFeaturePriority(llvm::X86::ProcessorFeatures Feat) { 1000 enum class FeatPriority { 1001 #define FEATURE(FEAT) FEAT, 1002 #include "clang/Basic/X86Target.def" 1003 }; 1004 switch (Feat) { 1005 #define FEATURE(FEAT) \ 1006 case llvm::X86::FEAT: \ 1007 return static_cast<unsigned>(FeatPriority::FEAT); 1008 #include "clang/Basic/X86Target.def" 1009 default: 1010 llvm_unreachable("No Feature Priority for non-CPUSupports Features"); 1011 } 1012 } 1013 1014 unsigned X86TargetInfo::multiVersionSortPriority(StringRef Name) const { 1015 // Valid CPUs have a 'key feature' that compares just better than its key 1016 // feature. 1017 using namespace llvm::X86; 1018 CPUKind Kind = parseArchX86(Name); 1019 if (Kind != CK_None) { 1020 ProcessorFeatures KeyFeature = getKeyFeature(Kind); 1021 return (getFeaturePriority(KeyFeature) << 1) + 1; 1022 } 1023 1024 // Now we know we have a feature, so get its priority and shift it a few so 1025 // that we have sufficient room for the CPUs (above). 1026 return getFeaturePriority(getFeature(Name)) << 1; 1027 } 1028 1029 bool X86TargetInfo::validateCPUSpecificCPUDispatch(StringRef Name) const { 1030 return llvm::StringSwitch<bool>(Name) 1031 #define CPU_SPECIFIC(NAME, MANGLING, FEATURES) .Case(NAME, true) 1032 #define CPU_SPECIFIC_ALIAS(NEW_NAME, NAME) .Case(NEW_NAME, true) 1033 #include "clang/Basic/X86Target.def" 1034 .Default(false); 1035 } 1036 1037 static StringRef CPUSpecificCPUDispatchNameDealias(StringRef Name) { 1038 return llvm::StringSwitch<StringRef>(Name) 1039 #define CPU_SPECIFIC_ALIAS(NEW_NAME, NAME) .Case(NEW_NAME, NAME) 1040 #include "clang/Basic/X86Target.def" 1041 .Default(Name); 1042 } 1043 1044 char X86TargetInfo::CPUSpecificManglingCharacter(StringRef Name) const { 1045 return llvm::StringSwitch<char>(CPUSpecificCPUDispatchNameDealias(Name)) 1046 #define CPU_SPECIFIC(NAME, MANGLING, FEATURES) .Case(NAME, MANGLING) 1047 #include "clang/Basic/X86Target.def" 1048 .Default(0); 1049 } 1050 1051 void X86TargetInfo::getCPUSpecificCPUDispatchFeatures( 1052 StringRef Name, llvm::SmallVectorImpl<StringRef> &Features) const { 1053 StringRef WholeList = 1054 llvm::StringSwitch<StringRef>(CPUSpecificCPUDispatchNameDealias(Name)) 1055 #define CPU_SPECIFIC(NAME, MANGLING, FEATURES) .Case(NAME, FEATURES) 1056 #include "clang/Basic/X86Target.def" 1057 .Default(""); 1058 WholeList.split(Features, ',', /*MaxSplit=*/-1, /*KeepEmpty=*/false); 1059 } 1060 1061 // We can't use a generic validation scheme for the cpus accepted here 1062 // versus subtarget cpus accepted in the target attribute because the 1063 // variables intitialized by the runtime only support the below currently 1064 // rather than the full range of cpus. 1065 bool X86TargetInfo::validateCpuIs(StringRef FeatureStr) const { 1066 return llvm::StringSwitch<bool>(FeatureStr) 1067 #define X86_VENDOR(ENUM, STRING) .Case(STRING, true) 1068 #define X86_CPU_TYPE_ALIAS(ENUM, ALIAS) .Case(ALIAS, true) 1069 #define X86_CPU_TYPE(ENUM, STR) .Case(STR, true) 1070 #define X86_CPU_SUBTYPE(ENUM, STR) .Case(STR, true) 1071 #include "llvm/Support/X86TargetParser.def" 1072 .Default(false); 1073 } 1074 1075 static unsigned matchAsmCCConstraint(const char *&Name) { 1076 auto RV = llvm::StringSwitch<unsigned>(Name) 1077 .Case("@cca", 4) 1078 .Case("@ccae", 5) 1079 .Case("@ccb", 4) 1080 .Case("@ccbe", 5) 1081 .Case("@ccc", 4) 1082 .Case("@cce", 4) 1083 .Case("@ccz", 4) 1084 .Case("@ccg", 4) 1085 .Case("@ccge", 5) 1086 .Case("@ccl", 4) 1087 .Case("@ccle", 5) 1088 .Case("@ccna", 5) 1089 .Case("@ccnae", 6) 1090 .Case("@ccnb", 5) 1091 .Case("@ccnbe", 6) 1092 .Case("@ccnc", 5) 1093 .Case("@ccne", 5) 1094 .Case("@ccnz", 5) 1095 .Case("@ccng", 5) 1096 .Case("@ccnge", 6) 1097 .Case("@ccnl", 5) 1098 .Case("@ccnle", 6) 1099 .Case("@ccno", 5) 1100 .Case("@ccnp", 5) 1101 .Case("@ccns", 5) 1102 .Case("@cco", 4) 1103 .Case("@ccp", 4) 1104 .Case("@ccs", 4) 1105 .Default(0); 1106 return RV; 1107 } 1108 1109 bool X86TargetInfo::validateAsmConstraint( 1110 const char *&Name, TargetInfo::ConstraintInfo &Info) const { 1111 switch (*Name) { 1112 default: 1113 return false; 1114 // Constant constraints. 1115 case 'e': // 32-bit signed integer constant for use with sign-extending x86_64 1116 // instructions. 1117 case 'Z': // 32-bit unsigned integer constant for use with zero-extending 1118 // x86_64 instructions. 1119 case 's': 1120 Info.setRequiresImmediate(); 1121 return true; 1122 case 'I': 1123 Info.setRequiresImmediate(0, 31); 1124 return true; 1125 case 'J': 1126 Info.setRequiresImmediate(0, 63); 1127 return true; 1128 case 'K': 1129 Info.setRequiresImmediate(-128, 127); 1130 return true; 1131 case 'L': 1132 Info.setRequiresImmediate({int(0xff), int(0xffff), int(0xffffffff)}); 1133 return true; 1134 case 'M': 1135 Info.setRequiresImmediate(0, 3); 1136 return true; 1137 case 'N': 1138 Info.setRequiresImmediate(0, 255); 1139 return true; 1140 case 'O': 1141 Info.setRequiresImmediate(0, 127); 1142 return true; 1143 // Register constraints. 1144 case 'Y': // 'Y' is the first character for several 2-character constraints. 1145 // Shift the pointer to the second character of the constraint. 1146 Name++; 1147 switch (*Name) { 1148 default: 1149 return false; 1150 case 'z': // First SSE register. 1151 case '2': 1152 case 't': // Any SSE register, when SSE2 is enabled. 1153 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled. 1154 case 'm': // Any MMX register, when inter-unit moves enabled. 1155 case 'k': // AVX512 arch mask registers: k1-k7. 1156 Info.setAllowsRegister(); 1157 return true; 1158 } 1159 case 'f': // Any x87 floating point stack register. 1160 // Constraint 'f' cannot be used for output operands. 1161 if (Info.ConstraintStr[0] == '=') 1162 return false; 1163 Info.setAllowsRegister(); 1164 return true; 1165 case 'a': // eax. 1166 case 'b': // ebx. 1167 case 'c': // ecx. 1168 case 'd': // edx. 1169 case 'S': // esi. 1170 case 'D': // edi. 1171 case 'A': // edx:eax. 1172 case 't': // Top of floating point stack. 1173 case 'u': // Second from top of floating point stack. 1174 case 'q': // Any register accessible as [r]l: a, b, c, and d. 1175 case 'y': // Any MMX register. 1176 case 'v': // Any {X,Y,Z}MM register (Arch & context dependent) 1177 case 'x': // Any SSE register. 1178 case 'k': // Any AVX512 mask register (same as Yk, additionally allows k0 1179 // for intermideate k reg operations). 1180 case 'Q': // Any register accessible as [r]h: a, b, c, and d. 1181 case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp. 1182 case 'l': // "Index" registers: any general register that can be used as an 1183 // index in a base+index memory access. 1184 Info.setAllowsRegister(); 1185 return true; 1186 // Floating point constant constraints. 1187 case 'C': // SSE floating point constant. 1188 case 'G': // x87 floating point constant. 1189 return true; 1190 case '@': 1191 // CC condition changes. 1192 if (auto Len = matchAsmCCConstraint(Name)) { 1193 Name += Len - 1; 1194 Info.setAllowsRegister(); 1195 return true; 1196 } 1197 return false; 1198 } 1199 } 1200 1201 // Below is based on the following information: 1202 // +------------------------------------+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ 1203 // | Processor Name | Cache Line Size (Bytes) | Source | 1204 // +------------------------------------+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ 1205 // | i386 | 64 | https://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-optimization-manual.pdf | 1206 // | i486 | 16 | "four doublewords" (doubleword = 32 bits, 4 bits * 32 bits = 16 bytes) https://en.wikichip.org/w/images/d/d3/i486_MICROPROCESSOR_HARDWARE_REFERENCE_MANUAL_%281990%29.pdf and http://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.126.4216&rep=rep1&type=pdf (page 29) | 1207 // | i586/Pentium MMX | 32 | https://www.7-cpu.com/cpu/P-MMX.html | 1208 // | i686/Pentium | 32 | https://www.7-cpu.com/cpu/P6.html | 1209 // | Netburst/Pentium4 | 64 | https://www.7-cpu.com/cpu/P4-180.html | 1210 // | Atom | 64 | https://www.7-cpu.com/cpu/Atom.html | 1211 // | Westmere | 64 | https://en.wikichip.org/wiki/intel/microarchitectures/sandy_bridge_(client) "Cache Architecture" | 1212 // | Sandy Bridge | 64 | https://en.wikipedia.org/wiki/Sandy_Bridge and https://www.7-cpu.com/cpu/SandyBridge.html | 1213 // | Ivy Bridge | 64 | https://blog.stuffedcow.net/2013/01/ivb-cache-replacement/ and https://www.7-cpu.com/cpu/IvyBridge.html | 1214 // | Haswell | 64 | https://www.7-cpu.com/cpu/Haswell.html | 1215 // | Boadwell | 64 | https://www.7-cpu.com/cpu/Broadwell.html | 1216 // | Skylake (including skylake-avx512) | 64 | https://www.nas.nasa.gov/hecc/support/kb/skylake-processors_550.html "Cache Hierarchy" | 1217 // | Cascade Lake | 64 | https://www.nas.nasa.gov/hecc/support/kb/cascade-lake-processors_579.html "Cache Hierarchy" | 1218 // | Skylake | 64 | https://en.wikichip.org/wiki/intel/microarchitectures/kaby_lake "Memory Hierarchy" | 1219 // | Ice Lake | 64 | https://www.7-cpu.com/cpu/Ice_Lake.html | 1220 // | Knights Landing | 64 | https://software.intel.com/en-us/articles/intel-xeon-phi-processor-7200-family-memory-management-optimizations "The Intel® Xeon Phi™ Processor Architecture" | 1221 // | Knights Mill | 64 | https://software.intel.com/sites/default/files/managed/9e/bc/64-ia-32-architectures-optimization-manual.pdf?countrylabel=Colombia "2.5.5.2 L1 DCache " | 1222 // +------------------------------------+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ 1223 Optional<unsigned> X86TargetInfo::getCPUCacheLineSize() const { 1224 using namespace llvm::X86; 1225 switch (CPU) { 1226 // i386 1227 case CK_i386: 1228 // i486 1229 case CK_i486: 1230 case CK_WinChipC6: 1231 case CK_WinChip2: 1232 case CK_C3: 1233 // Lakemont 1234 case CK_Lakemont: 1235 return 16; 1236 1237 // i586 1238 case CK_i586: 1239 case CK_Pentium: 1240 case CK_PentiumMMX: 1241 // i686 1242 case CK_PentiumPro: 1243 case CK_i686: 1244 case CK_Pentium2: 1245 case CK_Pentium3: 1246 case CK_PentiumM: 1247 case CK_C3_2: 1248 // K6 1249 case CK_K6: 1250 case CK_K6_2: 1251 case CK_K6_3: 1252 // Geode 1253 case CK_Geode: 1254 return 32; 1255 1256 // Netburst 1257 case CK_Pentium4: 1258 case CK_Prescott: 1259 case CK_Nocona: 1260 // Atom 1261 case CK_Bonnell: 1262 case CK_Silvermont: 1263 case CK_Goldmont: 1264 case CK_GoldmontPlus: 1265 case CK_Tremont: 1266 1267 case CK_Westmere: 1268 case CK_SandyBridge: 1269 case CK_IvyBridge: 1270 case CK_Haswell: 1271 case CK_Broadwell: 1272 case CK_SkylakeClient: 1273 case CK_SkylakeServer: 1274 case CK_Cascadelake: 1275 case CK_Nehalem: 1276 case CK_Cooperlake: 1277 case CK_Cannonlake: 1278 case CK_Tigerlake: 1279 case CK_IcelakeClient: 1280 case CK_IcelakeServer: 1281 case CK_KNL: 1282 case CK_KNM: 1283 // K7 1284 case CK_Athlon: 1285 case CK_AthlonXP: 1286 // K8 1287 case CK_K8: 1288 case CK_K8SSE3: 1289 case CK_AMDFAM10: 1290 // Bobcat 1291 case CK_BTVER1: 1292 case CK_BTVER2: 1293 // Bulldozer 1294 case CK_BDVER1: 1295 case CK_BDVER2: 1296 case CK_BDVER3: 1297 case CK_BDVER4: 1298 // Zen 1299 case CK_ZNVER1: 1300 case CK_ZNVER2: 1301 // Deprecated 1302 case CK_x86_64: 1303 case CK_Yonah: 1304 case CK_Penryn: 1305 case CK_Core2: 1306 return 64; 1307 1308 // The following currently have unknown cache line sizes (but they are probably all 64): 1309 // Core 1310 case CK_None: 1311 return None; 1312 } 1313 llvm_unreachable("Unknown CPU kind"); 1314 } 1315 1316 bool X86TargetInfo::validateOutputSize(const llvm::StringMap<bool> &FeatureMap, 1317 StringRef Constraint, 1318 unsigned Size) const { 1319 // Strip off constraint modifiers. 1320 while (Constraint[0] == '=' || Constraint[0] == '+' || Constraint[0] == '&') 1321 Constraint = Constraint.substr(1); 1322 1323 return validateOperandSize(FeatureMap, Constraint, Size); 1324 } 1325 1326 bool X86TargetInfo::validateInputSize(const llvm::StringMap<bool> &FeatureMap, 1327 StringRef Constraint, 1328 unsigned Size) const { 1329 return validateOperandSize(FeatureMap, Constraint, Size); 1330 } 1331 1332 bool X86TargetInfo::validateOperandSize(const llvm::StringMap<bool> &FeatureMap, 1333 StringRef Constraint, 1334 unsigned Size) const { 1335 switch (Constraint[0]) { 1336 default: 1337 break; 1338 case 'k': 1339 // Registers k0-k7 (AVX512) size limit is 64 bit. 1340 case 'y': 1341 return Size <= 64; 1342 case 'f': 1343 case 't': 1344 case 'u': 1345 return Size <= 128; 1346 case 'Y': 1347 // 'Y' is the first character for several 2-character constraints. 1348 switch (Constraint[1]) { 1349 default: 1350 return false; 1351 case 'm': 1352 // 'Ym' is synonymous with 'y'. 1353 case 'k': 1354 return Size <= 64; 1355 case 'z': 1356 // XMM0/YMM/ZMM0 1357 if (FeatureMap.lookup("avx512f")) 1358 // ZMM0 can be used if target supports AVX512F. 1359 return Size <= 512U; 1360 else if (FeatureMap.lookup("avx")) 1361 // YMM0 can be used if target supports AVX. 1362 return Size <= 256U; 1363 else if (FeatureMap.lookup("sse")) 1364 return Size <= 128U; 1365 return false; 1366 case 'i': 1367 case 't': 1368 case '2': 1369 // 'Yi','Yt','Y2' are synonymous with 'x' when SSE2 is enabled. 1370 if (SSELevel < SSE2) 1371 return false; 1372 break; 1373 } 1374 break; 1375 case 'v': 1376 case 'x': 1377 if (FeatureMap.lookup("avx512f")) 1378 // 512-bit zmm registers can be used if target supports AVX512F. 1379 return Size <= 512U; 1380 else if (FeatureMap.lookup("avx")) 1381 // 256-bit ymm registers can be used if target supports AVX. 1382 return Size <= 256U; 1383 return Size <= 128U; 1384 1385 } 1386 1387 return true; 1388 } 1389 1390 std::string X86TargetInfo::convertConstraint(const char *&Constraint) const { 1391 switch (*Constraint) { 1392 case '@': 1393 if (auto Len = matchAsmCCConstraint(Constraint)) { 1394 std::string Converted = "{" + std::string(Constraint, Len) + "}"; 1395 Constraint += Len - 1; 1396 return Converted; 1397 } 1398 return std::string(1, *Constraint); 1399 case 'a': 1400 return std::string("{ax}"); 1401 case 'b': 1402 return std::string("{bx}"); 1403 case 'c': 1404 return std::string("{cx}"); 1405 case 'd': 1406 return std::string("{dx}"); 1407 case 'S': 1408 return std::string("{si}"); 1409 case 'D': 1410 return std::string("{di}"); 1411 case 'p': // address 1412 return std::string("im"); 1413 case 't': // top of floating point stack. 1414 return std::string("{st}"); 1415 case 'u': // second from top of floating point stack. 1416 return std::string("{st(1)}"); // second from top of floating point stack. 1417 case 'Y': 1418 switch (Constraint[1]) { 1419 default: 1420 // Break from inner switch and fall through (copy single char), 1421 // continue parsing after copying the current constraint into 1422 // the return string. 1423 break; 1424 case 'k': 1425 case 'm': 1426 case 'i': 1427 case 't': 1428 case 'z': 1429 case '2': 1430 // "^" hints llvm that this is a 2 letter constraint. 1431 // "Constraint++" is used to promote the string iterator 1432 // to the next constraint. 1433 return std::string("^") + std::string(Constraint++, 2); 1434 } 1435 LLVM_FALLTHROUGH; 1436 default: 1437 return std::string(1, *Constraint); 1438 } 1439 } 1440 1441 void X86TargetInfo::fillValidCPUList(SmallVectorImpl<StringRef> &Values) const { 1442 bool Only64Bit = getTriple().getArch() != llvm::Triple::x86; 1443 llvm::X86::fillValidCPUArchList(Values, Only64Bit); 1444 } 1445 1446 ArrayRef<const char *> X86TargetInfo::getGCCRegNames() const { 1447 return llvm::makeArrayRef(GCCRegNames); 1448 } 1449 1450 ArrayRef<TargetInfo::AddlRegName> X86TargetInfo::getGCCAddlRegNames() const { 1451 return llvm::makeArrayRef(AddlRegNames); 1452 } 1453 1454 ArrayRef<Builtin::Info> X86_32TargetInfo::getTargetBuiltins() const { 1455 return llvm::makeArrayRef(BuiltinInfoX86, clang::X86::LastX86CommonBuiltin - 1456 Builtin::FirstTSBuiltin + 1); 1457 } 1458 1459 ArrayRef<Builtin::Info> X86_64TargetInfo::getTargetBuiltins() const { 1460 return llvm::makeArrayRef(BuiltinInfoX86, 1461 X86::LastTSBuiltin - Builtin::FirstTSBuiltin); 1462 } 1463