xref: /onnv-gate/usr/src/uts/sun4v/vm/mach_vm_dep.c (revision 5631:86330280b9fd)
10Sstevel@tonic-gate /*
20Sstevel@tonic-gate  * CDDL HEADER START
30Sstevel@tonic-gate  *
40Sstevel@tonic-gate  * The contents of this file are subject to the terms of the
51859Sha137994  * Common Development and Distribution License (the "License").
61859Sha137994  * You may not use this file except in compliance with the License.
70Sstevel@tonic-gate  *
80Sstevel@tonic-gate  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
90Sstevel@tonic-gate  * or http://www.opensolaris.org/os/licensing.
100Sstevel@tonic-gate  * See the License for the specific language governing permissions
110Sstevel@tonic-gate  * and limitations under the License.
120Sstevel@tonic-gate  *
130Sstevel@tonic-gate  * When distributing Covered Code, include this CDDL HEADER in each
140Sstevel@tonic-gate  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
150Sstevel@tonic-gate  * If applicable, add the following below this CDDL HEADER, with the
160Sstevel@tonic-gate  * fields enclosed by brackets "[]" replaced with your own identifying
170Sstevel@tonic-gate  * information: Portions Copyright [yyyy] [name of copyright owner]
180Sstevel@tonic-gate  *
190Sstevel@tonic-gate  * CDDL HEADER END
200Sstevel@tonic-gate  */
210Sstevel@tonic-gate /*
223764Sdp78419  * Copyright 2007 Sun Microsystems, Inc.  All rights reserved.
230Sstevel@tonic-gate  * Use is subject to license terms.
240Sstevel@tonic-gate  */
250Sstevel@tonic-gate 
260Sstevel@tonic-gate /* Copyright (c) 1984, 1986, 1987, 1988, 1989 AT&T */
270Sstevel@tonic-gate /*	All Rights Reserved   */
280Sstevel@tonic-gate 
290Sstevel@tonic-gate /*
300Sstevel@tonic-gate  * Portions of this source code were derived from Berkeley 4.3 BSD
310Sstevel@tonic-gate  * under license from the Regents of the University of California.
320Sstevel@tonic-gate  */
330Sstevel@tonic-gate 
340Sstevel@tonic-gate #pragma ident	"%Z%%M%	%I%	%E% SMI"
350Sstevel@tonic-gate 
360Sstevel@tonic-gate /*
370Sstevel@tonic-gate  * UNIX machine dependent virtual memory support.
380Sstevel@tonic-gate  */
390Sstevel@tonic-gate 
400Sstevel@tonic-gate #include <sys/vm.h>
410Sstevel@tonic-gate #include <sys/exec.h>
420Sstevel@tonic-gate #include <sys/cmn_err.h>
430Sstevel@tonic-gate #include <sys/cpu_module.h>
440Sstevel@tonic-gate #include <sys/cpu.h>
450Sstevel@tonic-gate #include <sys/elf_SPARC.h>
460Sstevel@tonic-gate #include <sys/archsystm.h>
470Sstevel@tonic-gate #include <vm/hat_sfmmu.h>
480Sstevel@tonic-gate #include <sys/memnode.h>
490Sstevel@tonic-gate #include <sys/mem_cage.h>
500Sstevel@tonic-gate #include <vm/vm_dep.h>
510Sstevel@tonic-gate #include <sys/error.h>
520Sstevel@tonic-gate #include <sys/machsystm.h>
530Sstevel@tonic-gate #include <vm/seg_kmem.h>
543177Sdp78419 #include <sys/stack.h>
553177Sdp78419 #include <sys/atomic.h>
560Sstevel@tonic-gate 
570Sstevel@tonic-gate uint_t page_colors = 0;
580Sstevel@tonic-gate uint_t page_colors_mask = 0;
590Sstevel@tonic-gate uint_t page_coloring_shift = 0;
600Sstevel@tonic-gate int consistent_coloring;
614266Sdp78419 int update_proc_pgcolorbase_after_fork = 1;
620Sstevel@tonic-gate 
630Sstevel@tonic-gate uint_t mmu_page_sizes = MMU_PAGE_SIZES;
640Sstevel@tonic-gate uint_t max_mmu_page_sizes = MMU_PAGE_SIZES;
650Sstevel@tonic-gate uint_t mmu_hashcnt = MAX_HASHCNT;
660Sstevel@tonic-gate uint_t max_mmu_hashcnt = MAX_HASHCNT;
670Sstevel@tonic-gate size_t mmu_ism_pagesize = DEFAULT_ISM_PAGESIZE;
680Sstevel@tonic-gate 
690Sstevel@tonic-gate /*
700Sstevel@tonic-gate  * A bitmask of the page sizes supported by hardware based upon szc.
710Sstevel@tonic-gate  * The base pagesize (p_szc == 0) must always be supported by the hardware.
720Sstevel@tonic-gate  */
730Sstevel@tonic-gate int mmu_exported_pagesize_mask;
740Sstevel@tonic-gate uint_t mmu_exported_page_sizes;
750Sstevel@tonic-gate 
760Sstevel@tonic-gate uint_t szc_2_userszc[MMU_PAGE_SIZES];
770Sstevel@tonic-gate uint_t userszc_2_szc[MMU_PAGE_SIZES];
780Sstevel@tonic-gate 
790Sstevel@tonic-gate extern uint_t vac_colors_mask;
800Sstevel@tonic-gate extern int vac_shift;
810Sstevel@tonic-gate 
820Sstevel@tonic-gate hw_pagesize_t hw_page_array[] = {
832961Sdp78419 	{MMU_PAGESIZE, MMU_PAGESHIFT, 0, MMU_PAGESIZE >> MMU_PAGESHIFT},
842961Sdp78419 	{MMU_PAGESIZE64K, MMU_PAGESHIFT64K, 0,
852961Sdp78419 	    MMU_PAGESIZE64K >> MMU_PAGESHIFT},
862961Sdp78419 	{MMU_PAGESIZE512K, MMU_PAGESHIFT512K, 0,
870Sstevel@tonic-gate 	    MMU_PAGESIZE512K >> MMU_PAGESHIFT},
882961Sdp78419 	{MMU_PAGESIZE4M, MMU_PAGESHIFT4M, 0, MMU_PAGESIZE4M >> MMU_PAGESHIFT},
892961Sdp78419 	{MMU_PAGESIZE32M, MMU_PAGESHIFT32M, 0,
902961Sdp78419 	    MMU_PAGESIZE32M >> MMU_PAGESHIFT},
912961Sdp78419 	{MMU_PAGESIZE256M, MMU_PAGESHIFT256M, 0,
920Sstevel@tonic-gate 	    MMU_PAGESIZE256M >> MMU_PAGESHIFT},
932961Sdp78419 	{0, 0, 0, 0}
940Sstevel@tonic-gate };
950Sstevel@tonic-gate 
960Sstevel@tonic-gate /*
973764Sdp78419  * Maximum page size used to map 64-bit memory segment kmem64_base..kmem64_end
983764Sdp78419  */
993764Sdp78419 int	max_bootlp_tteszc = TTE256M;
1003764Sdp78419 
1013764Sdp78419 /*
1022991Ssusans  * Maximum and default segment size tunables for user heap, stack, private
1032991Ssusans  * and shared anonymous memory, and user text and initialized data.
1040Sstevel@tonic-gate  */
1052991Ssusans size_t max_uheap_lpsize = MMU_PAGESIZE64K;
1062991Ssusans size_t default_uheap_lpsize = MMU_PAGESIZE64K;
1072991Ssusans size_t max_ustack_lpsize = MMU_PAGESIZE64K;
1082991Ssusans size_t default_ustack_lpsize = MMU_PAGESIZE64K;
1092991Ssusans size_t max_privmap_lpsize = MMU_PAGESIZE64K;
1102991Ssusans size_t max_uidata_lpsize = MMU_PAGESIZE64K;
1112991Ssusans size_t max_utext_lpsize = MMU_PAGESIZE4M;
1122414Saguzovsk size_t max_shm_lpsize = MMU_PAGESIZE4M;
1132414Saguzovsk 
1140Sstevel@tonic-gate /*
1154204Sha137994  * Contiguous memory allocator data structures and variables.
1164204Sha137994  *
1174204Sha137994  * The sun4v kernel must provide a means to allocate physically
1184204Sha137994  * contiguous, non-relocatable memory. The contig_mem_arena
1194204Sha137994  * and contig_mem_slab_arena exist for this purpose. Allocations
1204204Sha137994  * that require physically contiguous non-relocatable memory should
1214204Sha137994  * be made using contig_mem_alloc() or contig_mem_alloc_align()
1224204Sha137994  * which return memory from contig_mem_arena or contig_mem_reloc_arena.
1234204Sha137994  * These arenas import memory from the contig_mem_slab_arena one
1244204Sha137994  * contiguous chunk at a time.
1254204Sha137994  *
1264204Sha137994  * When importing slabs, an attempt is made to allocate a large page
1274204Sha137994  * to use as backing. As a result of the non-relocatable requirement,
1284204Sha137994  * slabs are allocated from the kernel cage freelists. If the cage does
1294204Sha137994  * not contain any free contiguous chunks large enough to satisfy the
1304204Sha137994  * slab allocation, the slab size will be downsized and the operation
1314204Sha137994  * retried. Large slab sizes are tried first to minimize cage
1324204Sha137994  * fragmentation. If the slab allocation is unsuccessful still, the slab
1334204Sha137994  * is allocated from outside the kernel cage. This is undesirable because,
1344204Sha137994  * until slabs are freed, it results in non-relocatable chunks scattered
1354204Sha137994  * throughout physical memory.
1364204Sha137994  *
1374204Sha137994  * Allocations from the contig_mem_arena are backed by slabs from the
1384204Sha137994  * cage. Allocations from the contig_mem_reloc_arena are backed by
1394204Sha137994  * slabs allocated outside the cage. Slabs are left share locked while
1404204Sha137994  * in use to prevent non-cage slabs from being relocated.
1414204Sha137994  *
1424204Sha137994  * Since there is no guarantee that large pages will be available in
1434204Sha137994  * the kernel cage, contiguous memory is reserved and added to the
1444204Sha137994  * contig_mem_arena at boot time, making it available for later
1454204Sha137994  * contiguous memory allocations. This reserve will be used to satisfy
1464204Sha137994  * contig_mem allocations first and it is only when the reserve is
1474204Sha137994  * completely allocated that new slabs will need to be imported.
1484204Sha137994  */
1494204Sha137994 static	vmem_t		*contig_mem_slab_arena;
1504204Sha137994 static	vmem_t		*contig_mem_arena;
1514204Sha137994 static	vmem_t		*contig_mem_reloc_arena;
1524204Sha137994 static	kmutex_t	contig_mem_lock;
1534204Sha137994 #define	CONTIG_MEM_ARENA_QUANTUM	64
1544204Sha137994 #define	CONTIG_MEM_SLAB_ARENA_QUANTUM	MMU_PAGESIZE64K
1554204Sha137994 
1564204Sha137994 /* contig_mem_arena import slab sizes, in decreasing size order */
1574204Sha137994 static size_t contig_mem_import_sizes[] = {
1584204Sha137994 	MMU_PAGESIZE4M,
1594204Sha137994 	MMU_PAGESIZE512K,
1604204Sha137994 	MMU_PAGESIZE64K
1614204Sha137994 };
1624204Sha137994 #define	NUM_IMPORT_SIZES	\
1634204Sha137994 	(sizeof (contig_mem_import_sizes) / sizeof (size_t))
1644204Sha137994 static size_t contig_mem_import_size_max	= MMU_PAGESIZE4M;
1654204Sha137994 size_t contig_mem_slab_size			= MMU_PAGESIZE4M;
1664204Sha137994 
1674204Sha137994 /* Boot-time allocated buffer to pre-populate the contig_mem_arena */
168*5631Swh94709 static size_t contig_mem_prealloc_size;
169*5631Swh94709 static void *contig_mem_prealloc_buf;
1704204Sha137994 
1714204Sha137994 /*
1720Sstevel@tonic-gate  * map_addr_proc() is the routine called when the system is to
1730Sstevel@tonic-gate  * choose an address for the user.  We will pick an address
1740Sstevel@tonic-gate  * range which is just below the current stack limit.  The
1750Sstevel@tonic-gate  * algorithm used for cache consistency on machines with virtual
1760Sstevel@tonic-gate  * address caches is such that offset 0 in the vnode is always
1770Sstevel@tonic-gate  * on a shm_alignment'ed aligned address.  Unfortunately, this
1780Sstevel@tonic-gate  * means that vnodes which are demand paged will not be mapped
1790Sstevel@tonic-gate  * cache consistently with the executable images.  When the
1800Sstevel@tonic-gate  * cache alignment for a given object is inconsistent, the
1810Sstevel@tonic-gate  * lower level code must manage the translations so that this
1820Sstevel@tonic-gate  * is not seen here (at the cost of efficiency, of course).
1830Sstevel@tonic-gate  *
1840Sstevel@tonic-gate  * addrp is a value/result parameter.
1850Sstevel@tonic-gate  *	On input it is a hint from the user to be used in a completely
1860Sstevel@tonic-gate  *	machine dependent fashion.  For MAP_ALIGN, addrp contains the
1870Sstevel@tonic-gate  *	minimal alignment.
1880Sstevel@tonic-gate  *
1890Sstevel@tonic-gate  *	On output it is NULL if no address can be found in the current
1900Sstevel@tonic-gate  *	processes address space or else an address that is currently
1910Sstevel@tonic-gate  *	not mapped for len bytes with a page of red zone on either side.
1920Sstevel@tonic-gate  *	If vacalign is true, then the selected address will obey the alignment
1930Sstevel@tonic-gate  *	constraints of a vac machine based on the given off value.
1940Sstevel@tonic-gate  */
1950Sstevel@tonic-gate /*ARGSUSED3*/
1960Sstevel@tonic-gate void
1970Sstevel@tonic-gate map_addr_proc(caddr_t *addrp, size_t len, offset_t off, int vacalign,
1980Sstevel@tonic-gate     caddr_t userlimit, struct proc *p, uint_t flags)
1990Sstevel@tonic-gate {
2000Sstevel@tonic-gate 	struct as *as = p->p_as;
2010Sstevel@tonic-gate 	caddr_t addr;
2020Sstevel@tonic-gate 	caddr_t base;
2030Sstevel@tonic-gate 	size_t slen;
2040Sstevel@tonic-gate 	uintptr_t align_amount;
2050Sstevel@tonic-gate 	int allow_largepage_alignment = 1;
2060Sstevel@tonic-gate 
2070Sstevel@tonic-gate 	base = p->p_brkbase;
2080Sstevel@tonic-gate 	if (userlimit < as->a_userlimit) {
2090Sstevel@tonic-gate 		/*
2100Sstevel@tonic-gate 		 * This happens when a program wants to map something in
2110Sstevel@tonic-gate 		 * a range that's accessible to a program in a smaller
2120Sstevel@tonic-gate 		 * address space.  For example, a 64-bit program might
2130Sstevel@tonic-gate 		 * be calling mmap32(2) to guarantee that the returned
2140Sstevel@tonic-gate 		 * address is below 4Gbytes.
2150Sstevel@tonic-gate 		 */
2160Sstevel@tonic-gate 		ASSERT(userlimit > base);
2170Sstevel@tonic-gate 		slen = userlimit - base;
2180Sstevel@tonic-gate 	} else {
2190Sstevel@tonic-gate 		slen = p->p_usrstack - base - (((size_t)rctl_enforced_value(
2200Sstevel@tonic-gate 		    rctlproc_legacy[RLIMIT_STACK], p->p_rctls, p) + PAGEOFFSET)
2210Sstevel@tonic-gate 		    & PAGEMASK);
2220Sstevel@tonic-gate 	}
2230Sstevel@tonic-gate 	len = (len + PAGEOFFSET) & PAGEMASK;
2240Sstevel@tonic-gate 
2250Sstevel@tonic-gate 	/*
2260Sstevel@tonic-gate 	 * Redzone for each side of the request. This is done to leave
2270Sstevel@tonic-gate 	 * one page unmapped between segments. This is not required, but
2280Sstevel@tonic-gate 	 * it's useful for the user because if their program strays across
2290Sstevel@tonic-gate 	 * a segment boundary, it will catch a fault immediately making
2300Sstevel@tonic-gate 	 * debugging a little easier.
2310Sstevel@tonic-gate 	 */
2320Sstevel@tonic-gate 	len += (2 * PAGESIZE);
2330Sstevel@tonic-gate 
2340Sstevel@tonic-gate 	/*
2350Sstevel@tonic-gate 	 *  If the request is larger than the size of a particular
2360Sstevel@tonic-gate 	 *  mmu level, then we use that level to map the request.
2370Sstevel@tonic-gate 	 *  But this requires that both the virtual and the physical
2380Sstevel@tonic-gate 	 *  addresses be aligned with respect to that level, so we
2390Sstevel@tonic-gate 	 *  do the virtual bit of nastiness here.
2400Sstevel@tonic-gate 	 *
2410Sstevel@tonic-gate 	 *  For 32-bit processes, only those which have specified
2420Sstevel@tonic-gate 	 *  MAP_ALIGN or an addr will be aligned on a page size > 4MB. Otherwise
2430Sstevel@tonic-gate 	 *  we can potentially waste up to 256MB of the 4G process address
2440Sstevel@tonic-gate 	 *  space just for alignment.
2450Sstevel@tonic-gate 	 *
2460Sstevel@tonic-gate 	 * XXXQ Should iterate trough hw_page_array here to catch
2470Sstevel@tonic-gate 	 * all supported pagesizes
2480Sstevel@tonic-gate 	 */
2490Sstevel@tonic-gate 	if (p->p_model == DATAMODEL_ILP32 && ((flags & MAP_ALIGN) == 0 ||
2500Sstevel@tonic-gate 	    ((uintptr_t)*addrp) != 0)) {
2510Sstevel@tonic-gate 		allow_largepage_alignment = 0;
2520Sstevel@tonic-gate 	}
2530Sstevel@tonic-gate 	if ((mmu_page_sizes == max_mmu_page_sizes) &&
2540Sstevel@tonic-gate 	    allow_largepage_alignment &&
255*5631Swh94709 	    (len >= MMU_PAGESIZE256M)) {	/* 256MB mappings */
2560Sstevel@tonic-gate 		align_amount = MMU_PAGESIZE256M;
2570Sstevel@tonic-gate 	} else if ((mmu_page_sizes == max_mmu_page_sizes) &&
2580Sstevel@tonic-gate 	    allow_largepage_alignment &&
259*5631Swh94709 	    (len >= MMU_PAGESIZE32M)) {	/* 32MB mappings */
2600Sstevel@tonic-gate 		align_amount = MMU_PAGESIZE32M;
2610Sstevel@tonic-gate 	} else if (len >= MMU_PAGESIZE4M) {  /* 4MB mappings */
2620Sstevel@tonic-gate 		align_amount = MMU_PAGESIZE4M;
2630Sstevel@tonic-gate 	} else if (len >= MMU_PAGESIZE512K) { /* 512KB mappings */
2640Sstevel@tonic-gate 		align_amount = MMU_PAGESIZE512K;
2650Sstevel@tonic-gate 	} else if (len >= MMU_PAGESIZE64K) { /* 64KB mappings */
2660Sstevel@tonic-gate 		align_amount = MMU_PAGESIZE64K;
2670Sstevel@tonic-gate 	} else  {
2680Sstevel@tonic-gate 		/*
2690Sstevel@tonic-gate 		 * Align virtual addresses on a 64K boundary to ensure
2700Sstevel@tonic-gate 		 * that ELF shared libraries are mapped with the appropriate
2710Sstevel@tonic-gate 		 * alignment constraints by the run-time linker.
2720Sstevel@tonic-gate 		 */
2730Sstevel@tonic-gate 		align_amount = ELF_SPARC_MAXPGSZ;
2740Sstevel@tonic-gate 		if ((flags & MAP_ALIGN) && ((uintptr_t)*addrp != 0) &&
275*5631Swh94709 		    ((uintptr_t)*addrp < align_amount))
2760Sstevel@tonic-gate 			align_amount = (uintptr_t)*addrp;
2770Sstevel@tonic-gate 	}
2780Sstevel@tonic-gate 
2790Sstevel@tonic-gate 	/*
2800Sstevel@tonic-gate 	 * 64-bit processes require 1024K alignment of ELF shared libraries.
2810Sstevel@tonic-gate 	 */
2820Sstevel@tonic-gate 	if (p->p_model == DATAMODEL_LP64)
2830Sstevel@tonic-gate 		align_amount = MAX(align_amount, ELF_SPARCV9_MAXPGSZ);
2840Sstevel@tonic-gate #ifdef VAC
2850Sstevel@tonic-gate 	if (vac && vacalign && (align_amount < shm_alignment))
2860Sstevel@tonic-gate 		align_amount = shm_alignment;
2870Sstevel@tonic-gate #endif
2880Sstevel@tonic-gate 
2890Sstevel@tonic-gate 	if ((flags & MAP_ALIGN) && ((uintptr_t)*addrp > align_amount)) {
2900Sstevel@tonic-gate 		align_amount = (uintptr_t)*addrp;
2910Sstevel@tonic-gate 	}
2920Sstevel@tonic-gate 	len += align_amount;
2930Sstevel@tonic-gate 
2940Sstevel@tonic-gate 	/*
2950Sstevel@tonic-gate 	 * Look for a large enough hole starting below the stack limit.
2960Sstevel@tonic-gate 	 * After finding it, use the upper part.  Addition of PAGESIZE is
2970Sstevel@tonic-gate 	 * for the redzone as described above.
2980Sstevel@tonic-gate 	 */
2990Sstevel@tonic-gate 	as_purge(as);
3000Sstevel@tonic-gate 	if (as_gap(as, len, &base, &slen, AH_HI, NULL) == 0) {
3010Sstevel@tonic-gate 		caddr_t as_addr;
3020Sstevel@tonic-gate 
3030Sstevel@tonic-gate 		addr = base + slen - len + PAGESIZE;
3040Sstevel@tonic-gate 		as_addr = addr;
3050Sstevel@tonic-gate 		/*
3060Sstevel@tonic-gate 		 * Round address DOWN to the alignment amount,
3070Sstevel@tonic-gate 		 * add the offset, and if this address is less
3080Sstevel@tonic-gate 		 * than the original address, add alignment amount.
3090Sstevel@tonic-gate 		 */
3100Sstevel@tonic-gate 		addr = (caddr_t)((uintptr_t)addr & (~(align_amount - 1l)));
3110Sstevel@tonic-gate 		addr += (long)(off & (align_amount - 1l));
3120Sstevel@tonic-gate 		if (addr < as_addr) {
3130Sstevel@tonic-gate 			addr += align_amount;
3140Sstevel@tonic-gate 		}
3150Sstevel@tonic-gate 
3160Sstevel@tonic-gate 		ASSERT(addr <= (as_addr + align_amount));
3170Sstevel@tonic-gate 		ASSERT(((uintptr_t)addr & (align_amount - 1l)) ==
3180Sstevel@tonic-gate 		    ((uintptr_t)(off & (align_amount - 1l))));
3190Sstevel@tonic-gate 		*addrp = addr;
3200Sstevel@tonic-gate 
3210Sstevel@tonic-gate 	} else {
3220Sstevel@tonic-gate 		*addrp = NULL;	/* no more virtual space */
3230Sstevel@tonic-gate 	}
3240Sstevel@tonic-gate }
3250Sstevel@tonic-gate 
3260Sstevel@tonic-gate /*
3270Sstevel@tonic-gate  * Platform-dependent page scrub call.
3280Sstevel@tonic-gate  * We call hypervisor to scrub the page.
3290Sstevel@tonic-gate  */
3300Sstevel@tonic-gate void
3310Sstevel@tonic-gate pagescrub(page_t *pp, uint_t off, uint_t len)
3320Sstevel@tonic-gate {
3330Sstevel@tonic-gate 	uint64_t pa, length;
3340Sstevel@tonic-gate 
3350Sstevel@tonic-gate 	pa = (uint64_t)(pp->p_pagenum << MMU_PAGESHIFT + off);
3360Sstevel@tonic-gate 	length = (uint64_t)len;
3370Sstevel@tonic-gate 
3380Sstevel@tonic-gate 	(void) mem_scrub(pa, length);
3390Sstevel@tonic-gate }
3400Sstevel@tonic-gate 
3410Sstevel@tonic-gate void
3420Sstevel@tonic-gate sync_data_memory(caddr_t va, size_t len)
3430Sstevel@tonic-gate {
3440Sstevel@tonic-gate 	/* Call memory sync function */
3453199Sep32863 	(void) mem_sync(va, len);
3460Sstevel@tonic-gate }
3470Sstevel@tonic-gate 
3480Sstevel@tonic-gate size_t
3490Sstevel@tonic-gate mmu_get_kernel_lpsize(size_t lpsize)
3500Sstevel@tonic-gate {
3510Sstevel@tonic-gate 	extern int mmu_exported_pagesize_mask;
3520Sstevel@tonic-gate 	uint_t tte;
3530Sstevel@tonic-gate 
3540Sstevel@tonic-gate 	if (lpsize == 0) {
3550Sstevel@tonic-gate 		/* no setting for segkmem_lpsize in /etc/system: use default */
3560Sstevel@tonic-gate 		if (mmu_exported_pagesize_mask & (1 << TTE256M)) {
3570Sstevel@tonic-gate 			lpsize = MMU_PAGESIZE256M;
3580Sstevel@tonic-gate 		} else if (mmu_exported_pagesize_mask & (1 << TTE4M)) {
3590Sstevel@tonic-gate 			lpsize = MMU_PAGESIZE4M;
3600Sstevel@tonic-gate 		} else if (mmu_exported_pagesize_mask & (1 << TTE64K)) {
3610Sstevel@tonic-gate 			lpsize = MMU_PAGESIZE64K;
3620Sstevel@tonic-gate 		} else {
3630Sstevel@tonic-gate 			lpsize = MMU_PAGESIZE;
3640Sstevel@tonic-gate 		}
3650Sstevel@tonic-gate 
3660Sstevel@tonic-gate 		return (lpsize);
3670Sstevel@tonic-gate 	}
3680Sstevel@tonic-gate 
3690Sstevel@tonic-gate 	for (tte = TTE8K; tte <= TTE256M; tte++) {
3700Sstevel@tonic-gate 
3710Sstevel@tonic-gate 		if ((mmu_exported_pagesize_mask & (1 << tte)) == 0)
3720Sstevel@tonic-gate 			continue;
3730Sstevel@tonic-gate 
3740Sstevel@tonic-gate 		if (lpsize == TTEBYTES(tte))
3750Sstevel@tonic-gate 			return (lpsize);
3760Sstevel@tonic-gate 	}
3770Sstevel@tonic-gate 
3780Sstevel@tonic-gate 	lpsize = TTEBYTES(TTE8K);
3790Sstevel@tonic-gate 	return (lpsize);
3800Sstevel@tonic-gate }
3810Sstevel@tonic-gate 
3820Sstevel@tonic-gate void
3830Sstevel@tonic-gate mmu_init_kcontext()
3840Sstevel@tonic-gate {
3850Sstevel@tonic-gate }
3860Sstevel@tonic-gate 
3870Sstevel@tonic-gate /*ARGSUSED*/
3880Sstevel@tonic-gate void
3890Sstevel@tonic-gate mmu_init_kernel_pgsz(struct hat *hat)
3900Sstevel@tonic-gate {
3910Sstevel@tonic-gate }
3920Sstevel@tonic-gate 
3930Sstevel@tonic-gate static void *
3940Sstevel@tonic-gate contig_mem_span_alloc(vmem_t *vmp, size_t size, int vmflag)
3950Sstevel@tonic-gate {
3960Sstevel@tonic-gate 	page_t *ppl;
3970Sstevel@tonic-gate 	page_t *rootpp;
3980Sstevel@tonic-gate 	caddr_t addr = NULL;
3990Sstevel@tonic-gate 	pgcnt_t npages = btopr(size);
4000Sstevel@tonic-gate 	page_t **ppa;
4010Sstevel@tonic-gate 	int pgflags;
4024204Sha137994 	spgcnt_t i = 0;
4030Sstevel@tonic-gate 
4040Sstevel@tonic-gate 
4054204Sha137994 	ASSERT(size <= contig_mem_import_size_max);
4064204Sha137994 	ASSERT((size & (size - 1)) == 0);
4071859Sha137994 
4080Sstevel@tonic-gate 	if ((addr = vmem_xalloc(vmp, size, size, 0, 0,
4090Sstevel@tonic-gate 	    NULL, NULL, vmflag)) == NULL) {
4100Sstevel@tonic-gate 		return (NULL);
4110Sstevel@tonic-gate 	}
4120Sstevel@tonic-gate 
4131859Sha137994 	/* The address should be slab-size aligned. */
4144204Sha137994 	ASSERT(((uintptr_t)addr & (size - 1)) == 0);
4150Sstevel@tonic-gate 
4160Sstevel@tonic-gate 	if (page_resv(npages, vmflag & VM_KMFLAGS) == 0) {
4170Sstevel@tonic-gate 		vmem_xfree(vmp, addr, size);
4180Sstevel@tonic-gate 		return (NULL);
4190Sstevel@tonic-gate 	}
4200Sstevel@tonic-gate 
4210Sstevel@tonic-gate 	pgflags = PG_EXCL;
4224204Sha137994 	if (vmflag & VM_NORELOC)
4234204Sha137994 		pgflags |= PG_NORELOC;
4240Sstevel@tonic-gate 
4250Sstevel@tonic-gate 	ppl = page_create_va_large(&kvp, (u_offset_t)(uintptr_t)addr, size,
4260Sstevel@tonic-gate 	    pgflags, &kvseg, addr, NULL);
4270Sstevel@tonic-gate 
4280Sstevel@tonic-gate 	if (ppl == NULL) {
4290Sstevel@tonic-gate 		vmem_xfree(vmp, addr, size);
4300Sstevel@tonic-gate 		page_unresv(npages);
4310Sstevel@tonic-gate 		return (NULL);
4320Sstevel@tonic-gate 	}
4330Sstevel@tonic-gate 
4340Sstevel@tonic-gate 	rootpp = ppl;
4350Sstevel@tonic-gate 	ppa = kmem_zalloc(npages * sizeof (page_t *), KM_SLEEP);
4360Sstevel@tonic-gate 	while (ppl != NULL) {
4370Sstevel@tonic-gate 		page_t *pp = ppl;
4380Sstevel@tonic-gate 		ppa[i++] = pp;
4390Sstevel@tonic-gate 		page_sub(&ppl, pp);
4400Sstevel@tonic-gate 		ASSERT(page_iolock_assert(pp));
4414204Sha137994 		ASSERT(PAGE_EXCL(pp));
4420Sstevel@tonic-gate 		page_io_unlock(pp);
4430Sstevel@tonic-gate 	}
4440Sstevel@tonic-gate 
4450Sstevel@tonic-gate 	/*
4460Sstevel@tonic-gate 	 * Load the locked entry.  It's OK to preload the entry into
4470Sstevel@tonic-gate 	 * the TSB since we now support large mappings in the kernel TSB.
4480Sstevel@tonic-gate 	 */
4490Sstevel@tonic-gate 	hat_memload_array(kas.a_hat, (caddr_t)rootpp->p_offset, size,
4500Sstevel@tonic-gate 	    ppa, (PROT_ALL & ~PROT_USER) | HAT_NOSYNC, HAT_LOAD_LOCK);
4510Sstevel@tonic-gate 
4524204Sha137994 	ASSERT(i == page_get_pagecnt(ppa[0]->p_szc));
4530Sstevel@tonic-gate 	for (--i; i >= 0; --i) {
4544204Sha137994 		ASSERT(ppa[i]->p_szc == ppa[0]->p_szc);
4554204Sha137994 		ASSERT(page_pptonum(ppa[i]) == page_pptonum(ppa[0]) + i);
4560Sstevel@tonic-gate 		(void) page_pp_lock(ppa[i], 0, 1);
4574204Sha137994 		/*
4584204Sha137994 		 * Leave the page share locked. For non-cage pages,
4594204Sha137994 		 * this would prevent memory DR if it were supported
4604204Sha137994 		 * on sun4v.
4614204Sha137994 		 */
4624204Sha137994 		page_downgrade(ppa[i]);
4630Sstevel@tonic-gate 	}
4640Sstevel@tonic-gate 
4650Sstevel@tonic-gate 	kmem_free(ppa, npages * sizeof (page_t *));
4660Sstevel@tonic-gate 	return (addr);
4670Sstevel@tonic-gate }
4680Sstevel@tonic-gate 
4694204Sha137994 /*
4704204Sha137994  * Allocates a slab by first trying to use the largest slab size
4714204Sha137994  * in contig_mem_import_sizes and then falling back to smaller slab
4724204Sha137994  * sizes still large enough for the allocation. The sizep argument
4734204Sha137994  * is a pointer to the requested size. When a slab is successfully
4744204Sha137994  * allocated, the slab size, which must be >= *sizep and <=
4754204Sha137994  * contig_mem_import_size_max, is returned in the *sizep argument.
4764204Sha137994  * Returns the virtual address of the new slab.
4774204Sha137994  */
4784204Sha137994 static void *
4794204Sha137994 span_alloc_downsize(vmem_t *vmp, size_t *sizep, size_t align, int vmflag)
4804204Sha137994 {
4814204Sha137994 	int i;
4824204Sha137994 
4834204Sha137994 	ASSERT(*sizep <= contig_mem_import_size_max);
4844204Sha137994 
4854204Sha137994 	for (i = 0; i < NUM_IMPORT_SIZES; i++) {
4864204Sha137994 		size_t page_size = contig_mem_import_sizes[i];
4874204Sha137994 
4884204Sha137994 		/*
4894204Sha137994 		 * Check that the alignment is also less than the
4904204Sha137994 		 * import (large page) size. In the case where the
4914204Sha137994 		 * alignment is larger than the size, a large page
4924204Sha137994 		 * large enough for the allocation is not necessarily
4934204Sha137994 		 * physical-address aligned to satisfy the requested
4944204Sha137994 		 * alignment. Since alignment is required to be a
4954204Sha137994 		 * power-of-2, any large page >= size && >= align will
4964204Sha137994 		 * suffice.
4974204Sha137994 		 */
4984204Sha137994 		if (*sizep <= page_size && align <= page_size) {
4994204Sha137994 			void *addr;
5004204Sha137994 			addr = contig_mem_span_alloc(vmp, page_size, vmflag);
5014204Sha137994 			if (addr == NULL)
5024204Sha137994 				continue;
5034204Sha137994 			*sizep = page_size;
5044204Sha137994 			return (addr);
5054204Sha137994 		}
5064204Sha137994 		return (NULL);
5074204Sha137994 	}
5084204Sha137994 
5094204Sha137994 	return (NULL);
5104204Sha137994 }
5114204Sha137994 
5124204Sha137994 static void *
5134204Sha137994 contig_mem_span_xalloc(vmem_t *vmp, size_t *sizep, size_t align, int vmflag)
5144204Sha137994 {
5154204Sha137994 	return (span_alloc_downsize(vmp, sizep, align, vmflag | VM_NORELOC));
5164204Sha137994 }
5174204Sha137994 
5184204Sha137994 static void *
5194204Sha137994 contig_mem_reloc_span_xalloc(vmem_t *vmp, size_t *sizep, size_t align,
5204204Sha137994     int vmflag)
5214204Sha137994 {
5224204Sha137994 	ASSERT((vmflag & VM_NORELOC) == 0);
5234204Sha137994 	return (span_alloc_downsize(vmp, sizep, align, vmflag));
5244204Sha137994 }
5254204Sha137994 
5264204Sha137994 /*
5274204Sha137994  * Free a span, which is always exactly one large page.
5284204Sha137994  */
5294204Sha137994 static void
5300Sstevel@tonic-gate contig_mem_span_free(vmem_t *vmp, void *inaddr, size_t size)
5310Sstevel@tonic-gate {
5320Sstevel@tonic-gate 	page_t *pp;
5330Sstevel@tonic-gate 	caddr_t addr = inaddr;
5340Sstevel@tonic-gate 	caddr_t eaddr;
5350Sstevel@tonic-gate 	pgcnt_t npages = btopr(size);
5360Sstevel@tonic-gate 	page_t *rootpp = NULL;
5370Sstevel@tonic-gate 
5384204Sha137994 	ASSERT(size <= contig_mem_import_size_max);
5394204Sha137994 	/* All slabs should be size aligned */
5404204Sha137994 	ASSERT(((uintptr_t)addr & (size - 1)) == 0);
5410Sstevel@tonic-gate 
5420Sstevel@tonic-gate 	hat_unload(kas.a_hat, addr, size, HAT_UNLOAD_UNLOCK);
5430Sstevel@tonic-gate 
5440Sstevel@tonic-gate 	for (eaddr = addr + size; addr < eaddr; addr += PAGESIZE) {
5454204Sha137994 		pp = page_find(&kvp, (u_offset_t)(uintptr_t)addr);
5464204Sha137994 		if (pp == NULL) {
5470Sstevel@tonic-gate 			panic("contig_mem_span_free: page not found");
5484204Sha137994 		}
5494204Sha137994 		if (!page_tryupgrade(pp)) {
5504204Sha137994 			page_unlock(pp);
5514204Sha137994 			pp = page_lookup(&kvp,
5524204Sha137994 			    (u_offset_t)(uintptr_t)addr, SE_EXCL);
5534204Sha137994 			if (pp == NULL)
5544204Sha137994 				panic("contig_mem_span_free: page not found");
5554204Sha137994 		}
5560Sstevel@tonic-gate 
5570Sstevel@tonic-gate 		ASSERT(PAGE_EXCL(pp));
5584204Sha137994 		ASSERT(size == page_get_pagesize(pp->p_szc));
5594204Sha137994 		ASSERT(rootpp == NULL || rootpp->p_szc == pp->p_szc);
5604204Sha137994 		ASSERT(rootpp == NULL || (page_pptonum(rootpp) +
5614204Sha137994 		    (pgcnt_t)btop(addr - (caddr_t)inaddr) == page_pptonum(pp)));
5624204Sha137994 
5630Sstevel@tonic-gate 		page_pp_unlock(pp, 0, 1);
5640Sstevel@tonic-gate 
5650Sstevel@tonic-gate 		if (rootpp == NULL)
5660Sstevel@tonic-gate 			rootpp = pp;
5670Sstevel@tonic-gate 	}
5684204Sha137994 	page_destroy_pages(rootpp);
5690Sstevel@tonic-gate 	page_unresv(npages);
5700Sstevel@tonic-gate 
5710Sstevel@tonic-gate 	if (vmp != NULL)
5720Sstevel@tonic-gate 		vmem_xfree(vmp, inaddr, size);
5730Sstevel@tonic-gate }
5740Sstevel@tonic-gate 
5750Sstevel@tonic-gate static void *
5764204Sha137994 contig_vmem_xalloc_aligned_wrapper(vmem_t *vmp, size_t *sizep, size_t align,
5774204Sha137994     int vmflag)
5780Sstevel@tonic-gate {
5794204Sha137994 	ASSERT((align & (align - 1)) == 0);
5804204Sha137994 	return (vmem_xalloc(vmp, *sizep, align, 0, 0, NULL, NULL, vmflag));
5810Sstevel@tonic-gate }
5820Sstevel@tonic-gate 
583288Sarao /*
5844204Sha137994  * contig_mem_alloc, contig_mem_alloc_align
5854204Sha137994  *
5864204Sha137994  * Caution: contig_mem_alloc and contig_mem_alloc_align should be
5874204Sha137994  * used only when physically contiguous non-relocatable memory is
5884204Sha137994  * required. Furthermore, use of these allocation routines should be
5894204Sha137994  * minimized as well as should the allocation size. As described in the
5904204Sha137994  * contig_mem_arena comment block above, slab allocations fall back to
5914204Sha137994  * being outside of the cage. Therefore, overuse of these allocation
5924204Sha137994  * routines can lead to non-relocatable large pages being allocated
5934204Sha137994  * outside the cage. Such pages prevent the allocation of a larger page
5944204Sha137994  * occupying overlapping pages. This can impact performance for
5954204Sha137994  * applications that utilize e.g. 256M large pages.
596288Sarao  */
597288Sarao 
598288Sarao /*
5994204Sha137994  * Allocates size aligned contiguous memory up to contig_mem_import_size_max.
600288Sarao  * Size must be a power of 2.
601288Sarao  */
6020Sstevel@tonic-gate void *
6030Sstevel@tonic-gate contig_mem_alloc(size_t size)
6040Sstevel@tonic-gate {
605288Sarao 	ASSERT((size & (size - 1)) == 0);
606288Sarao 	return (contig_mem_alloc_align(size, size));
6070Sstevel@tonic-gate }
6080Sstevel@tonic-gate 
6094204Sha137994 /*
6104204Sha137994  * contig_mem_alloc_align allocates real contiguous memory with the specified
6114204Sha137994  * alignment up to contig_mem_import_size_max. The alignment must be a
6124204Sha137994  * power of 2 and no greater than contig_mem_import_size_max. We assert
6134204Sha137994  * the aligment is a power of 2. For non-debug, vmem_xalloc will panic
6144204Sha137994  * for non power of 2 alignments.
6154204Sha137994  */
6164204Sha137994 void *
6174204Sha137994 contig_mem_alloc_align(size_t size, size_t align)
6184204Sha137994 {
6194204Sha137994 	void *buf;
6204204Sha137994 
6214204Sha137994 	ASSERT(size <= contig_mem_import_size_max);
6224204Sha137994 	ASSERT(align <= contig_mem_import_size_max);
6234204Sha137994 	ASSERT((align & (align - 1)) == 0);
6244204Sha137994 
6254204Sha137994 	if (align < CONTIG_MEM_ARENA_QUANTUM)
6264204Sha137994 		align = CONTIG_MEM_ARENA_QUANTUM;
6274204Sha137994 
6284204Sha137994 	/*
6294204Sha137994 	 * We take the lock here to serialize span allocations.
6304204Sha137994 	 * We do not lose concurrency for the common case, since
6314204Sha137994 	 * allocations that don't require new span allocations
6324204Sha137994 	 * are serialized by vmem_xalloc. Serializing span
6334204Sha137994 	 * allocations also prevents us from trying to allocate
6344204Sha137994 	 * more spans that necessary.
6354204Sha137994 	 */
6364204Sha137994 	mutex_enter(&contig_mem_lock);
6374204Sha137994 
6384204Sha137994 	buf = vmem_xalloc(contig_mem_arena, size, align, 0, 0,
6394204Sha137994 	    NULL, NULL, VM_NOSLEEP | VM_NORELOC);
6404204Sha137994 
6414204Sha137994 	if ((buf == NULL) && (size <= MMU_PAGESIZE)) {
6424204Sha137994 		mutex_exit(&contig_mem_lock);
6434204Sha137994 		return (vmem_xalloc(static_alloc_arena, size, align, 0, 0,
6444204Sha137994 		    NULL, NULL, VM_NOSLEEP));
6454204Sha137994 	}
6464204Sha137994 
6474204Sha137994 	if (buf == NULL) {
6484204Sha137994 		buf = vmem_xalloc(contig_mem_reloc_arena, size, align, 0, 0,
6494204Sha137994 		    NULL, NULL, VM_NOSLEEP);
6504204Sha137994 	}
6514204Sha137994 
6524204Sha137994 	mutex_exit(&contig_mem_lock);
6534204Sha137994 
6544204Sha137994 	return (buf);
6554204Sha137994 }
6564204Sha137994 
6570Sstevel@tonic-gate void
6580Sstevel@tonic-gate contig_mem_free(void *vaddr, size_t size)
6590Sstevel@tonic-gate {
6604204Sha137994 	if (vmem_contains(contig_mem_arena, vaddr, size)) {
6614204Sha137994 		vmem_xfree(contig_mem_arena, vaddr, size);
6624204Sha137994 	} else if (size > MMU_PAGESIZE) {
6634204Sha137994 		vmem_xfree(contig_mem_reloc_arena, vaddr, size);
6644204Sha137994 	} else {
6654204Sha137994 		vmem_xfree(static_alloc_arena, vaddr, size);
6664204Sha137994 	}
6670Sstevel@tonic-gate }
6680Sstevel@tonic-gate 
6690Sstevel@tonic-gate /*
6700Sstevel@tonic-gate  * We create a set of stacked vmem arenas to enable us to
6714204Sha137994  * allocate large >PAGESIZE chucks of contiguous Real Address space.
6724204Sha137994  * The vmem_xcreate interface is used to create the contig_mem_arena
6734204Sha137994  * allowing the import routine to downsize the requested slab size
6744204Sha137994  * and return a smaller slab.
6750Sstevel@tonic-gate  */
6760Sstevel@tonic-gate void
6770Sstevel@tonic-gate contig_mem_init(void)
6780Sstevel@tonic-gate {
6794204Sha137994 	mutex_init(&contig_mem_lock, NULL, MUTEX_DEFAULT, NULL);
6800Sstevel@tonic-gate 
6814204Sha137994 	contig_mem_slab_arena = vmem_xcreate("contig_mem_slab_arena", NULL, 0,
6824204Sha137994 	    CONTIG_MEM_SLAB_ARENA_QUANTUM, contig_vmem_xalloc_aligned_wrapper,
6834204Sha137994 	    vmem_xfree, heap_arena, 0, VM_SLEEP | VMC_XALIGN);
6840Sstevel@tonic-gate 
6854204Sha137994 	contig_mem_arena = vmem_xcreate("contig_mem_arena", NULL, 0,
6864204Sha137994 	    CONTIG_MEM_ARENA_QUANTUM, contig_mem_span_xalloc,
6874204Sha137994 	    contig_mem_span_free, contig_mem_slab_arena, 0,
6884204Sha137994 	    VM_SLEEP | VM_BESTFIT | VMC_XALIGN);
6890Sstevel@tonic-gate 
6904204Sha137994 	contig_mem_reloc_arena = vmem_xcreate("contig_mem_reloc_arena", NULL, 0,
6914204Sha137994 	    CONTIG_MEM_ARENA_QUANTUM, contig_mem_reloc_span_xalloc,
6924204Sha137994 	    contig_mem_span_free, contig_mem_slab_arena, 0,
6934204Sha137994 	    VM_SLEEP | VM_BESTFIT | VMC_XALIGN);
6944204Sha137994 
695*5631Swh94709 	if (vmem_add(contig_mem_arena, contig_mem_prealloc_buf,
696*5631Swh94709 	    contig_mem_prealloc_size, VM_SLEEP) == NULL)
6974204Sha137994 		cmn_err(CE_PANIC, "Failed to pre-populate contig_mem_arena");
6980Sstevel@tonic-gate }
6993177Sdp78419 
7004204Sha137994 /*
7014204Sha137994  * In calculating how much memory to pre-allocate, we include a small
7024204Sha137994  * amount per-CPU to account for per-CPU buffers in line with measured
703*5631Swh94709  * values for different size systems. contig_mem_prealloc_base_size is
704*5631Swh94709  * a cpu specific amount to be pre-allocated before considering per-CPU
705*5631Swh94709  * requirements and memory size. We always pre-allocate a minimum amount
706*5631Swh94709  * of memory determined by PREALLOC_MIN. Beyond that, we take the minimum
707*5631Swh94709  * of contig_mem_prealloc_base_size and a small percentage of physical
708*5631Swh94709  * memory to prevent allocating too much on smaller systems.
709*5631Swh94709  * contig_mem_prealloc_base_size is global, allowing for the CPU module
710*5631Swh94709  * to increase its value if necessary.
7114204Sha137994  */
7124204Sha137994 #define	PREALLOC_PER_CPU	(256 * 1024)		/* 256K */
7134204Sha137994 #define	PREALLOC_PERCENT	(4)			/* 4% */
7144204Sha137994 #define	PREALLOC_MIN		(16 * 1024 * 1024)	/* 16M */
715*5631Swh94709 size_t contig_mem_prealloc_base_size = 0;
7164204Sha137994 
7174204Sha137994 /*
7184204Sha137994  * Called at boot-time allowing pre-allocation of contiguous memory.
7194204Sha137994  * The argument 'alloc_base' is the requested base address for the
7204204Sha137994  * allocation and originates in startup_memlist.
7214204Sha137994  */
7224204Sha137994 caddr_t
7234204Sha137994 contig_mem_prealloc(caddr_t alloc_base, pgcnt_t npages)
7244204Sha137994 {
725*5631Swh94709 	contig_mem_prealloc_size = MIN((PREALLOC_PER_CPU * ncpu_guest_max) +
726*5631Swh94709 	    contig_mem_prealloc_base_size,
727*5631Swh94709 	    (ptob(npages) * PREALLOC_PERCENT) / 100);
728*5631Swh94709 	contig_mem_prealloc_size = MAX(contig_mem_prealloc_size, PREALLOC_MIN);
729*5631Swh94709 	contig_mem_prealloc_size = P2ROUNDUP(contig_mem_prealloc_size,
730*5631Swh94709 	    MMU_PAGESIZE4M);
7314204Sha137994 
7324204Sha137994 	alloc_base = (caddr_t)roundup((uintptr_t)alloc_base, MMU_PAGESIZE4M);
733*5631Swh94709 	contig_mem_prealloc_buf = alloc_base;
734*5631Swh94709 	alloc_base += contig_mem_prealloc_size;
7354204Sha137994 
7364204Sha137994 	return (alloc_base);
7374204Sha137994 }
7383177Sdp78419 
7393177Sdp78419 static uint_t sp_color_stride = 16;
7403177Sdp78419 static uint_t sp_color_mask = 0x1f;
7413177Sdp78419 static uint_t sp_current_color = (uint_t)-1;
7423177Sdp78419 
7433177Sdp78419 size_t
7443177Sdp78419 exec_get_spslew(void)
7453177Sdp78419 {
7463177Sdp78419 	uint_t spcolor = atomic_inc_32_nv(&sp_current_color);
7473177Sdp78419 	return ((size_t)((spcolor & sp_color_mask) * SA(sp_color_stride)));
7483177Sdp78419 }
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