xref: /onnv-gate/usr/src/uts/sun4v/sys/machintreg.h (revision 5513:874db86a55c3)
10Sstevel@tonic-gate /*
20Sstevel@tonic-gate  * CDDL HEADER START
30Sstevel@tonic-gate  *
40Sstevel@tonic-gate  * The contents of this file are subject to the terms of the
5*5513Slm66018  * Common Development and Distribution License (the "License").
6*5513Slm66018  * You may not use this file except in compliance with the License.
70Sstevel@tonic-gate  *
80Sstevel@tonic-gate  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
90Sstevel@tonic-gate  * or http://www.opensolaris.org/os/licensing.
100Sstevel@tonic-gate  * See the License for the specific language governing permissions
110Sstevel@tonic-gate  * and limitations under the License.
120Sstevel@tonic-gate  *
130Sstevel@tonic-gate  * When distributing Covered Code, include this CDDL HEADER in each
140Sstevel@tonic-gate  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
150Sstevel@tonic-gate  * If applicable, add the following below this CDDL HEADER, with the
160Sstevel@tonic-gate  * fields enclosed by brackets "[]" replaced with your own identifying
170Sstevel@tonic-gate  * information: Portions Copyright [yyyy] [name of copyright owner]
180Sstevel@tonic-gate  *
190Sstevel@tonic-gate  * CDDL HEADER END
200Sstevel@tonic-gate  */
210Sstevel@tonic-gate /*
22*5513Slm66018  * Copyright 2007 Sun Microsystems, Inc.  All rights reserved.
230Sstevel@tonic-gate  * Use is subject to license terms.
240Sstevel@tonic-gate  */
250Sstevel@tonic-gate 
260Sstevel@tonic-gate #ifndef _SYS_MACHINTREG_H
270Sstevel@tonic-gate #define	_SYS_MACHINTREG_H
280Sstevel@tonic-gate 
290Sstevel@tonic-gate #pragma ident	"%Z%%M%	%I%	%E% SMI"
300Sstevel@tonic-gate 
310Sstevel@tonic-gate #ifdef	__cplusplus
320Sstevel@tonic-gate extern "C" {
330Sstevel@tonic-gate #endif
340Sstevel@tonic-gate 
350Sstevel@tonic-gate /*
360Sstevel@tonic-gate  * IGN_SIZE can be defined in a platform's makefile. If it is not defined,
370Sstevel@tonic-gate  * use a default of 5.
380Sstevel@tonic-gate  */
390Sstevel@tonic-gate #ifndef IGN_SIZE
400Sstevel@tonic-gate #define	IGN_SIZE	5		/* Interrupt Group Number bit size */
410Sstevel@tonic-gate #endif
420Sstevel@tonic-gate #define	UPAID_TO_IGN(upaid) (upaid)
430Sstevel@tonic-gate 
440Sstevel@tonic-gate /*
45*5513Slm66018  * MAXVINTRS is the number of interrupts we require to be allocated
46*5513Slm66018  * in the system intr_vec_table in addition to the hardware interrupts.
47*5513Slm66018  * These interrupts will be used by the sun4v cnex driver for its Logical
48*5513Slm66018  * Domain Channels. Each LDC requires a pair of interrupts, (RX/TX),
49*5513Slm66018  * and the total number of interrupts required will depend on the
50*5513Slm66018  * resources available to the system (CPUs, memory, etc) and how
51*5513Slm66018  * the system domains are configured, (number of virtual disks/networks
52*5513Slm66018  * per domain etc).
53*5513Slm66018  *
54*5513Slm66018  * The service domain requires (at least) a console LDC, Domain Services
55*5513Slm66018  * LDCs, vdisk LDC and vnet LDC per guest domain. It also requires a small
56*5513Slm66018  * number of LDCs for communications with the SP etc.
57*5513Slm66018  *
58*5513Slm66018  * The number of LDCs required is ~(N * 4 + a few more) where N is the
59*5513Slm66018  * possible maximum guest domains. The current possible maximum
60*5513Slm66018  * number of domains is 512, so we require ~2048 LDCs. And as
61*5513Slm66018  * each LDC requires a pair of interrupts we need to add the
62*5513Slm66018  * capacity for ~4096 interrupts to the system interrupt table.
63*5513Slm66018  *
64*5513Slm66018  * We start allocating the LDC interrupts at MINVINTR_COOKIE.
65*5513Slm66018  */
66*5513Slm66018 #define	MINVINTR_COOKIE		(MAXDEVINTRS)
67*5513Slm66018 #define	MAXVINTRS		4096
68*5513Slm66018 
69*5513Slm66018 /*
700Sstevel@tonic-gate  * CPU_MONDO and DEV_MONDO  registers
710Sstevel@tonic-gate  * for sun4v class of cpus probably should
720Sstevel@tonic-gate  * be moved to a new file
730Sstevel@tonic-gate  */
740Sstevel@tonic-gate #define	CPU_MONDO_Q_HD	0x3c0
750Sstevel@tonic-gate #define	CPU_MONDO_Q_TL	0x3c8
760Sstevel@tonic-gate #define	DEV_MONDO_Q_HD	0x3d0
770Sstevel@tonic-gate #define	DEV_MONDO_Q_TL	0x3d8
780Sstevel@tonic-gate 
790Sstevel@tonic-gate /*
800Sstevel@tonic-gate  * RESUMABLE_ERROR and NONRESUMABLE_ERROR registers
810Sstevel@tonic-gate  * for sun4v class of cpus
820Sstevel@tonic-gate  */
830Sstevel@tonic-gate #define	CPU_RQ_HD		0x3e0
840Sstevel@tonic-gate #define	CPU_RQ_TL		0x3e8
850Sstevel@tonic-gate #define	CPU_NRQ_HD		0x3f0
860Sstevel@tonic-gate #define	CPU_NRQ_TL		0x3f8
870Sstevel@tonic-gate 
880Sstevel@tonic-gate #ifdef	__cplusplus
890Sstevel@tonic-gate }
900Sstevel@tonic-gate #endif
910Sstevel@tonic-gate 
920Sstevel@tonic-gate #endif	/* _SYS_MACHINTREG_H */
93