1*0Sstevel@tonic-gate /* 2*0Sstevel@tonic-gate * CDDL HEADER START 3*0Sstevel@tonic-gate * 4*0Sstevel@tonic-gate * The contents of this file are subject to the terms of the 5*0Sstevel@tonic-gate * Common Development and Distribution License, Version 1.0 only 6*0Sstevel@tonic-gate * (the "License"). You may not use this file except in compliance 7*0Sstevel@tonic-gate * with the License. 8*0Sstevel@tonic-gate * 9*0Sstevel@tonic-gate * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10*0Sstevel@tonic-gate * or http://www.opensolaris.org/os/licensing. 11*0Sstevel@tonic-gate * See the License for the specific language governing permissions 12*0Sstevel@tonic-gate * and limitations under the License. 13*0Sstevel@tonic-gate * 14*0Sstevel@tonic-gate * When distributing Covered Code, include this CDDL HEADER in each 15*0Sstevel@tonic-gate * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16*0Sstevel@tonic-gate * If applicable, add the following below this CDDL HEADER, with the 17*0Sstevel@tonic-gate * fields enclosed by brackets "[]" replaced with your own identifying 18*0Sstevel@tonic-gate * information: Portions Copyright [yyyy] [name of copyright owner] 19*0Sstevel@tonic-gate * 20*0Sstevel@tonic-gate * CDDL HEADER END 21*0Sstevel@tonic-gate */ 22*0Sstevel@tonic-gate /* 23*0Sstevel@tonic-gate * Copyright 2005 Sun Microsystems, Inc. All rights reserved. 24*0Sstevel@tonic-gate * Use is subject to license terms. 25*0Sstevel@tonic-gate */ 26*0Sstevel@tonic-gate 27*0Sstevel@tonic-gate #ifndef _SYS_HYPERVISOR_API_H 28*0Sstevel@tonic-gate #define _SYS_HYPERVISOR_API_H 29*0Sstevel@tonic-gate 30*0Sstevel@tonic-gate #pragma ident "%Z%%M% %I% %E% SMI" 31*0Sstevel@tonic-gate 32*0Sstevel@tonic-gate /* 33*0Sstevel@tonic-gate * sun4v Hypervisor API 34*0Sstevel@tonic-gate * 35*0Sstevel@tonic-gate * Reference: api.pdf Revision 0.12 dated May 12, 2004. 36*0Sstevel@tonic-gate * io-api.txt version 1.11 dated 10/19/2004 37*0Sstevel@tonic-gate */ 38*0Sstevel@tonic-gate 39*0Sstevel@tonic-gate #ifdef __cplusplus 40*0Sstevel@tonic-gate extern "C" { 41*0Sstevel@tonic-gate #endif 42*0Sstevel@tonic-gate 43*0Sstevel@tonic-gate /* 44*0Sstevel@tonic-gate * Trap types 45*0Sstevel@tonic-gate */ 46*0Sstevel@tonic-gate #define FAST_TRAP 0x80 /* Function # in %o5 */ 47*0Sstevel@tonic-gate #define CPU_TICK_NPT 0x81 48*0Sstevel@tonic-gate #define CPU_STICK_NPT 0x82 49*0Sstevel@tonic-gate #define MMU_MAP_ADDR 0x83 50*0Sstevel@tonic-gate #define MMU_UNMAP_ADDR 0x84 51*0Sstevel@tonic-gate 52*0Sstevel@tonic-gate /* 53*0Sstevel@tonic-gate * Error returns in %o0. 54*0Sstevel@tonic-gate * (Additional result is returned in %o1.) 55*0Sstevel@tonic-gate */ 56*0Sstevel@tonic-gate #define H_EOK 0 /* Successful return */ 57*0Sstevel@tonic-gate #define H_ENOCPU 1 /* Invalid CPU id */ 58*0Sstevel@tonic-gate #define H_ENORADDR 2 /* Invalid real address */ 59*0Sstevel@tonic-gate #define H_ENOINTR 3 /* Invalid interrupt id */ 60*0Sstevel@tonic-gate #define H_EBADPGSZ 4 /* Invalid pagesize encoding */ 61*0Sstevel@tonic-gate #define H_EBADTSB 5 /* Invalid TSB description */ 62*0Sstevel@tonic-gate #define H_EINVAL 6 /* Invalid argument */ 63*0Sstevel@tonic-gate #define H_EBADTRAP 7 /* Invalid function number */ 64*0Sstevel@tonic-gate #define H_EBADALIGN 8 /* Invalid address alignment */ 65*0Sstevel@tonic-gate #define H_EWOULDBLOCK 9 /* Cannot complete operation */ 66*0Sstevel@tonic-gate /* without blocking */ 67*0Sstevel@tonic-gate #define H_ENOACCESS 10 /* No access to resource */ 68*0Sstevel@tonic-gate #define H_EIO 11 /* I/O error */ 69*0Sstevel@tonic-gate #define H_ECPUERROR 12 /* CPU is in error state */ 70*0Sstevel@tonic-gate #define H_ENOTSUPPORTED 13 /* Function not supported */ 71*0Sstevel@tonic-gate #define H_ENOMAP 14 /* Mapping is not valid, */ 72*0Sstevel@tonic-gate /* no translation exists */ 73*0Sstevel@tonic-gate 74*0Sstevel@tonic-gate #define H_BREAK -1 /* Console Break */ 75*0Sstevel@tonic-gate #define H_HUP -2 /* Console Break */ 76*0Sstevel@tonic-gate /* 77*0Sstevel@tonic-gate * Function numbers for FAST_TRAP. 78*0Sstevel@tonic-gate */ 79*0Sstevel@tonic-gate #define HV_MACH_EXIT 0x00 80*0Sstevel@tonic-gate #define HV_MACH_DESC 0x01 81*0Sstevel@tonic-gate #define HV_CPU_YIELD 0x12 82*0Sstevel@tonic-gate #define CPU_QCONF 0x14 83*0Sstevel@tonic-gate #define HV_CPU_STATE 0x17 84*0Sstevel@tonic-gate #define MMU_TSB_CTX0 0x20 85*0Sstevel@tonic-gate #define MMU_TSB_CTXNON0 0x21 86*0Sstevel@tonic-gate #define MMU_DEMAP_PAGE 0x22 87*0Sstevel@tonic-gate #define MMU_DEMAP_CTX 0x23 88*0Sstevel@tonic-gate #define MMU_DEMAP_ALL 0x24 89*0Sstevel@tonic-gate #define MAP_PERM_ADDR 0x25 90*0Sstevel@tonic-gate #define MMU_SET_INFOPTR 0x26 91*0Sstevel@tonic-gate #define UNMAP_PERM_ADDR 0x28 92*0Sstevel@tonic-gate #define HV_MEM_SCRUB 0x31 93*0Sstevel@tonic-gate #define HV_MEM_SYNC 0x32 94*0Sstevel@tonic-gate #define HV_INTR_SEND 0x42 95*0Sstevel@tonic-gate #define TOD_GET 0x50 96*0Sstevel@tonic-gate #define TOD_SET 0x51 97*0Sstevel@tonic-gate #define CONS_READ 0x60 98*0Sstevel@tonic-gate #define CONS_WRITE 0x61 99*0Sstevel@tonic-gate 100*0Sstevel@tonic-gate #define SVC_SEND 0x80 101*0Sstevel@tonic-gate #define SVC_RECV 0x81 102*0Sstevel@tonic-gate #define SVC_GETSTATUS 0x82 103*0Sstevel@tonic-gate #define SVC_SETSTATUS 0x83 104*0Sstevel@tonic-gate #define SVC_CLRSTATUS 0x84 105*0Sstevel@tonic-gate 106*0Sstevel@tonic-gate #define TTRACE_BUF_CONF 0x90 107*0Sstevel@tonic-gate #define TTRACE_BUF_INFO 0x91 108*0Sstevel@tonic-gate #define TTRACE_ENABLE 0x92 109*0Sstevel@tonic-gate #define TTRACE_FREEZE 0x93 110*0Sstevel@tonic-gate 111*0Sstevel@tonic-gate #define DUMP_BUF_UPDATE 0x94 112*0Sstevel@tonic-gate 113*0Sstevel@tonic-gate #define HVIO_INTR_DEVINO2SYSINO 0xa0 114*0Sstevel@tonic-gate #define HVIO_INTR_GETVALID 0xa1 115*0Sstevel@tonic-gate #define HVIO_INTR_SETVALID 0xa2 116*0Sstevel@tonic-gate #define HVIO_INTR_GETSTATE 0xa3 117*0Sstevel@tonic-gate #define HVIO_INTR_SETSTATE 0xa4 118*0Sstevel@tonic-gate #define HVIO_INTR_GETTARGET 0xa5 119*0Sstevel@tonic-gate #define HVIO_INTR_SETTARGET 0xa6 120*0Sstevel@tonic-gate 121*0Sstevel@tonic-gate #define HVIO_IOMMU_MAP 0xb0 122*0Sstevel@tonic-gate #define HVIO_IOMMU_DEMAP 0xb1 123*0Sstevel@tonic-gate #define HVIO_IOMMU_GETMAP 0xb2 124*0Sstevel@tonic-gate #define HVIO_IOMMU_GETBYPASS 0xb3 125*0Sstevel@tonic-gate 126*0Sstevel@tonic-gate #define HVIO_CONFIG_GET 0xb4 127*0Sstevel@tonic-gate #define HVIO_CONFIG_PUT 0xb5 128*0Sstevel@tonic-gate 129*0Sstevel@tonic-gate #define HVIO_PEEK 0xb6 130*0Sstevel@tonic-gate #define HVIO_POKE 0xb7 131*0Sstevel@tonic-gate 132*0Sstevel@tonic-gate #define HVIO_DMA_SYNC 0xb8 133*0Sstevel@tonic-gate 134*0Sstevel@tonic-gate #define HVIO_MSIQ_CONF 0xc0 135*0Sstevel@tonic-gate #define HVIO_MSIQ_INFO 0xc1 136*0Sstevel@tonic-gate #define HVIO_MSIQ_GETVALID 0xc2 137*0Sstevel@tonic-gate #define HVIO_MSIQ_SETVALID 0xc3 138*0Sstevel@tonic-gate #define HVIO_MSIQ_GETSTATE 0xc4 139*0Sstevel@tonic-gate #define HVIO_MSIQ_SETSTATE 0xc5 140*0Sstevel@tonic-gate #define HVIO_MSIQ_GETHEAD 0xc6 141*0Sstevel@tonic-gate #define HVIO_MSIQ_SETHEAD 0xc7 142*0Sstevel@tonic-gate #define HVIO_MSIQ_GETTAIL 0xc8 143*0Sstevel@tonic-gate 144*0Sstevel@tonic-gate #define HVIO_MSI_GETVALID 0xc9 145*0Sstevel@tonic-gate #define HVIO_MSI_SETVALID 0xca 146*0Sstevel@tonic-gate #define HVIO_MSI_GETMSIQ 0xcb 147*0Sstevel@tonic-gate #define HVIO_MSI_SETMSIQ 0xcc 148*0Sstevel@tonic-gate #define HVIO_MSI_GETSTATE 0xcd 149*0Sstevel@tonic-gate #define HVIO_MSI_SETSTATE 0xce 150*0Sstevel@tonic-gate 151*0Sstevel@tonic-gate #define HVIO_MSG_GETMSIQ 0xd0 152*0Sstevel@tonic-gate #define HVIO_MSG_SETMSIQ 0xd1 153*0Sstevel@tonic-gate #define HVIO_MSG_GETVALID 0xd2 154*0Sstevel@tonic-gate #define HVIO_MSG_SETVALID 0xd3 155*0Sstevel@tonic-gate 156*0Sstevel@tonic-gate #ifdef SET_MMU_STATS 157*0Sstevel@tonic-gate #define MMU_STAT_AREA 0xfc 158*0Sstevel@tonic-gate #endif /* SET_MMU_STATS */ 159*0Sstevel@tonic-gate 160*0Sstevel@tonic-gate #define HV_NCS_REQUEST 0x110 161*0Sstevel@tonic-gate 162*0Sstevel@tonic-gate /* 163*0Sstevel@tonic-gate * Bits for MMU functions flags argument: 164*0Sstevel@tonic-gate * arg3 of MMU_MAP_ADDR 165*0Sstevel@tonic-gate * arg3 of MMU_DEMAP_CTX 166*0Sstevel@tonic-gate * arg2 of MMU_DEMAP_ALL 167*0Sstevel@tonic-gate */ 168*0Sstevel@tonic-gate #define MAP_DTLB 0x1 169*0Sstevel@tonic-gate #define MAP_ITLB 0x2 170*0Sstevel@tonic-gate 171*0Sstevel@tonic-gate 172*0Sstevel@tonic-gate /* 173*0Sstevel@tonic-gate * Interrupt state manipulation definitions. 174*0Sstevel@tonic-gate */ 175*0Sstevel@tonic-gate 176*0Sstevel@tonic-gate #define HV_INTR_IDLE_STATE 0 177*0Sstevel@tonic-gate #define HV_INTR_RECEIVED_STATE 1 178*0Sstevel@tonic-gate #define HV_INTR_DELIVERED_STATE 2 179*0Sstevel@tonic-gate 180*0Sstevel@tonic-gate #define HV_INTR_NOTVALID 0 181*0Sstevel@tonic-gate #define HV_INTR_VALID 1 182*0Sstevel@tonic-gate 183*0Sstevel@tonic-gate #ifndef _ASM 184*0Sstevel@tonic-gate 185*0Sstevel@tonic-gate /* 186*0Sstevel@tonic-gate * TSB description structure for MMU_TSB_CTX0 and MMU_TSB_CTXNON0. 187*0Sstevel@tonic-gate */ 188*0Sstevel@tonic-gate typedef struct hv_tsb_info { 189*0Sstevel@tonic-gate uint16_t hvtsb_idxpgsz; /* page size used to index TSB */ 190*0Sstevel@tonic-gate uint16_t hvtsb_assoc; /* TSB associativity */ 191*0Sstevel@tonic-gate uint32_t hvtsb_ntte; /* TSB size (#TTE entries) */ 192*0Sstevel@tonic-gate uint32_t hvtsb_ctx_index; /* context reg index */ 193*0Sstevel@tonic-gate uint32_t hvtsb_pgszs; /* sizes in use */ 194*0Sstevel@tonic-gate uint64_t hvtsb_pa; /* real address of TSB base */ 195*0Sstevel@tonic-gate uint64_t hvtsb_rsvd; /* reserved */ 196*0Sstevel@tonic-gate } hv_tsb_info_t; 197*0Sstevel@tonic-gate 198*0Sstevel@tonic-gate #define HVTSB_SHARE_INDEX ((uint32_t)-1) 199*0Sstevel@tonic-gate 200*0Sstevel@tonic-gate #ifdef SET_MMU_STATS 201*0Sstevel@tonic-gate #ifndef TTE4V_NPGSZ 202*0Sstevel@tonic-gate #define TTE4V_NPGSZ 8 203*0Sstevel@tonic-gate #endif /* TTE4V_NPGSZ */ 204*0Sstevel@tonic-gate /* 205*0Sstevel@tonic-gate * MMU statistics structure for MMU_STAT_AREA 206*0Sstevel@tonic-gate */ 207*0Sstevel@tonic-gate struct mmu_stat_one { 208*0Sstevel@tonic-gate uint64_t hit_ctx0[TTE4V_NPGSZ]; 209*0Sstevel@tonic-gate uint64_t hit_ctxn0[TTE4V_NPGSZ]; 210*0Sstevel@tonic-gate uint64_t tsb_miss; 211*0Sstevel@tonic-gate uint64_t tlb_miss; /* miss, no TSB set */ 212*0Sstevel@tonic-gate uint64_t map_ctx0[TTE4V_NPGSZ]; 213*0Sstevel@tonic-gate uint64_t map_ctxn0[TTE4V_NPGSZ]; 214*0Sstevel@tonic-gate }; 215*0Sstevel@tonic-gate 216*0Sstevel@tonic-gate struct mmu_stat { 217*0Sstevel@tonic-gate struct mmu_stat_one immu_stat; 218*0Sstevel@tonic-gate struct mmu_stat_one dmmu_stat; 219*0Sstevel@tonic-gate uint64_t set_ctx0; 220*0Sstevel@tonic-gate uint64_t set_ctxn0; 221*0Sstevel@tonic-gate }; 222*0Sstevel@tonic-gate #endif /* SET_MMU_STATS */ 223*0Sstevel@tonic-gate 224*0Sstevel@tonic-gate #endif /* _ASM */ 225*0Sstevel@tonic-gate 226*0Sstevel@tonic-gate /* 227*0Sstevel@tonic-gate * CPU States 228*0Sstevel@tonic-gate */ 229*0Sstevel@tonic-gate #define CPU_STATE_INVALID 0x0 230*0Sstevel@tonic-gate #define CPU_STATE_IDLE 0x1 /* cpu not started */ 231*0Sstevel@tonic-gate #define CPU_STATE_GUEST 0x2 /* cpu running guest code */ 232*0Sstevel@tonic-gate #define CPU_STATE_ERROR 0x3 /* cpu is in the error state */ 233*0Sstevel@tonic-gate #define CPU_STATE_LAST_PUBLIC CPU_STATE_ERROR /* last valid state */ 234*0Sstevel@tonic-gate 235*0Sstevel@tonic-gate /* 236*0Sstevel@tonic-gate * MMU fault status area 237*0Sstevel@tonic-gate */ 238*0Sstevel@tonic-gate 239*0Sstevel@tonic-gate #define MMFSA_TYPE_ 0x00 /* fault type */ 240*0Sstevel@tonic-gate #define MMFSA_ADDR_ 0x08 /* fault address */ 241*0Sstevel@tonic-gate #define MMFSA_CTX_ 0x10 /* fault context */ 242*0Sstevel@tonic-gate 243*0Sstevel@tonic-gate #define MMFSA_I_ 0x00 /* start of fields for I */ 244*0Sstevel@tonic-gate #define MMFSA_I_TYPE (MMFSA_I_ + MMFSA_TYPE_) /* instruction fault type */ 245*0Sstevel@tonic-gate #define MMFSA_I_ADDR (MMFSA_I_ + MMFSA_ADDR_) /* instruction fault address */ 246*0Sstevel@tonic-gate #define MMFSA_I_CTX (MMFSA_I_ + MMFSA_CTX_) /* instruction fault context */ 247*0Sstevel@tonic-gate 248*0Sstevel@tonic-gate #define MMFSA_D_ 0x40 /* start of fields for D */ 249*0Sstevel@tonic-gate #define MMFSA_D_TYPE (MMFSA_D_ + MMFSA_TYPE_) /* data fault type */ 250*0Sstevel@tonic-gate #define MMFSA_D_ADDR (MMFSA_D_ + MMFSA_ADDR_) /* data fault address */ 251*0Sstevel@tonic-gate #define MMFSA_D_CTX (MMFSA_D_ + MMFSA_CTX_) /* data fault context */ 252*0Sstevel@tonic-gate 253*0Sstevel@tonic-gate #define MMFSA_F_FMISS 1 /* fast miss */ 254*0Sstevel@tonic-gate #define MMFSA_F_FPROT 2 /* fast protection */ 255*0Sstevel@tonic-gate #define MMFSA_F_MISS 3 /* mmu miss */ 256*0Sstevel@tonic-gate #define MMFSA_F_INVRA 4 /* invalid RA */ 257*0Sstevel@tonic-gate #define MMFSA_F_PRIV 5 /* privilege violation */ 258*0Sstevel@tonic-gate #define MMFSA_F_PROT 6 /* protection violation */ 259*0Sstevel@tonic-gate #define MMFSA_F_NFO 7 /* NFO access */ 260*0Sstevel@tonic-gate #define MMFSA_F_SOPG 8 /* so page */ 261*0Sstevel@tonic-gate #define MMFSA_F_INVVA 9 /* invalid VA */ 262*0Sstevel@tonic-gate #define MMFSA_F_INVASI 10 /* invalid ASI */ 263*0Sstevel@tonic-gate #define MMFSA_F_NCATM 11 /* non-cacheable atomic */ 264*0Sstevel@tonic-gate #define MMFSA_F_PRVACT 12 /* privileged action */ 265*0Sstevel@tonic-gate #define MMFSA_F_WPT 13 /* watchpoint hit */ 266*0Sstevel@tonic-gate #define MMFSA_F_UNALIGN 14 /* unaligned access */ 267*0Sstevel@tonic-gate #define MMFSA_F_INVPGSZ 15 /* invalid page size */ 268*0Sstevel@tonic-gate 269*0Sstevel@tonic-gate #define MMFSA_SIZE 0x80 /* in bytes, 64 byte aligned */ 270*0Sstevel@tonic-gate 271*0Sstevel@tonic-gate /* 272*0Sstevel@tonic-gate * MMU fault status - MMFSA_IFS and MMFSA_DFS 273*0Sstevel@tonic-gate */ 274*0Sstevel@tonic-gate #define MMFS_FV 0x00000001 275*0Sstevel@tonic-gate #define MMFS_OW 0x00000002 276*0Sstevel@tonic-gate #define MMFS_W 0x00000004 277*0Sstevel@tonic-gate #define MMFS_PR 0x00000008 278*0Sstevel@tonic-gate #define MMFS_CT 0x00000030 279*0Sstevel@tonic-gate #define MMFS_E 0x00000040 280*0Sstevel@tonic-gate #define MMFS_FT 0x00003f80 281*0Sstevel@tonic-gate #define MMFS_ME 0x00004000 282*0Sstevel@tonic-gate #define MMFS_TM 0x00008000 283*0Sstevel@tonic-gate #define MMFS_ASI 0x00ff0000 284*0Sstevel@tonic-gate #define MMFS_NF 0x01000000 285*0Sstevel@tonic-gate 286*0Sstevel@tonic-gate /* 287*0Sstevel@tonic-gate * DMA sync parameter definitions 288*0Sstevel@tonic-gate */ 289*0Sstevel@tonic-gate #define HVIO_DMA_SYNC_DIR_TO_DEV 0x01 290*0Sstevel@tonic-gate #define HVIO_DMA_SYNC_DIR_FROM_DEV 0x02 291*0Sstevel@tonic-gate 292*0Sstevel@tonic-gate #ifndef _ASM 293*0Sstevel@tonic-gate 294*0Sstevel@tonic-gate extern uint64_t hv_mmu_map_perm_addr(void *, int, uint64_t, int); 295*0Sstevel@tonic-gate extern uint64_t hv_mmu_unmap_perm_addr(void *, int, int); 296*0Sstevel@tonic-gate extern uint64_t hv_set_ctx0(uint64_t, uint64_t); 297*0Sstevel@tonic-gate extern uint64_t hv_set_ctxnon0(uint64_t, uint64_t); 298*0Sstevel@tonic-gate #ifdef SET_MMU_STATS 299*0Sstevel@tonic-gate extern uint64_t hv_mmu_set_stat_area(uint64_t, uint64_t); 300*0Sstevel@tonic-gate #endif /* SET_MMU_STATS */ 301*0Sstevel@tonic-gate 302*0Sstevel@tonic-gate extern uint64_t hv_cpu_qconf(int queue, uint64_t paddr, int size); 303*0Sstevel@tonic-gate extern uint64_t hv_cpu_yield(); 304*0Sstevel@tonic-gate 305*0Sstevel@tonic-gate extern uint64_t hv_cpu_state(uint64_t cpuid, uint64_t *cpu_state); 306*0Sstevel@tonic-gate extern uint64_t hv_mem_scrub(uint64_t real_addr, uint64_t length, 307*0Sstevel@tonic-gate uint64_t *scrubbed_len); 308*0Sstevel@tonic-gate extern uint64_t hv_mem_sync(uint64_t real_addr, uint64_t length, 309*0Sstevel@tonic-gate uint64_t *flushed_len); 310*0Sstevel@tonic-gate 311*0Sstevel@tonic-gate extern uint64_t hv_service_recv(uint64_t s_id, uint64_t buf_pa, 312*0Sstevel@tonic-gate uint64_t size, uint64_t *recv_bytes); 313*0Sstevel@tonic-gate extern uint64_t hv_service_send(uint64_t s_id, uint64_t buf_pa, 314*0Sstevel@tonic-gate uint64_t size, uint64_t *send_bytes); 315*0Sstevel@tonic-gate extern uint64_t hv_service_getstatus(uint64_t s_id, uint64_t *vreg); 316*0Sstevel@tonic-gate extern uint64_t hv_service_clrstatus(uint64_t s_id, uint64_t bits); 317*0Sstevel@tonic-gate 318*0Sstevel@tonic-gate extern uint64_t hv_mach_desc(uint64_t buffer_ra, uint64_t *buffer_sizep); 319*0Sstevel@tonic-gate 320*0Sstevel@tonic-gate extern uint64_t hv_ttrace_buf_info(uint64_t *, uint64_t *); 321*0Sstevel@tonic-gate extern uint64_t hv_ttrace_buf_conf(uint64_t, uint64_t, uint64_t *); 322*0Sstevel@tonic-gate extern uint64_t hv_ttrace_enable(uint64_t, uint64_t *); 323*0Sstevel@tonic-gate extern uint64_t hv_ttrace_freeze(uint64_t, uint64_t *); 324*0Sstevel@tonic-gate extern uint64_t hv_dump_buf_update(uint64_t, uint64_t, uint64_t *); 325*0Sstevel@tonic-gate 326*0Sstevel@tonic-gate extern int64_t hv_cnputchar(uint8_t); 327*0Sstevel@tonic-gate extern int64_t hv_cngetchar(uint8_t *); 328*0Sstevel@tonic-gate 329*0Sstevel@tonic-gate extern uint64_t hv_tod_get(uint64_t *seconds); 330*0Sstevel@tonic-gate extern uint64_t hv_tod_set(uint64_t); 331*0Sstevel@tonic-gate 332*0Sstevel@tonic-gate extern uint64_t hvio_intr_devino_to_sysino(uint64_t dev_hdl, uint32_t devino, 333*0Sstevel@tonic-gate uint64_t *sysino); 334*0Sstevel@tonic-gate extern uint64_t hvio_intr_getvalid(uint64_t sysino, 335*0Sstevel@tonic-gate int *intr_valid_state); 336*0Sstevel@tonic-gate extern uint64_t hvio_intr_setvalid(uint64_t sysino, 337*0Sstevel@tonic-gate int intr_valid_state); 338*0Sstevel@tonic-gate extern uint64_t hvio_intr_getstate(uint64_t sysino, 339*0Sstevel@tonic-gate int *intr_state); 340*0Sstevel@tonic-gate extern uint64_t hvio_intr_setstate(uint64_t sysino, int intr_state); 341*0Sstevel@tonic-gate extern uint64_t hvio_intr_gettarget(uint64_t sysino, uint32_t *cpuid); 342*0Sstevel@tonic-gate extern uint64_t hvio_intr_settarget(uint64_t sysino, uint32_t cpuid); 343*0Sstevel@tonic-gate #endif 344*0Sstevel@tonic-gate 345*0Sstevel@tonic-gate #ifdef __cplusplus 346*0Sstevel@tonic-gate } 347*0Sstevel@tonic-gate #endif 348*0Sstevel@tonic-gate 349*0Sstevel@tonic-gate #endif /* _SYS_HYPERVISOR_API_H */ 350