1*0Sstevel@tonic-gate /* 2*0Sstevel@tonic-gate * CDDL HEADER START 3*0Sstevel@tonic-gate * 4*0Sstevel@tonic-gate * The contents of this file are subject to the terms of the 5*0Sstevel@tonic-gate * Common Development and Distribution License, Version 1.0 only 6*0Sstevel@tonic-gate * (the "License"). You may not use this file except in compliance 7*0Sstevel@tonic-gate * with the License. 8*0Sstevel@tonic-gate * 9*0Sstevel@tonic-gate * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10*0Sstevel@tonic-gate * or http://www.opensolaris.org/os/licensing. 11*0Sstevel@tonic-gate * See the License for the specific language governing permissions 12*0Sstevel@tonic-gate * and limitations under the License. 13*0Sstevel@tonic-gate * 14*0Sstevel@tonic-gate * When distributing Covered Code, include this CDDL HEADER in each 15*0Sstevel@tonic-gate * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16*0Sstevel@tonic-gate * If applicable, add the following below this CDDL HEADER, with the 17*0Sstevel@tonic-gate * fields enclosed by brackets "[]" replaced with your own identifying 18*0Sstevel@tonic-gate * information: Portions Copyright [yyyy] [name of copyright owner] 19*0Sstevel@tonic-gate * 20*0Sstevel@tonic-gate * CDDL HEADER END 21*0Sstevel@tonic-gate */ 22*0Sstevel@tonic-gate /* 23*0Sstevel@tonic-gate * Copyright 2005 Sun Microsystems, Inc. All rights reserved. 24*0Sstevel@tonic-gate * Use is subject to license terms. 25*0Sstevel@tonic-gate */ 26*0Sstevel@tonic-gate 27*0Sstevel@tonic-gate #pragma ident "%Z%%M% %I% %E% SMI" 28*0Sstevel@tonic-gate 29*0Sstevel@tonic-gate #include <sys/types.h> 30*0Sstevel@tonic-gate #include <sys/machsystm.h> 31*0Sstevel@tonic-gate #include <sys/cmp.h> 32*0Sstevel@tonic-gate #include <sys/chip.h> 33*0Sstevel@tonic-gate 34*0Sstevel@tonic-gate /* 35*0Sstevel@tonic-gate * Note: For now assume the chip ID as 0 for all the cpus until additional 36*0Sstevel@tonic-gate * information is available via machine description table 37*0Sstevel@tonic-gate */ 38*0Sstevel@tonic-gate 39*0Sstevel@tonic-gate /* 40*0Sstevel@tonic-gate * Returns 1 if cpuid is CMP-capable, 0 otherwise. 41*0Sstevel@tonic-gate */ 42*0Sstevel@tonic-gate /*ARGSUSED*/ 43*0Sstevel@tonic-gate int 44*0Sstevel@tonic-gate cmp_cpu_is_cmp(processorid_t cpuid) 45*0Sstevel@tonic-gate { 46*0Sstevel@tonic-gate return (0); 47*0Sstevel@tonic-gate } 48*0Sstevel@tonic-gate 49*0Sstevel@tonic-gate /* 50*0Sstevel@tonic-gate * Indicate that this core (cpuid) resides on the chip indicated by chipid. 51*0Sstevel@tonic-gate * Called during boot and DR add. 52*0Sstevel@tonic-gate */ 53*0Sstevel@tonic-gate /*ARGSUSED*/ 54*0Sstevel@tonic-gate void 55*0Sstevel@tonic-gate cmp_add_cpu(chipid_t chipid, processorid_t cpuid) 56*0Sstevel@tonic-gate { 57*0Sstevel@tonic-gate } 58*0Sstevel@tonic-gate 59*0Sstevel@tonic-gate /* 60*0Sstevel@tonic-gate * Indicate that this core (cpuid) is being DR removed. 61*0Sstevel@tonic-gate */ 62*0Sstevel@tonic-gate /*ARGSUSED*/ 63*0Sstevel@tonic-gate void 64*0Sstevel@tonic-gate cmp_delete_cpu(processorid_t cpuid) 65*0Sstevel@tonic-gate { 66*0Sstevel@tonic-gate } 67*0Sstevel@tonic-gate 68*0Sstevel@tonic-gate /* 69*0Sstevel@tonic-gate * Called when cpuid is being onlined or offlined. If the offlined 70*0Sstevel@tonic-gate * processor is CMP-capable then current target of the CMP Error Steering 71*0Sstevel@tonic-gate * Register is set to either the lowest numbered on-line sibling core, if 72*0Sstevel@tonic-gate * one exists, or else to this core. 73*0Sstevel@tonic-gate */ 74*0Sstevel@tonic-gate /*ARGSUSED*/ 75*0Sstevel@tonic-gate void 76*0Sstevel@tonic-gate cmp_error_resteer(processorid_t cpuid) 77*0Sstevel@tonic-gate { 78*0Sstevel@tonic-gate } 79*0Sstevel@tonic-gate 80*0Sstevel@tonic-gate /* 81*0Sstevel@tonic-gate * Return 0, shortterm workaround until MD table is updated 82*0Sstevel@tonic-gate * to provide cpu-chip mapping 83*0Sstevel@tonic-gate */ 84*0Sstevel@tonic-gate 85*0Sstevel@tonic-gate /*ARGSUSED*/ 86*0Sstevel@tonic-gate chipid_t 87*0Sstevel@tonic-gate cmp_cpu_to_chip(processorid_t cpuid) 88*0Sstevel@tonic-gate { 89*0Sstevel@tonic-gate return (0); 90*0Sstevel@tonic-gate } 91*0Sstevel@tonic-gate 92*0Sstevel@tonic-gate /* 93*0Sstevel@tonic-gate * Return a chip "id" for the given cpu_t 94*0Sstevel@tonic-gate * cpu_t's residing on the same physical processor 95*0Sstevel@tonic-gate * should map to the same "id" 96*0Sstevel@tonic-gate */ 97*0Sstevel@tonic-gate chipid_t 98*0Sstevel@tonic-gate chip_plat_get_chipid(cpu_t *cp) 99*0Sstevel@tonic-gate { 100*0Sstevel@tonic-gate return (cmp_cpu_to_chip(cp->cpu_id)); 101*0Sstevel@tonic-gate } 102*0Sstevel@tonic-gate 103*0Sstevel@tonic-gate /*ARGSUSED*/ 104*0Sstevel@tonic-gate void 105*0Sstevel@tonic-gate chip_plat_define_chip(cpu_t *cp, chip_def_t *cd) 106*0Sstevel@tonic-gate { 107*0Sstevel@tonic-gate cd->chipd_type = CHIP_DEFAULT; 108*0Sstevel@tonic-gate 109*0Sstevel@tonic-gate /* 110*0Sstevel@tonic-gate * Define any needed adjustment of rechoose_interval 111*0Sstevel@tonic-gate * For now, all chips use the default. This 112*0Sstevel@tonic-gate * will change with future processors. 113*0Sstevel@tonic-gate */ 114*0Sstevel@tonic-gate cd->chipd_rechoose_adj = 0; 115*0Sstevel@tonic-gate } 116