xref: /onnv-gate/usr/src/uts/sun4v/cpu/generic.c (revision 4203:8d20ed8bb872)
10Sstevel@tonic-gate /*
20Sstevel@tonic-gate  * CDDL HEADER START
30Sstevel@tonic-gate  *
40Sstevel@tonic-gate  * The contents of this file are subject to the terms of the
51991Sheppo  * Common Development and Distribution License (the "License").
61991Sheppo  * You may not use this file except in compliance with the License.
70Sstevel@tonic-gate  *
80Sstevel@tonic-gate  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
90Sstevel@tonic-gate  * or http://www.opensolaris.org/os/licensing.
100Sstevel@tonic-gate  * See the License for the specific language governing permissions
110Sstevel@tonic-gate  * and limitations under the License.
120Sstevel@tonic-gate  *
130Sstevel@tonic-gate  * When distributing Covered Code, include this CDDL HEADER in each
140Sstevel@tonic-gate  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
150Sstevel@tonic-gate  * If applicable, add the following below this CDDL HEADER, with the
160Sstevel@tonic-gate  * fields enclosed by brackets "[]" replaced with your own identifying
170Sstevel@tonic-gate  * information: Portions Copyright [yyyy] [name of copyright owner]
180Sstevel@tonic-gate  *
190Sstevel@tonic-gate  * CDDL HEADER END
200Sstevel@tonic-gate  */
21*4203Srsmaeda 
220Sstevel@tonic-gate /*
233434Sesaxe  * Copyright 2007 Sun Microsystems, Inc.  All rights reserved.
240Sstevel@tonic-gate  * Use is subject to license terms.
250Sstevel@tonic-gate  */
260Sstevel@tonic-gate 
270Sstevel@tonic-gate #pragma ident	"%Z%%M%	%I%	%E% SMI"
280Sstevel@tonic-gate 
290Sstevel@tonic-gate #include <sys/types.h>
300Sstevel@tonic-gate #include <sys/systm.h>
310Sstevel@tonic-gate #include <sys/archsystm.h>
320Sstevel@tonic-gate #include <sys/machparam.h>
330Sstevel@tonic-gate #include <sys/machsystm.h>
340Sstevel@tonic-gate #include <sys/cpu.h>
350Sstevel@tonic-gate #include <sys/elf_SPARC.h>
360Sstevel@tonic-gate #include <vm/hat_sfmmu.h>
370Sstevel@tonic-gate #include <vm/page.h>
380Sstevel@tonic-gate #include <sys/cpuvar.h>
390Sstevel@tonic-gate #include <sys/async.h>
400Sstevel@tonic-gate #include <sys/cmn_err.h>
410Sstevel@tonic-gate #include <sys/debug.h>
420Sstevel@tonic-gate #include <sys/dditypes.h>
430Sstevel@tonic-gate #include <sys/sunddi.h>
440Sstevel@tonic-gate #include <sys/cpu_module.h>
450Sstevel@tonic-gate #include <sys/prom_debug.h>
460Sstevel@tonic-gate #include <sys/vmsystm.h>
470Sstevel@tonic-gate #include <sys/prom_plat.h>
480Sstevel@tonic-gate #include <sys/sysmacros.h>
490Sstevel@tonic-gate #include <sys/intreg.h>
500Sstevel@tonic-gate #include <sys/machtrap.h>
510Sstevel@tonic-gate #include <sys/ontrap.h>
520Sstevel@tonic-gate #include <sys/ivintr.h>
530Sstevel@tonic-gate #include <sys/atomic.h>
540Sstevel@tonic-gate #include <sys/panic.h>
550Sstevel@tonic-gate #include <sys/dtrace.h>
560Sstevel@tonic-gate #include <vm/seg_spt.h>
571991Sheppo #include <sys/simulate.h>
581991Sheppo #include <sys/fault.h>
590Sstevel@tonic-gate 
600Sstevel@tonic-gate 
610Sstevel@tonic-gate uint_t root_phys_addr_lo_mask = 0xffffffffU;
620Sstevel@tonic-gate 
630Sstevel@tonic-gate void
640Sstevel@tonic-gate cpu_setup(void)
650Sstevel@tonic-gate {
660Sstevel@tonic-gate 	extern int mmu_exported_pagesize_mask;
671991Sheppo 	char *generic_isa_set[] = {
681991Sheppo 	    "sparcv9+vis",
691991Sheppo 	    "sparcv8plus+vis",
701991Sheppo 	    NULL
711991Sheppo 	};
721991Sheppo 
731991Sheppo 	/*
741991Sheppo 	 * The setup common to all CPU modules is done in cpu_setup_common
751991Sheppo 	 * routine.
761991Sheppo 	 */
771991Sheppo 	cpu_setup_common(generic_isa_set);
780Sstevel@tonic-gate 
790Sstevel@tonic-gate 	cache |= (CACHE_PTAG | CACHE_IOCOHERENT);
800Sstevel@tonic-gate 
811991Sheppo 	if (broken_md_flag) {
821991Sheppo 		/*
831991Sheppo 		 * Turn on the missing bits supported by sun4v architecture in
841991Sheppo 		 * MMU pagesize mask returned by MD.
851991Sheppo 		 */
861991Sheppo 		mmu_exported_pagesize_mask |= DEFAULT_SUN4V_MMU_PAGESIZE_MASK;
871991Sheppo 	} else {
881991Sheppo 		/*
891991Sheppo 		 * According to sun4v architecture each processor must
901991Sheppo 		 * support 8K, 64K and 4M page sizes. If any of the page
911991Sheppo 		 * size is missing from page size mask, then panic.
921991Sheppo 		 */
931991Sheppo 		if ((mmu_exported_pagesize_mask &
941991Sheppo 		    DEFAULT_SUN4V_MMU_PAGESIZE_MASK) !=
951991Sheppo 		    DEFAULT_SUN4V_MMU_PAGESIZE_MASK)
961991Sheppo 			cmn_err(CE_PANIC, "machine description"
971991Sheppo 			    " does not have required sun4v page sizes"
981991Sheppo 			    " 8K, 64K and 4M: MD mask is 0x%x",
991991Sheppo 			    mmu_exported_pagesize_mask);
1000Sstevel@tonic-gate 	}
1010Sstevel@tonic-gate 
1020Sstevel@tonic-gate 	/*
1031991Sheppo 	 * If processor supports the subset of full 64-bit virtual
1041991Sheppo 	 * address space, then set VA hole accordingly.
1050Sstevel@tonic-gate 	 */
1061991Sheppo 	if (va_bits < VA_ADDRESS_SPACE_BITS) {
1071991Sheppo 		hole_start = (caddr_t)(1ull << (va_bits - 1));
1081991Sheppo 		hole_end = (caddr_t)(0ull - (1ull << (va_bits - 1)));
1091991Sheppo 	} else {
1101991Sheppo 		hole_start = hole_end = 0;
1111991Sheppo 	}
1120Sstevel@tonic-gate }
1130Sstevel@tonic-gate 
1140Sstevel@tonic-gate void
1150Sstevel@tonic-gate cpu_fiximp(struct cpu_node *cpunode)
1160Sstevel@tonic-gate {
1170Sstevel@tonic-gate 	/*
1181991Sheppo 	 * The Cache node is optional in MD. Therefore in case "Cache"
1191991Sheppo 	 * does not exists in MD, set the default L2 cache associativity,
1201991Sheppo 	 * size, linesize for generic CPU module.
1210Sstevel@tonic-gate 	 */
1221991Sheppo 	if (cpunode->ecache_size == 0)
1231991Sheppo 		cpunode->ecache_size = 0x100000;
1241991Sheppo 	if (cpunode->ecache_linesize == 0)
1251991Sheppo 		cpunode->ecache_linesize = 64;
1261991Sheppo 	if (cpunode->ecache_associativity == 0)
1271991Sheppo 		cpunode->ecache_associativity = 1;
1280Sstevel@tonic-gate }
1290Sstevel@tonic-gate 
1300Sstevel@tonic-gate void
1310Sstevel@tonic-gate dtrace_flush_sec(uintptr_t addr)
1320Sstevel@tonic-gate {
1330Sstevel@tonic-gate 	pfn_t pfn;
1340Sstevel@tonic-gate 	proc_t *procp = ttoproc(curthread);
1350Sstevel@tonic-gate 	page_t *pp;
1360Sstevel@tonic-gate 	caddr_t va;
1370Sstevel@tonic-gate 
1380Sstevel@tonic-gate 	pfn = hat_getpfnum(procp->p_as->a_hat, (void *)addr);
1390Sstevel@tonic-gate 	if (pfn != -1) {
1400Sstevel@tonic-gate 		ASSERT(pf_is_memory(pfn));
1410Sstevel@tonic-gate 		pp = page_numtopp_noreclaim(pfn, SE_SHARED);
1420Sstevel@tonic-gate 		if (pp != NULL) {
1430Sstevel@tonic-gate 			va = ppmapin(pp, PROT_READ | PROT_WRITE, (void *)addr);
1440Sstevel@tonic-gate 			/* sparc needs 8-byte align */
1450Sstevel@tonic-gate 			doflush((caddr_t)((uintptr_t)va & -8l));
1460Sstevel@tonic-gate 			ppmapout(va);
1470Sstevel@tonic-gate 			page_unlock(pp);
1480Sstevel@tonic-gate 		}
1490Sstevel@tonic-gate 	}
1500Sstevel@tonic-gate }
1510Sstevel@tonic-gate 
1520Sstevel@tonic-gate void
153*4203Srsmaeda cpu_map_exec_units(struct cpu *cp)
1540Sstevel@tonic-gate {
155*4203Srsmaeda 	ASSERT(MUTEX_HELD(&cpu_lock));
156*4203Srsmaeda 
157220Sesaxe 	/*
1583434Sesaxe 	 * The cpu_ipipe and cpu_fpu fields are initialized based on
159*4203Srsmaeda 	 * the execution unit sharing information from the MD. They
160*4203Srsmaeda 	 * default to the CPU id in the absence of such information.
161220Sesaxe 	 */
1621991Sheppo 	cp->cpu_m.cpu_ipipe = cpunodes[cp->cpu_id].exec_unit_mapping;
1631991Sheppo 	if (cp->cpu_m.cpu_ipipe == NO_EU_MAPPING_FOUND)
1641991Sheppo 		cp->cpu_m.cpu_ipipe = (id_t)(cp->cpu_id);
1653434Sesaxe 
1663434Sesaxe 	cp->cpu_m.cpu_fpu = cpunodes[cp->cpu_id].fpu_mapping;
1673434Sesaxe 	if (cp->cpu_m.cpu_fpu == NO_EU_MAPPING_FOUND)
1683434Sesaxe 		cp->cpu_m.cpu_fpu = (id_t)(cp->cpu_id);
1693434Sesaxe 
1703434Sesaxe 	cp->cpu_m.cpu_core = (id_t)(cp->cpu_id);
1710Sstevel@tonic-gate }
1720Sstevel@tonic-gate 
1730Sstevel@tonic-gate void
174*4203Srsmaeda cpu_init_private(struct cpu *cp)
1750Sstevel@tonic-gate {
176*4203Srsmaeda 	cpu_map_exec_units(cp);
1770Sstevel@tonic-gate }
1780Sstevel@tonic-gate 
179*4203Srsmaeda /*ARGSUSED*/
180*4203Srsmaeda void
181*4203Srsmaeda cpu_uninit_private(struct cpu *cp)
182*4203Srsmaeda {}
183*4203Srsmaeda 
1840Sstevel@tonic-gate /*
1850Sstevel@tonic-gate  * Invalidate a TSB. Since this needs to work on all sun4v
1860Sstevel@tonic-gate  * architecture compliant processors, we use the old method of
1870Sstevel@tonic-gate  * walking the TSB, setting each tag to TSBTAG_INVALID.
1880Sstevel@tonic-gate  */
1890Sstevel@tonic-gate void
1900Sstevel@tonic-gate cpu_inv_tsb(caddr_t tsb_base, uint_t tsb_bytes)
1910Sstevel@tonic-gate {
1920Sstevel@tonic-gate 	struct tsbe *tsbaddr;
1930Sstevel@tonic-gate 
1940Sstevel@tonic-gate 	for (tsbaddr = (struct tsbe *)tsb_base;
1950Sstevel@tonic-gate 	    (uintptr_t)tsbaddr < (uintptr_t)(tsb_base + tsb_bytes);
1960Sstevel@tonic-gate 	    tsbaddr++) {
1970Sstevel@tonic-gate 		tsbaddr->tte_tag.tag_inthi = TSBTAG_INVALID;
1980Sstevel@tonic-gate 	}
1990Sstevel@tonic-gate }
2001050Sgirish 
2011050Sgirish /*
2021991Sheppo  * Sun4v kernel must emulate code a generic sun4v processor may not support
2031991Sheppo  * i.e. VIS1 and VIS2.
2041991Sheppo  */
2051991Sheppo #define	IS_FLOAT(i) (((i) & 0x1000000) != 0)
2061991Sheppo #define	IS_IBIT_SET(x)	(x & 0x2000)
2071991Sheppo #define	IS_VIS1(op, op3)(op == 2 && op3 == 0x36)
2081991Sheppo #define	IS_PARTIAL_OR_SHORT_FLOAT_LD_ST(op, op3, asi)		\
2091991Sheppo 		(op == 3 && (op3 == IOP_V8_LDDFA ||		\
2101991Sheppo 		op3 == IOP_V8_STDFA) &&	asi > ASI_SNFL)
2111991Sheppo int
2121991Sheppo vis1_partial_support(struct regs *rp, k_siginfo_t *siginfo, uint_t *fault)
2131991Sheppo {
2141991Sheppo 	char *badaddr;
2151991Sheppo 	int instr;
2161991Sheppo 	uint_t	optype, op3, asi;
2171991Sheppo 	uint_t	rd, ignor;
2181991Sheppo 
2191991Sheppo 	if (!USERMODE(rp->r_tstate))
2201991Sheppo 		return (-1);
2211991Sheppo 
2221991Sheppo 	instr = fetch_user_instr((caddr_t)rp->r_pc);
2231991Sheppo 
2241991Sheppo 	rd = (instr >> 25) & 0x1f;
2251991Sheppo 	optype = (instr >> 30) & 0x3;
2261991Sheppo 	op3 = (instr >> 19) & 0x3f;
2271991Sheppo 	ignor = (instr >> 5) & 0xff;
2281991Sheppo 	if (IS_IBIT_SET(instr)) {
2291991Sheppo 		asi = (uint32_t)((rp->r_tstate >> TSTATE_ASI_SHIFT) &
2301991Sheppo 		    TSTATE_ASI_MASK);
2311991Sheppo 	} else {
2321991Sheppo 		asi = ignor;
2331991Sheppo 	}
2341991Sheppo 
2351991Sheppo 	if (!IS_VIS1(optype, op3) &&
2361991Sheppo 	    !IS_PARTIAL_OR_SHORT_FLOAT_LD_ST(optype, op3, asi)) {
2371991Sheppo 		return (-1);
2381991Sheppo 	}
2391991Sheppo 	switch (simulate_unimp(rp, &badaddr)) {
2401991Sheppo 	case SIMU_RETRY:
2411991Sheppo 		break;	/* regs are already set up */
2421991Sheppo 		/*NOTREACHED*/
2431991Sheppo 
2441991Sheppo 	case SIMU_SUCCESS:
2451991Sheppo 		/*
2461991Sheppo 		 * skip the successfully
2471991Sheppo 		 * simulated instruction
2481991Sheppo 		 */
2491991Sheppo 		rp->r_pc = rp->r_npc;
2501991Sheppo 		rp->r_npc += 4;
2511991Sheppo 		break;
2521991Sheppo 		/*NOTREACHED*/
2531991Sheppo 
2541991Sheppo 	case SIMU_FAULT:
2551991Sheppo 		siginfo->si_signo = SIGSEGV;
2561991Sheppo 		siginfo->si_code = SEGV_MAPERR;
2571991Sheppo 		siginfo->si_addr = badaddr;
2581991Sheppo 		*fault = FLTBOUNDS;
2591991Sheppo 		break;
2601991Sheppo 
2611991Sheppo 	case SIMU_DZERO:
2621991Sheppo 		siginfo->si_signo = SIGFPE;
2631991Sheppo 		siginfo->si_code = FPE_INTDIV;
2641991Sheppo 		siginfo->si_addr = (caddr_t)rp->r_pc;
2651991Sheppo 		*fault = FLTIZDIV;
2661991Sheppo 		break;
2671991Sheppo 
2681991Sheppo 	case SIMU_UNALIGN:
2691991Sheppo 		siginfo->si_signo = SIGBUS;
2701991Sheppo 		siginfo->si_code = BUS_ADRALN;
2711991Sheppo 		siginfo->si_addr = badaddr;
2721991Sheppo 		*fault = FLTACCESS;
2731991Sheppo 		break;
2741991Sheppo 
2751991Sheppo 	case SIMU_ILLEGAL:
2761991Sheppo 	default:
2771991Sheppo 		siginfo->si_signo = SIGILL;
2781991Sheppo 		op3 = (instr >> 19) & 0x3F;
2791991Sheppo 		if ((IS_FLOAT(instr) && (op3 == IOP_V8_STQFA) ||
2801991Sheppo 		    (op3 == IOP_V8_STDFA)))
2811991Sheppo 			siginfo->si_code = ILL_ILLADR;
2821991Sheppo 		else
2831991Sheppo 			siginfo->si_code = ILL_ILLOPC;
2841991Sheppo 		siginfo->si_addr = (caddr_t)rp->r_pc;
2851991Sheppo 		*fault = FLTILL;
2861991Sheppo 		break;
2871991Sheppo 	}
2881991Sheppo 	return (0);
2891991Sheppo }
2901991Sheppo 
2911991Sheppo /*
2921050Sgirish  * Trapstat support for generic sun4v processor
2931050Sgirish  */
2941050Sgirish int
2951050Sgirish cpu_trapstat_conf(int cmd)
2961050Sgirish {
2971050Sgirish 	int status;
2981050Sgirish 
2991050Sgirish 	switch (cmd) {
3001050Sgirish 	case CPU_TSTATCONF_INIT:
3011050Sgirish 	case CPU_TSTATCONF_FINI:
3021050Sgirish 	case CPU_TSTATCONF_ENABLE:
3031050Sgirish 	case CPU_TSTATCONF_DISABLE:
3041050Sgirish 		status = ENOTSUP;
3051050Sgirish 		break;
3061050Sgirish 
3071050Sgirish 	default:
3081050Sgirish 		status = EINVAL;
3091050Sgirish 		break;
3101050Sgirish 	}
3111050Sgirish 	return (status);
3121050Sgirish }
3131050Sgirish 
3141050Sgirish /*ARGSUSED*/
3151050Sgirish void
3161050Sgirish cpu_trapstat_data(void *buf, uint_t tstat_pgszs)
3171050Sgirish {
3181050Sgirish }
319