1*0Sstevel@tonic-gate /* 2*0Sstevel@tonic-gate * CDDL HEADER START 3*0Sstevel@tonic-gate * 4*0Sstevel@tonic-gate * The contents of this file are subject to the terms of the 5*0Sstevel@tonic-gate * Common Development and Distribution License, Version 1.0 only 6*0Sstevel@tonic-gate * (the "License"). You may not use this file except in compliance 7*0Sstevel@tonic-gate * with the License. 8*0Sstevel@tonic-gate * 9*0Sstevel@tonic-gate * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10*0Sstevel@tonic-gate * or http://www.opensolaris.org/os/licensing. 11*0Sstevel@tonic-gate * See the License for the specific language governing permissions 12*0Sstevel@tonic-gate * and limitations under the License. 13*0Sstevel@tonic-gate * 14*0Sstevel@tonic-gate * When distributing Covered Code, include this CDDL HEADER in each 15*0Sstevel@tonic-gate * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16*0Sstevel@tonic-gate * If applicable, add the following below this CDDL HEADER, with the 17*0Sstevel@tonic-gate * fields enclosed by brackets "[]" replaced with your own identifying 18*0Sstevel@tonic-gate * information: Portions Copyright [yyyy] [name of copyright owner] 19*0Sstevel@tonic-gate * 20*0Sstevel@tonic-gate * CDDL HEADER END 21*0Sstevel@tonic-gate */ 22*0Sstevel@tonic-gate /* 23*0Sstevel@tonic-gate * Copyright 2005 Sun Microsystems, Inc. All rights reserved. 24*0Sstevel@tonic-gate * Use is subject to license terms. 25*0Sstevel@tonic-gate */ 26*0Sstevel@tonic-gate 27*0Sstevel@tonic-gate #pragma ident "%Z%%M% %I% %E% SMI" 28*0Sstevel@tonic-gate 29*0Sstevel@tonic-gate #include <sys/types.h> 30*0Sstevel@tonic-gate #include <sys/systm.h> 31*0Sstevel@tonic-gate #include <sys/archsystm.h> 32*0Sstevel@tonic-gate #include <sys/machparam.h> 33*0Sstevel@tonic-gate #include <sys/machsystm.h> 34*0Sstevel@tonic-gate #include <sys/cpu.h> 35*0Sstevel@tonic-gate #include <sys/elf_SPARC.h> 36*0Sstevel@tonic-gate #include <vm/hat_sfmmu.h> 37*0Sstevel@tonic-gate #include <vm/page.h> 38*0Sstevel@tonic-gate #include <sys/cpuvar.h> 39*0Sstevel@tonic-gate #include <sys/async.h> 40*0Sstevel@tonic-gate #include <sys/cmn_err.h> 41*0Sstevel@tonic-gate #include <sys/debug.h> 42*0Sstevel@tonic-gate #include <sys/dditypes.h> 43*0Sstevel@tonic-gate #include <sys/sunddi.h> 44*0Sstevel@tonic-gate #include <sys/cpu_module.h> 45*0Sstevel@tonic-gate #include <sys/prom_debug.h> 46*0Sstevel@tonic-gate #include <sys/vmsystm.h> 47*0Sstevel@tonic-gate #include <sys/prom_plat.h> 48*0Sstevel@tonic-gate #include <sys/sysmacros.h> 49*0Sstevel@tonic-gate #include <sys/intreg.h> 50*0Sstevel@tonic-gate #include <sys/machtrap.h> 51*0Sstevel@tonic-gate #include <sys/ontrap.h> 52*0Sstevel@tonic-gate #include <sys/ivintr.h> 53*0Sstevel@tonic-gate #include <sys/atomic.h> 54*0Sstevel@tonic-gate #include <sys/panic.h> 55*0Sstevel@tonic-gate #include <sys/dtrace.h> 56*0Sstevel@tonic-gate #include <vm/seg_spt.h> 57*0Sstevel@tonic-gate 58*0Sstevel@tonic-gate #define S_VAC_SIZE MMU_PAGESIZE /* XXXQ? */ 59*0Sstevel@tonic-gate 60*0Sstevel@tonic-gate /* 61*0Sstevel@tonic-gate * Maximum number of contexts 62*0Sstevel@tonic-gate */ 63*0Sstevel@tonic-gate #define MAX_NCTXS (1 << 13) 64*0Sstevel@tonic-gate 65*0Sstevel@tonic-gate uint_t root_phys_addr_lo_mask = 0xffffffffU; 66*0Sstevel@tonic-gate 67*0Sstevel@tonic-gate void 68*0Sstevel@tonic-gate cpu_setup(void) 69*0Sstevel@tonic-gate { 70*0Sstevel@tonic-gate extern int at_flags; 71*0Sstevel@tonic-gate extern int disable_delay_tlb_flush, delay_tlb_flush; 72*0Sstevel@tonic-gate extern int mmu_exported_pagesize_mask; 73*0Sstevel@tonic-gate extern int get_cpu_pagesizes(void); 74*0Sstevel@tonic-gate 75*0Sstevel@tonic-gate cache |= (CACHE_PTAG | CACHE_IOCOHERENT); 76*0Sstevel@tonic-gate 77*0Sstevel@tonic-gate at_flags = EF_SPARC_32PLUS | EF_SPARC_SUN_US1; /* XXXQ */ 78*0Sstevel@tonic-gate 79*0Sstevel@tonic-gate /* 80*0Sstevel@tonic-gate * Use the maximum number of contexts available for Spitfire unless 81*0Sstevel@tonic-gate * it has been tuned for debugging. 82*0Sstevel@tonic-gate * We are checking against 0 here since this value can be patched 83*0Sstevel@tonic-gate * while booting. It can not be patched via /etc/system since it 84*0Sstevel@tonic-gate * will be patched too late and thus cause the system to panic. 85*0Sstevel@tonic-gate */ 86*0Sstevel@tonic-gate if (nctxs == 0) 87*0Sstevel@tonic-gate nctxs = MAX_NCTXS; 88*0Sstevel@tonic-gate 89*0Sstevel@tonic-gate if (use_page_coloring) { 90*0Sstevel@tonic-gate do_pg_coloring = 1; 91*0Sstevel@tonic-gate if (use_virtual_coloring) 92*0Sstevel@tonic-gate do_virtual_coloring = 1; 93*0Sstevel@tonic-gate } 94*0Sstevel@tonic-gate /* 95*0Sstevel@tonic-gate * Initalize supported page sizes information before the PD. 96*0Sstevel@tonic-gate * If no information is available, then initialize the 97*0Sstevel@tonic-gate * mmu_exported_pagesize_mask to a reasonable value for that processor. 98*0Sstevel@tonic-gate */ 99*0Sstevel@tonic-gate mmu_exported_pagesize_mask = get_cpu_pagesizes(); 100*0Sstevel@tonic-gate if (mmu_exported_pagesize_mask <= 0) { 101*0Sstevel@tonic-gate mmu_exported_pagesize_mask = (1 << TTE8K) | (1 << TTE64K) | 102*0Sstevel@tonic-gate (1 << TTE4M); 103*0Sstevel@tonic-gate } 104*0Sstevel@tonic-gate 105*0Sstevel@tonic-gate /* 106*0Sstevel@tonic-gate * Tune pp_slots to use up to 1/8th of the tlb entries. 107*0Sstevel@tonic-gate */ 108*0Sstevel@tonic-gate pp_slots = MIN(8, MAXPP_SLOTS); 109*0Sstevel@tonic-gate 110*0Sstevel@tonic-gate /* 111*0Sstevel@tonic-gate * Block stores invalidate all pages of the d$ so pagecopy 112*0Sstevel@tonic-gate * et. al. do not need virtual translations with virtual 113*0Sstevel@tonic-gate * coloring taken into consideration. 114*0Sstevel@tonic-gate */ 115*0Sstevel@tonic-gate pp_consistent_coloring = 0; 116*0Sstevel@tonic-gate isa_list = 117*0Sstevel@tonic-gate "sparcv9+vis sparcv9 " 118*0Sstevel@tonic-gate "sparcv8plus+vis sparcv8plus " 119*0Sstevel@tonic-gate "sparcv8 sparcv8-fsmuld sparcv7 sparc"; 120*0Sstevel@tonic-gate 121*0Sstevel@tonic-gate /* 122*0Sstevel@tonic-gate * On Spitfire, there's a hole in the address space 123*0Sstevel@tonic-gate * that we must never map (the hardware only support 44-bits of 124*0Sstevel@tonic-gate * virtual address). Later CPUs are expected to have wider 125*0Sstevel@tonic-gate * supported address ranges. 126*0Sstevel@tonic-gate * 127*0Sstevel@tonic-gate * See address map on p23 of the UltraSPARC 1 user's manual. 128*0Sstevel@tonic-gate */ 129*0Sstevel@tonic-gate /* XXXQ get from machine description */ 130*0Sstevel@tonic-gate hole_start = (caddr_t)0x80000000000ull; 131*0Sstevel@tonic-gate hole_end = (caddr_t)0xfffff80000000000ull; 132*0Sstevel@tonic-gate 133*0Sstevel@tonic-gate /* 134*0Sstevel@tonic-gate * The kpm mapping window. 135*0Sstevel@tonic-gate * kpm_size: 136*0Sstevel@tonic-gate * The size of a single kpm range. 137*0Sstevel@tonic-gate * The overall size will be: kpm_size * vac_colors. 138*0Sstevel@tonic-gate * kpm_vbase: 139*0Sstevel@tonic-gate * The virtual start address of the kpm range within the kernel 140*0Sstevel@tonic-gate * virtual address space. kpm_vbase has to be kpm_size aligned. 141*0Sstevel@tonic-gate */ 142*0Sstevel@tonic-gate kpm_size = (size_t)(2ull * 1024 * 1024 * 1024 * 1024); /* 2TB */ 143*0Sstevel@tonic-gate kpm_size_shift = 41; 144*0Sstevel@tonic-gate kpm_vbase = (caddr_t)0xfffffa0000000000ull; /* 16EB - 6TB */ 145*0Sstevel@tonic-gate 146*0Sstevel@tonic-gate /* 147*0Sstevel@tonic-gate * The traptrace code uses either %tick or %stick for 148*0Sstevel@tonic-gate * timestamping. We have %stick so we can use it. 149*0Sstevel@tonic-gate */ 150*0Sstevel@tonic-gate traptrace_use_stick = 1; 151*0Sstevel@tonic-gate 152*0Sstevel@tonic-gate /* 153*0Sstevel@tonic-gate * sun4v provides demap_all 154*0Sstevel@tonic-gate */ 155*0Sstevel@tonic-gate if (!disable_delay_tlb_flush) 156*0Sstevel@tonic-gate delay_tlb_flush = 1; 157*0Sstevel@tonic-gate } 158*0Sstevel@tonic-gate 159*0Sstevel@tonic-gate /* 160*0Sstevel@tonic-gate * Set the magic constants of the implementation. 161*0Sstevel@tonic-gate */ 162*0Sstevel@tonic-gate void 163*0Sstevel@tonic-gate cpu_fiximp(struct cpu_node *cpunode) 164*0Sstevel@tonic-gate { 165*0Sstevel@tonic-gate extern int vac_size, vac_shift; 166*0Sstevel@tonic-gate extern uint_t vac_mask; 167*0Sstevel@tonic-gate int i, a; 168*0Sstevel@tonic-gate 169*0Sstevel@tonic-gate /* 170*0Sstevel@tonic-gate * The assumption here is that fillsysinfo will eventually 171*0Sstevel@tonic-gate * have code to fill this info in from the PD. 172*0Sstevel@tonic-gate * We hard code this for now. 173*0Sstevel@tonic-gate * Once the PD access library is done this code 174*0Sstevel@tonic-gate * might need to be changed to get the info from the PD 175*0Sstevel@tonic-gate */ 176*0Sstevel@tonic-gate /* 177*0Sstevel@tonic-gate * Page Coloring defaults for sun4v 178*0Sstevel@tonic-gate */ 179*0Sstevel@tonic-gate ecache_setsize = 0x100000; 180*0Sstevel@tonic-gate ecache_alignsize = 64; 181*0Sstevel@tonic-gate cpunode->ecache_setsize = 0x100000; 182*0Sstevel@tonic-gate 183*0Sstevel@tonic-gate vac_size = S_VAC_SIZE; 184*0Sstevel@tonic-gate vac_mask = MMU_PAGEMASK & (vac_size - 1); 185*0Sstevel@tonic-gate i = 0; a = vac_size; 186*0Sstevel@tonic-gate while (a >>= 1) 187*0Sstevel@tonic-gate ++i; 188*0Sstevel@tonic-gate vac_shift = i; 189*0Sstevel@tonic-gate shm_alignment = vac_size; 190*0Sstevel@tonic-gate vac = 0; 191*0Sstevel@tonic-gate } 192*0Sstevel@tonic-gate 193*0Sstevel@tonic-gate void 194*0Sstevel@tonic-gate dtrace_flush_sec(uintptr_t addr) 195*0Sstevel@tonic-gate { 196*0Sstevel@tonic-gate pfn_t pfn; 197*0Sstevel@tonic-gate proc_t *procp = ttoproc(curthread); 198*0Sstevel@tonic-gate page_t *pp; 199*0Sstevel@tonic-gate caddr_t va; 200*0Sstevel@tonic-gate 201*0Sstevel@tonic-gate pfn = hat_getpfnum(procp->p_as->a_hat, (void *)addr); 202*0Sstevel@tonic-gate if (pfn != -1) { 203*0Sstevel@tonic-gate ASSERT(pf_is_memory(pfn)); 204*0Sstevel@tonic-gate pp = page_numtopp_noreclaim(pfn, SE_SHARED); 205*0Sstevel@tonic-gate if (pp != NULL) { 206*0Sstevel@tonic-gate va = ppmapin(pp, PROT_READ | PROT_WRITE, (void *)addr); 207*0Sstevel@tonic-gate /* sparc needs 8-byte align */ 208*0Sstevel@tonic-gate doflush((caddr_t)((uintptr_t)va & -8l)); 209*0Sstevel@tonic-gate ppmapout(va); 210*0Sstevel@tonic-gate page_unlock(pp); 211*0Sstevel@tonic-gate } 212*0Sstevel@tonic-gate } 213*0Sstevel@tonic-gate } 214*0Sstevel@tonic-gate 215*0Sstevel@tonic-gate void 216*0Sstevel@tonic-gate cpu_init_private(struct cpu *cp) 217*0Sstevel@tonic-gate { 218*0Sstevel@tonic-gate } 219*0Sstevel@tonic-gate 220*0Sstevel@tonic-gate void 221*0Sstevel@tonic-gate cpu_uninit_private(struct cpu *cp) 222*0Sstevel@tonic-gate { 223*0Sstevel@tonic-gate } 224*0Sstevel@tonic-gate 225*0Sstevel@tonic-gate /* 226*0Sstevel@tonic-gate * Invalidate a TSB. Since this needs to work on all sun4v 227*0Sstevel@tonic-gate * architecture compliant processors, we use the old method of 228*0Sstevel@tonic-gate * walking the TSB, setting each tag to TSBTAG_INVALID. 229*0Sstevel@tonic-gate */ 230*0Sstevel@tonic-gate void 231*0Sstevel@tonic-gate cpu_inv_tsb(caddr_t tsb_base, uint_t tsb_bytes) 232*0Sstevel@tonic-gate { 233*0Sstevel@tonic-gate struct tsbe *tsbaddr; 234*0Sstevel@tonic-gate 235*0Sstevel@tonic-gate for (tsbaddr = (struct tsbe *)tsb_base; 236*0Sstevel@tonic-gate (uintptr_t)tsbaddr < (uintptr_t)(tsb_base + tsb_bytes); 237*0Sstevel@tonic-gate tsbaddr++) { 238*0Sstevel@tonic-gate tsbaddr->tte_tag.tag_inthi = TSBTAG_INVALID; 239*0Sstevel@tonic-gate } 240*0Sstevel@tonic-gate } 241