1*0Sstevel@tonic-gate /*
2*0Sstevel@tonic-gate * CDDL HEADER START
3*0Sstevel@tonic-gate *
4*0Sstevel@tonic-gate * The contents of this file are subject to the terms of the
5*0Sstevel@tonic-gate * Common Development and Distribution License, Version 1.0 only
6*0Sstevel@tonic-gate * (the "License"). You may not use this file except in compliance
7*0Sstevel@tonic-gate * with the License.
8*0Sstevel@tonic-gate *
9*0Sstevel@tonic-gate * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
10*0Sstevel@tonic-gate * or http://www.opensolaris.org/os/licensing.
11*0Sstevel@tonic-gate * See the License for the specific language governing permissions
12*0Sstevel@tonic-gate * and limitations under the License.
13*0Sstevel@tonic-gate *
14*0Sstevel@tonic-gate * When distributing Covered Code, include this CDDL HEADER in each
15*0Sstevel@tonic-gate * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
16*0Sstevel@tonic-gate * If applicable, add the following below this CDDL HEADER, with the
17*0Sstevel@tonic-gate * fields enclosed by brackets "[]" replaced with your own identifying
18*0Sstevel@tonic-gate * information: Portions Copyright [yyyy] [name of copyright owner]
19*0Sstevel@tonic-gate *
20*0Sstevel@tonic-gate * CDDL HEADER END
21*0Sstevel@tonic-gate */
22*0Sstevel@tonic-gate /*
23*0Sstevel@tonic-gate * Copyright 2005 Sun Microsystems, Inc. All rights reserved.
24*0Sstevel@tonic-gate * Use is subject to license terms.
25*0Sstevel@tonic-gate */
26*0Sstevel@tonic-gate
27*0Sstevel@tonic-gate #pragma ident "%Z%%M% %I% %E% SMI"
28*0Sstevel@tonic-gate
29*0Sstevel@tonic-gate #include <sys/param.h>
30*0Sstevel@tonic-gate #include <sys/systm.h>
31*0Sstevel@tonic-gate #include <sys/sysmacros.h>
32*0Sstevel@tonic-gate #include <sys/sunddi.h>
33*0Sstevel@tonic-gate #include <sys/esunddi.h>
34*0Sstevel@tonic-gate #include <sys/platform_module.h>
35*0Sstevel@tonic-gate #include <sys/errno.h>
36*0Sstevel@tonic-gate
37*0Sstevel@tonic-gate /*
38*0Sstevel@tonic-gate * 1535D+ IDE Interface Control Register Index
39*0Sstevel@tonic-gate */
40*0Sstevel@tonic-gate #define IDEIC_RINDEX (0x58)
41*0Sstevel@tonic-gate
42*0Sstevel@tonic-gate int (*p2get_mem_unum)(int, uint64_t, char *, int, int *);
43*0Sstevel@tonic-gate
44*0Sstevel@tonic-gate void
startup_platform(void)45*0Sstevel@tonic-gate startup_platform(void)
46*0Sstevel@tonic-gate {
47*0Sstevel@tonic-gate }
48*0Sstevel@tonic-gate
49*0Sstevel@tonic-gate int
set_platform_tsb_spares(void)50*0Sstevel@tonic-gate set_platform_tsb_spares(void)
51*0Sstevel@tonic-gate {
52*0Sstevel@tonic-gate return (0);
53*0Sstevel@tonic-gate }
54*0Sstevel@tonic-gate
55*0Sstevel@tonic-gate void
set_platform_defaults(void)56*0Sstevel@tonic-gate set_platform_defaults(void)
57*0Sstevel@tonic-gate {
58*0Sstevel@tonic-gate }
59*0Sstevel@tonic-gate
60*0Sstevel@tonic-gate /*
61*0Sstevel@tonic-gate * Definitions for accessing the pci config space of the ISA node
62*0Sstevel@tonic-gate * of Southbridge.
63*0Sstevel@tonic-gate */
64*0Sstevel@tonic-gate #define TACO_ISA_PATHNAME "/pci@1e,600000/isa@7"
65*0Sstevel@tonic-gate static ddi_acc_handle_t isa_handle; /* handle for ISA pci space */
66*0Sstevel@tonic-gate
67*0Sstevel@tonic-gate
68*0Sstevel@tonic-gate void
load_platform_drivers(void)69*0Sstevel@tonic-gate load_platform_drivers(void)
70*0Sstevel@tonic-gate {
71*0Sstevel@tonic-gate dev_info_t *dip; /* dip of the ISA driver */
72*0Sstevel@tonic-gate
73*0Sstevel@tonic-gate /*
74*0Sstevel@tonic-gate * Install power driver which handles the power button.
75*0Sstevel@tonic-gate */
76*0Sstevel@tonic-gate if (i_ddi_attach_hw_nodes("power") != DDI_SUCCESS)
77*0Sstevel@tonic-gate cmn_err(CE_WARN, "Failed to install \"power\" driver.");
78*0Sstevel@tonic-gate (void) ddi_hold_driver(ddi_name_to_major("power"));
79*0Sstevel@tonic-gate
80*0Sstevel@tonic-gate /*
81*0Sstevel@tonic-gate * It is OK to return error because 'us' driver is not available
82*0Sstevel@tonic-gate * in all clusters (e.g. missing in Core cluster).
83*0Sstevel@tonic-gate */
84*0Sstevel@tonic-gate (void) i_ddi_attach_hw_nodes("us");
85*0Sstevel@tonic-gate
86*0Sstevel@tonic-gate if (i_ddi_attach_hw_nodes("grbeep") != DDI_SUCCESS)
87*0Sstevel@tonic-gate cmn_err(CE_WARN, "Failed to install \"beep\" driver.");
88*0Sstevel@tonic-gate
89*0Sstevel@tonic-gate
90*0Sstevel@tonic-gate /*
91*0Sstevel@tonic-gate * mc-us3i must stay loaded for plat_get_mem_unum()
92*0Sstevel@tonic-gate */
93*0Sstevel@tonic-gate if (i_ddi_attach_hw_nodes("mc-us3i") != DDI_SUCCESS)
94*0Sstevel@tonic-gate cmn_err(CE_WARN, "mc-us3i driver failed to install");
95*0Sstevel@tonic-gate (void) ddi_hold_driver(ddi_name_to_major("mc-us3i"));
96*0Sstevel@tonic-gate
97*0Sstevel@tonic-gate /*
98*0Sstevel@tonic-gate * Install ISA driver. This is required for the southbridge IDE
99*0Sstevel@tonic-gate * workaround - to reset the IDE channel during IDE bus reset.
100*0Sstevel@tonic-gate * Panic the system in case ISA driver could not be loaded or
101*0Sstevel@tonic-gate * any problem in accessing its pci config space. Since the register
102*0Sstevel@tonic-gate * to reset the channel for IDE is in ISA config space!.
103*0Sstevel@tonic-gate */
104*0Sstevel@tonic-gate
105*0Sstevel@tonic-gate dip = e_ddi_hold_devi_by_path(TACO_ISA_PATHNAME, 0);
106*0Sstevel@tonic-gate if (dip == NULL) {
107*0Sstevel@tonic-gate cmn_err(CE_PANIC, "Could not install the ISA driver\n");
108*0Sstevel@tonic-gate return;
109*0Sstevel@tonic-gate }
110*0Sstevel@tonic-gate
111*0Sstevel@tonic-gate if (pci_config_setup(dip, &isa_handle) != DDI_SUCCESS) {
112*0Sstevel@tonic-gate cmn_err(CE_PANIC, "Could not get the config space of ISA\n");
113*0Sstevel@tonic-gate return;
114*0Sstevel@tonic-gate }
115*0Sstevel@tonic-gate }
116*0Sstevel@tonic-gate
117*0Sstevel@tonic-gate /*
118*0Sstevel@tonic-gate * This routine provides a workaround for a bug in the SB chip which
119*0Sstevel@tonic-gate * can cause data corruption. Will be invoked from the IDE HBA driver for
120*0Sstevel@tonic-gate * Acer SouthBridge at the time of IDE bus reset.
121*0Sstevel@tonic-gate */
122*0Sstevel@tonic-gate /*ARGSUSED*/
123*0Sstevel@tonic-gate int
plat_ide_chipreset(dev_info_t * dip,int chno)124*0Sstevel@tonic-gate plat_ide_chipreset(dev_info_t *dip, int chno)
125*0Sstevel@tonic-gate {
126*0Sstevel@tonic-gate uint8_t val;
127*0Sstevel@tonic-gate int ret = DDI_SUCCESS;
128*0Sstevel@tonic-gate
129*0Sstevel@tonic-gate if (isa_handle == NULL) {
130*0Sstevel@tonic-gate return (DDI_FAILURE);
131*0Sstevel@tonic-gate }
132*0Sstevel@tonic-gate
133*0Sstevel@tonic-gate val = pci_config_get8(isa_handle, IDEIC_RINDEX);
134*0Sstevel@tonic-gate /*
135*0Sstevel@tonic-gate * The dip passed as the argument is not used here.
136*0Sstevel@tonic-gate * This will be needed for platforms which have multiple on-board SB,
137*0Sstevel@tonic-gate * The dip passed will be used to match the corresponding ISA node.
138*0Sstevel@tonic-gate */
139*0Sstevel@tonic-gate switch (chno) {
140*0Sstevel@tonic-gate case 0:
141*0Sstevel@tonic-gate /*
142*0Sstevel@tonic-gate * First disable the primary channel then re-enable it.
143*0Sstevel@tonic-gate * As per ALI no wait should be required in between have
144*0Sstevel@tonic-gate * given 1ms delay in between to be on safer side.
145*0Sstevel@tonic-gate * bit 2 of register 0x58 when 0 disable the channel 0.
146*0Sstevel@tonic-gate * bit 2 of register 0x58 when 1 enables the channel 0.
147*0Sstevel@tonic-gate */
148*0Sstevel@tonic-gate pci_config_put8(isa_handle, IDEIC_RINDEX, val & 0xFB);
149*0Sstevel@tonic-gate drv_usecwait(1000);
150*0Sstevel@tonic-gate pci_config_put8(isa_handle, IDEIC_RINDEX, val);
151*0Sstevel@tonic-gate break;
152*0Sstevel@tonic-gate case 1:
153*0Sstevel@tonic-gate /*
154*0Sstevel@tonic-gate * bit 3 of register 0x58 when 0 disable the channel 1.
155*0Sstevel@tonic-gate * bit 3 of register 0x58 when 1 enables the channel 1.
156*0Sstevel@tonic-gate */
157*0Sstevel@tonic-gate pci_config_put8(isa_handle, IDEIC_RINDEX, val & 0xF7);
158*0Sstevel@tonic-gate drv_usecwait(1000);
159*0Sstevel@tonic-gate pci_config_put8(isa_handle, IDEIC_RINDEX, val);
160*0Sstevel@tonic-gate break;
161*0Sstevel@tonic-gate default:
162*0Sstevel@tonic-gate /*
163*0Sstevel@tonic-gate * Unknown channel number passed. Return failure.
164*0Sstevel@tonic-gate */
165*0Sstevel@tonic-gate ret = DDI_FAILURE;
166*0Sstevel@tonic-gate }
167*0Sstevel@tonic-gate
168*0Sstevel@tonic-gate return (ret);
169*0Sstevel@tonic-gate }
170*0Sstevel@tonic-gate
171*0Sstevel@tonic-gate
172*0Sstevel@tonic-gate /*ARGSUSED*/
173*0Sstevel@tonic-gate int
plat_cpu_poweron(struct cpu * cp)174*0Sstevel@tonic-gate plat_cpu_poweron(struct cpu *cp)
175*0Sstevel@tonic-gate {
176*0Sstevel@tonic-gate return (ENOTSUP); /* not supported on this platform */
177*0Sstevel@tonic-gate }
178*0Sstevel@tonic-gate
179*0Sstevel@tonic-gate /*ARGSUSED*/
180*0Sstevel@tonic-gate int
plat_cpu_poweroff(struct cpu * cp)181*0Sstevel@tonic-gate plat_cpu_poweroff(struct cpu *cp)
182*0Sstevel@tonic-gate {
183*0Sstevel@tonic-gate return (ENOTSUP); /* not supported on this platform */
184*0Sstevel@tonic-gate }
185*0Sstevel@tonic-gate
186*0Sstevel@tonic-gate /*ARGSUSED*/
187*0Sstevel@tonic-gate void
plat_freelist_process(int mnode)188*0Sstevel@tonic-gate plat_freelist_process(int mnode)
189*0Sstevel@tonic-gate {
190*0Sstevel@tonic-gate }
191*0Sstevel@tonic-gate
192*0Sstevel@tonic-gate char *platform_module_list[] = {
193*0Sstevel@tonic-gate "m1535ppm",
194*0Sstevel@tonic-gate "jbusppm",
195*0Sstevel@tonic-gate "ics951601",
196*0Sstevel@tonic-gate "ppm",
197*0Sstevel@tonic-gate (char *)0
198*0Sstevel@tonic-gate };
199*0Sstevel@tonic-gate
200*0Sstevel@tonic-gate /*ARGSUSED*/
201*0Sstevel@tonic-gate void
plat_tod_fault(enum tod_fault_type tod_bad)202*0Sstevel@tonic-gate plat_tod_fault(enum tod_fault_type tod_bad)
203*0Sstevel@tonic-gate {
204*0Sstevel@tonic-gate }
205*0Sstevel@tonic-gate
206*0Sstevel@tonic-gate /*ARGSUSED*/
207*0Sstevel@tonic-gate int
plat_get_mem_unum(int synd_code,uint64_t flt_addr,int flt_bus_id,int flt_in_memory,ushort_t flt_status,char * buf,int buflen,int * lenp)208*0Sstevel@tonic-gate plat_get_mem_unum(int synd_code, uint64_t flt_addr, int flt_bus_id,
209*0Sstevel@tonic-gate int flt_in_memory, ushort_t flt_status, char *buf, int buflen, int *lenp)
210*0Sstevel@tonic-gate {
211*0Sstevel@tonic-gate if (flt_in_memory && (p2get_mem_unum != NULL))
212*0Sstevel@tonic-gate return (p2get_mem_unum(synd_code, P2ALIGN(flt_addr, 8),
213*0Sstevel@tonic-gate buf, buflen, lenp));
214*0Sstevel@tonic-gate else
215*0Sstevel@tonic-gate return (ENOTSUP);
216*0Sstevel@tonic-gate }
217*0Sstevel@tonic-gate
218*0Sstevel@tonic-gate /*ARGSUSED*/
219*0Sstevel@tonic-gate int
plat_get_cpu_unum(int cpuid,char * buf,int buflen,int * lenp)220*0Sstevel@tonic-gate plat_get_cpu_unum(int cpuid, char *buf, int buflen, int *lenp)
221*0Sstevel@tonic-gate {
222*0Sstevel@tonic-gate if (snprintf(buf, buflen, "MB") >= buflen) {
223*0Sstevel@tonic-gate return (ENOSPC);
224*0Sstevel@tonic-gate } else {
225*0Sstevel@tonic-gate *lenp = strlen(buf);
226*0Sstevel@tonic-gate return (0);
227*0Sstevel@tonic-gate }
228*0Sstevel@tonic-gate }
229