1*0Sstevel@tonic-gate /* 2*0Sstevel@tonic-gate * CDDL HEADER START 3*0Sstevel@tonic-gate * 4*0Sstevel@tonic-gate * The contents of this file are subject to the terms of the 5*0Sstevel@tonic-gate * Common Development and Distribution License, Version 1.0 only 6*0Sstevel@tonic-gate * (the "License"). You may not use this file except in compliance 7*0Sstevel@tonic-gate * with the License. 8*0Sstevel@tonic-gate * 9*0Sstevel@tonic-gate * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10*0Sstevel@tonic-gate * or http://www.opensolaris.org/os/licensing. 11*0Sstevel@tonic-gate * See the License for the specific language governing permissions 12*0Sstevel@tonic-gate * and limitations under the License. 13*0Sstevel@tonic-gate * 14*0Sstevel@tonic-gate * When distributing Covered Code, include this CDDL HEADER in each 15*0Sstevel@tonic-gate * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16*0Sstevel@tonic-gate * If applicable, add the following below this CDDL HEADER, with the 17*0Sstevel@tonic-gate * fields enclosed by brackets "[]" replaced with your own identifying 18*0Sstevel@tonic-gate * information: Portions Copyright [yyyy] [name of copyright owner] 19*0Sstevel@tonic-gate * 20*0Sstevel@tonic-gate * CDDL HEADER END 21*0Sstevel@tonic-gate */ 22*0Sstevel@tonic-gate /* 23*0Sstevel@tonic-gate * Copyright 2005 Sun Microsystems, Inc. All rights reserved. 24*0Sstevel@tonic-gate * Use is subject to license terms. 25*0Sstevel@tonic-gate */ 26*0Sstevel@tonic-gate 27*0Sstevel@tonic-gate #ifndef _SYS_PCI_VAR_H 28*0Sstevel@tonic-gate #define _SYS_PCI_VAR_H 29*0Sstevel@tonic-gate 30*0Sstevel@tonic-gate #pragma ident "%Z%%M% %I% %E% SMI" 31*0Sstevel@tonic-gate 32*0Sstevel@tonic-gate #ifdef __cplusplus 33*0Sstevel@tonic-gate extern "C" { 34*0Sstevel@tonic-gate #endif 35*0Sstevel@tonic-gate 36*0Sstevel@tonic-gate /* 37*0Sstevel@tonic-gate * The following typedef is used to represent a 38*0Sstevel@tonic-gate * 1275 "bus-range" property of a PCI Bus node. 39*0Sstevel@tonic-gate */ 40*0Sstevel@tonic-gate typedef struct bus_range { 41*0Sstevel@tonic-gate uint32_t lo; 42*0Sstevel@tonic-gate uint32_t hi; 43*0Sstevel@tonic-gate } pci_bus_range_t; 44*0Sstevel@tonic-gate 45*0Sstevel@tonic-gate /* 46*0Sstevel@tonic-gate * The following typedef is used to represent a 47*0Sstevel@tonic-gate * 1275 "reg" property of a PCI nexus. 48*0Sstevel@tonic-gate */ 49*0Sstevel@tonic-gate typedef struct pci_nexus_regspec { 50*0Sstevel@tonic-gate uint64_t phys_addr; 51*0Sstevel@tonic-gate uint64_t size; 52*0Sstevel@tonic-gate } pci_nexus_regspec_t; 53*0Sstevel@tonic-gate 54*0Sstevel@tonic-gate /* 55*0Sstevel@tonic-gate * The following typedef is used to represent an entry in the "ranges" 56*0Sstevel@tonic-gate * property of a device node. 57*0Sstevel@tonic-gate */ 58*0Sstevel@tonic-gate typedef struct ranges { 59*0Sstevel@tonic-gate uint32_t child_high; 60*0Sstevel@tonic-gate uint32_t child_mid; 61*0Sstevel@tonic-gate uint32_t child_low; 62*0Sstevel@tonic-gate uint32_t parent_high; 63*0Sstevel@tonic-gate uint32_t parent_low; 64*0Sstevel@tonic-gate uint32_t size_high; 65*0Sstevel@tonic-gate uint32_t size_low; 66*0Sstevel@tonic-gate } pci_ranges_t; 67*0Sstevel@tonic-gate 68*0Sstevel@tonic-gate typedef enum { PSYCHO, SCHIZO } pci_bridge_t; 69*0Sstevel@tonic-gate typedef enum { A, B } pci_side_t; 70*0Sstevel@tonic-gate typedef enum { PCI_NEW, PCI_ATTACHED, PCI_DETACHED, PCI_SUSPENDED } pci_state_t; 71*0Sstevel@tonic-gate typedef enum { PCI_PBM_OBJ, PCI_ECC_OBJ, PCI_CB_OBJ } pci_obj_t; 72*0Sstevel@tonic-gate typedef enum { PCI_OBJ_INTR_ADD, PCI_OBJ_INTR_REMOVE } pci_obj_op_t; 73*0Sstevel@tonic-gate 74*0Sstevel@tonic-gate #define PCI_ATTACH_RETCODE(obj, op, err) \ 75*0Sstevel@tonic-gate ((err) ? (obj) << 8 | (op) << 4 | (err) & 0xf : DDI_SUCCESS) 76*0Sstevel@tonic-gate 77*0Sstevel@tonic-gate #define PCI_OTHER_SIDE(side) ((side) ^ 1) 78*0Sstevel@tonic-gate 79*0Sstevel@tonic-gate /* 80*0Sstevel@tonic-gate * the sequence of the chip_type appearance is significant. There are code 81*0Sstevel@tonic-gate * depending on it: CHIP_TYPE(pci_p) < PCI_CHIP_SCHIZO. 82*0Sstevel@tonic-gate */ 83*0Sstevel@tonic-gate typedef enum { 84*0Sstevel@tonic-gate PCI_CHIP_UNIDENTIFIED = 0, 85*0Sstevel@tonic-gate 86*0Sstevel@tonic-gate PCI_CHIP_PSYCHO = 1, 87*0Sstevel@tonic-gate PCI_CHIP_SABRE, 88*0Sstevel@tonic-gate PCI_CHIP_HUMMINGBIRD, 89*0Sstevel@tonic-gate 90*0Sstevel@tonic-gate PCI_CHIP_SCHIZO = 0x11, 91*0Sstevel@tonic-gate PCI_CHIP_XMITS, 92*0Sstevel@tonic-gate PCI_CHIP_TOMATILLO 93*0Sstevel@tonic-gate } pci_chip_id_t; 94*0Sstevel@tonic-gate 95*0Sstevel@tonic-gate /* 96*0Sstevel@tonic-gate * [msb] [lsb] 97*0Sstevel@tonic-gate * 0x00 <chip_type> <version#> <module-revision#> 98*0Sstevel@tonic-gate */ 99*0Sstevel@tonic-gate #define CHIP_ID(t, v, m) (((t) << 16) | ((v) << 8) | (m)) 100*0Sstevel@tonic-gate #define ID_CHIP_TYPE(id) ((id) >> 16) 101*0Sstevel@tonic-gate #define PCI_CHIP_ID(pci_p) ((pci_p)->pci_common_p->pci_chip_id) 102*0Sstevel@tonic-gate #define CHIP_TYPE(pci_p) ID_CHIP_TYPE(PCI_CHIP_ID(pci_p)) 103*0Sstevel@tonic-gate #define CHIP_REV(pci_p) (PCI_CHIP_ID(pci_p) & 0xFF) 104*0Sstevel@tonic-gate #define CHIP_VER(pci_p) ((PCI_CHIP_ID(pci_p) >> 8) & 0xFF) 105*0Sstevel@tonic-gate #define CB_CHIP_TYPE(cb_p) ((cb_p)->cb_pci_cmn_p->pci_chip_id >> 16) 106*0Sstevel@tonic-gate 107*0Sstevel@tonic-gate /* 108*0Sstevel@tonic-gate * pci common soft state structure: 109*0Sstevel@tonic-gate * 110*0Sstevel@tonic-gate * Each psycho or schizo is represented by a pair of pci nodes in the 111*0Sstevel@tonic-gate * device tree. A single pci common soft state is allocated for each 112*0Sstevel@tonic-gate * pair. The UPA (Safari) bus id of the psycho (schizo) is used for 113*0Sstevel@tonic-gate * the instance number. The attach routine uses the existance of a 114*0Sstevel@tonic-gate * pci common soft state structure to determine if one node from the 115*0Sstevel@tonic-gate * pair has been attached. 116*0Sstevel@tonic-gate */ 117*0Sstevel@tonic-gate struct pci_common { 118*0Sstevel@tonic-gate uint_t pci_common_id; 119*0Sstevel@tonic-gate 120*0Sstevel@tonic-gate /* pointers & counters to facilitate attach/detach & suspend/resume */ 121*0Sstevel@tonic-gate ushort_t pci_common_refcnt; /* # of sides suspended + attached */ 122*0Sstevel@tonic-gate ushort_t pci_common_attachcnt; /* # of sides attached */ 123*0Sstevel@tonic-gate uint16_t pci_common_tsb_cookie; /* IOMMU TSB allocation */ 124*0Sstevel@tonic-gate pci_t *pci_p[2]; /* pci soft states of both sides */ 125*0Sstevel@tonic-gate 126*0Sstevel@tonic-gate uint32_t pci_chip_id; /* Bus bridge chip identification */ 127*0Sstevel@tonic-gate 128*0Sstevel@tonic-gate /* Links to functional blocks potentially shared between pci nodes */ 129*0Sstevel@tonic-gate iommu_t *pci_common_iommu_p; 130*0Sstevel@tonic-gate cb_t *pci_common_cb_p; 131*0Sstevel@tonic-gate ib_t *pci_common_ib_p; 132*0Sstevel@tonic-gate ecc_t *pci_common_ecc_p; 133*0Sstevel@tonic-gate 134*0Sstevel@tonic-gate /* 135*0Sstevel@tonic-gate * Performance counters kstat. 136*0Sstevel@tonic-gate */ 137*0Sstevel@tonic-gate pci_cntr_pa_t pci_cmn_uks_pa; 138*0Sstevel@tonic-gate kstat_t *pci_common_uksp; /* ptr to upstream kstat */ 139*0Sstevel@tonic-gate kmutex_t pci_fm_mutex; /* per chip error handling mutex */ 140*0Sstevel@tonic-gate }; 141*0Sstevel@tonic-gate 142*0Sstevel@tonic-gate /* 143*0Sstevel@tonic-gate * pci soft state structure: 144*0Sstevel@tonic-gate * 145*0Sstevel@tonic-gate * Each pci node has a pci soft state structure. 146*0Sstevel@tonic-gate */ 147*0Sstevel@tonic-gate struct pci { 148*0Sstevel@tonic-gate /* 149*0Sstevel@tonic-gate * State flags and mutex: 150*0Sstevel@tonic-gate */ 151*0Sstevel@tonic-gate pci_state_t pci_state; 152*0Sstevel@tonic-gate uint_t pci_soft_state; 153*0Sstevel@tonic-gate #define PCI_SOFT_STATE_OPEN 0x01 154*0Sstevel@tonic-gate #define PCI_SOFT_STATE_OPEN_EXCL 0x02 155*0Sstevel@tonic-gate #define PCI_SOFT_STATE_CLOSED 0x04 156*0Sstevel@tonic-gate uint_t pci_open_count; 157*0Sstevel@tonic-gate uint16_t pci_tsb_cookie; /* IOMMU TSB allocation */ 158*0Sstevel@tonic-gate kmutex_t pci_mutex; 159*0Sstevel@tonic-gate 160*0Sstevel@tonic-gate /* 161*0Sstevel@tonic-gate * Links to other state structures: 162*0Sstevel@tonic-gate */ 163*0Sstevel@tonic-gate pci_common_t *pci_common_p; /* pointer common soft state */ 164*0Sstevel@tonic-gate dev_info_t *pci_dip; /* devinfo structure */ 165*0Sstevel@tonic-gate ib_t *pci_ib_p; /* interrupt block */ 166*0Sstevel@tonic-gate cb_t *pci_cb_p; /* control block */ 167*0Sstevel@tonic-gate pbm_t *pci_pbm_p; /* PBM block */ 168*0Sstevel@tonic-gate iommu_t *pci_iommu_p; /* IOMMU block */ 169*0Sstevel@tonic-gate sc_t *pci_sc_p; /* streaming cache block */ 170*0Sstevel@tonic-gate ecc_t *pci_ecc_p; /* ECC error block */ 171*0Sstevel@tonic-gate 172*0Sstevel@tonic-gate /* 173*0Sstevel@tonic-gate * other state info: 174*0Sstevel@tonic-gate */ 175*0Sstevel@tonic-gate uint_t pci_id; /* UPA (or Safari) device id */ 176*0Sstevel@tonic-gate pci_side_t pci_side; 177*0Sstevel@tonic-gate 178*0Sstevel@tonic-gate /* 179*0Sstevel@tonic-gate * pci device node properties: 180*0Sstevel@tonic-gate */ 181*0Sstevel@tonic-gate pci_bus_range_t pci_bus_range; /* "bus-range" */ 182*0Sstevel@tonic-gate pci_ranges_t *pci_ranges; /* "ranges" data & length */ 183*0Sstevel@tonic-gate int pci_ranges_length; 184*0Sstevel@tonic-gate uint32_t *pci_inos; /* inos from "interrupts" prop */ 185*0Sstevel@tonic-gate int pci_inos_len; /* "interrupts" length */ 186*0Sstevel@tonic-gate int pci_numproxy; /* upa interrupt proxies */ 187*0Sstevel@tonic-gate int pci_thermal_interrupt; /* node has thermal interrupt */ 188*0Sstevel@tonic-gate 189*0Sstevel@tonic-gate /* 190*0Sstevel@tonic-gate * register mapping: 191*0Sstevel@tonic-gate */ 192*0Sstevel@tonic-gate caddr_t pci_address[4]; 193*0Sstevel@tonic-gate ddi_acc_handle_t pci_ac[4]; 194*0Sstevel@tonic-gate 195*0Sstevel@tonic-gate /* Interrupt support */ 196*0Sstevel@tonic-gate int intr_map_size; 197*0Sstevel@tonic-gate struct intr_map *intr_map; 198*0Sstevel@tonic-gate struct intr_map_mask *intr_map_mask; 199*0Sstevel@tonic-gate 200*0Sstevel@tonic-gate /* performance counters */ 201*0Sstevel@tonic-gate pci_cntr_addr_t pci_ks_addr; 202*0Sstevel@tonic-gate kstat_t *pci_ksp; 203*0Sstevel@tonic-gate 204*0Sstevel@tonic-gate /* Hotplug information */ 205*0Sstevel@tonic-gate 206*0Sstevel@tonic-gate boolean_t hotplug_capable; 207*0Sstevel@tonic-gate 208*0Sstevel@tonic-gate /* Fault Management support */ 209*0Sstevel@tonic-gate int pci_fm_cap; 210*0Sstevel@tonic-gate ddi_iblock_cookie_t pci_fm_ibc; 211*0Sstevel@tonic-gate }; 212*0Sstevel@tonic-gate 213*0Sstevel@tonic-gate /* 214*0Sstevel@tonic-gate * PSYCHO and PBM soft state macros: 215*0Sstevel@tonic-gate */ 216*0Sstevel@tonic-gate #define get_pci_soft_state(i) \ 217*0Sstevel@tonic-gate ((pci_t *)ddi_get_soft_state(per_pci_state, (i))) 218*0Sstevel@tonic-gate 219*0Sstevel@tonic-gate #define alloc_pci_soft_state(i) \ 220*0Sstevel@tonic-gate ddi_soft_state_zalloc(per_pci_state, (i)) 221*0Sstevel@tonic-gate 222*0Sstevel@tonic-gate #define free_pci_soft_state(i) \ 223*0Sstevel@tonic-gate ddi_soft_state_free(per_pci_state, (i)) 224*0Sstevel@tonic-gate 225*0Sstevel@tonic-gate #define get_pci_common_soft_state(i) \ 226*0Sstevel@tonic-gate ((pci_common_t *)ddi_get_soft_state(per_pci_common_state, (i))) 227*0Sstevel@tonic-gate 228*0Sstevel@tonic-gate #define alloc_pci_common_soft_state(i) \ 229*0Sstevel@tonic-gate ddi_soft_state_zalloc(per_pci_common_state, (i)) 230*0Sstevel@tonic-gate 231*0Sstevel@tonic-gate #define free_pci_common_soft_state(i) \ 232*0Sstevel@tonic-gate ddi_soft_state_free(per_pci_common_state, (i)) 233*0Sstevel@tonic-gate 234*0Sstevel@tonic-gate #define DEV_TO_SOFTSTATE(dev) ((pci_t *)ddi_get_soft_state(per_pci_state, \ 235*0Sstevel@tonic-gate PCIHP_AP_MINOR_NUM_TO_INSTANCE(getminor(dev)))) 236*0Sstevel@tonic-gate 237*0Sstevel@tonic-gate extern void *per_pci_state; /* per-pbm soft state pointer */ 238*0Sstevel@tonic-gate extern void *per_pci_common_state; /* per-psycho soft state pointer */ 239*0Sstevel@tonic-gate extern kmutex_t pci_global_mutex; /* attach/detach common struct lock */ 240*0Sstevel@tonic-gate extern kmutex_t dvma_active_list_mutex; 241*0Sstevel@tonic-gate 242*0Sstevel@tonic-gate /* 243*0Sstevel@tonic-gate * function prototypes for bus ops routines: 244*0Sstevel@tonic-gate */ 245*0Sstevel@tonic-gate extern int 246*0Sstevel@tonic-gate pci_map(dev_info_t *dip, dev_info_t *rdip, ddi_map_req_t *mp, 247*0Sstevel@tonic-gate off_t offset, off_t len, caddr_t *addrp); 248*0Sstevel@tonic-gate extern int 249*0Sstevel@tonic-gate pci_dma_setup(dev_info_t *dip, dev_info_t *rdip, 250*0Sstevel@tonic-gate ddi_dma_req_t *dmareq, ddi_dma_handle_t *handlep); 251*0Sstevel@tonic-gate extern int 252*0Sstevel@tonic-gate pci_dma_allochdl(dev_info_t *dip, dev_info_t *rdip, ddi_dma_attr_t *attrp, 253*0Sstevel@tonic-gate int (*waitfp)(caddr_t), caddr_t arg, ddi_dma_handle_t *handlep); 254*0Sstevel@tonic-gate extern int 255*0Sstevel@tonic-gate pci_dma_bindhdl(dev_info_t *dip, dev_info_t *rdip, 256*0Sstevel@tonic-gate ddi_dma_handle_t handle, ddi_dma_req_t *dmareq, 257*0Sstevel@tonic-gate ddi_dma_cookie_t *cookiep, uint_t *ccountp); 258*0Sstevel@tonic-gate extern int 259*0Sstevel@tonic-gate pci_dma_unbindhdl(dev_info_t *dip, dev_info_t *rdip, 260*0Sstevel@tonic-gate ddi_dma_handle_t handle); 261*0Sstevel@tonic-gate extern int 262*0Sstevel@tonic-gate pci_dma_flush(dev_info_t *dip, dev_info_t *rdip, 263*0Sstevel@tonic-gate ddi_dma_handle_t handle, off_t off, size_t len, 264*0Sstevel@tonic-gate uint_t cache_flags); 265*0Sstevel@tonic-gate extern int 266*0Sstevel@tonic-gate pci_dma_ctlops(dev_info_t *dip, dev_info_t *rdip, ddi_dma_handle_t handle, 267*0Sstevel@tonic-gate enum ddi_dma_ctlops cmd, off_t *offp, size_t *lenp, caddr_t *objp, 268*0Sstevel@tonic-gate uint_t cache_flags); 269*0Sstevel@tonic-gate extern int 270*0Sstevel@tonic-gate pci_ctlops(dev_info_t *dip, dev_info_t *rdip, 271*0Sstevel@tonic-gate ddi_ctl_enum_t op, void *arg, void *result); 272*0Sstevel@tonic-gate extern int 273*0Sstevel@tonic-gate pci_intr_ops(dev_info_t *dip, dev_info_t *rdip, ddi_intr_op_t intr_op, 274*0Sstevel@tonic-gate ddi_intr_handle_impl_t *handle, void *result); 275*0Sstevel@tonic-gate 276*0Sstevel@tonic-gate #ifdef __cplusplus 277*0Sstevel@tonic-gate } 278*0Sstevel@tonic-gate #endif 279*0Sstevel@tonic-gate 280*0Sstevel@tonic-gate #endif /* _SYS_PCI_VAR_H */ 281